JPH04229796A - Picture delay device - Google Patents

Abstract

PURPOSE:To easily simulate a satellite line or the line with a large delay time and to avoid fog or flicker of a contour in a picture with respect to the picture delay device simulating a transmission line through which a picture signal is sent. CONSTITUTION:A band compression quantity such as delay time and resolution is set to a setting control section 2. When a picture signal from a television camera is inputted to a coder section 1, the coder section 1 digitizes the signal corresponding to the picture element according to the set quantization bit number and gives the digitized picture signal to a delay memory section 3. The delay memory section 3 writes the digital picture signal in the unit of fields or frames. Then after the set delay time, the digital picture signal is read and fed to the decoder section 4, in which the original picture signal is restored and fed to a monitor television receiver. The monitor television receiver is observed to set optionally a parameter according to various transmission conditions of the picture signal to obtain an optimum condition.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image delay device that simulates a transmission path for transmitting image signals.

[0002] When transmitting an image signal captured by a television camera via a transmission line such as a public line, private line, or satellite line, a delay occurs corresponding to the length of the transmission line. Furthermore, since the amount of information that can be transmitted is limited by the transmission capacity of the transmission path, the amount of information to be transmitted is reduced by compressing the band of the image signal by encoding or the like. There is a need for a simulation device that can arbitrarily set the conditions of various transmission paths to find the optimal conditions for an image signal transmitting/receiving device.

0003

2. Description of the Related Art A conventional transmission path simulating device includes a delay circuit such as a memory that provides a delay time of about 1 second, and has a configuration for inputting and outputting data using a standard line interface. In other words, since we are assuming a domestic line such as a public line or a private line, the maximum delay time that can be set is as short as one second, and since we are assuming that the transmission line is a public line, the standard A line interface is provided. Furthermore, the gradation, resolution, etc. of the image signal to be transmitted are fixedly set.

0004

[Problem to be solved by the invention] When transmitting image signals via a satellite line, there are cases where the satellite line connects directly between the satellite and the ground, and cases where the satellite line connects via another communication satellite. In these cases, the delay time varies greatly, and for example, a maximum delay time of about 4 seconds occurs. Furthermore, since the transmission capacity of a satellite line is, for example, about several tens of Mbps, it is necessary to compress the band by high-efficiency encoding or the like on the image signal transmitting side.

However, it is difficult to mount a complex circuit configuration on a satellite due to issues such as space, weight, and radiation. Therefore, measures such as increasing the quantization step of the image signal to reduce the number of bits, or reducing the number of transmission frames by dropping frames are adopted.

[0006] In the conventional configuration, a configuration that provides a large delay as described above has not been realized, and a configuration that simulates various band compression amounts has not been realized. Therefore, there is a drawback that it is not possible to sufficiently simulate the transmission and reception of image signals via a satellite line. Furthermore, since the image signal input/output configuration uses a standard line interface, there is a drawback that image signals from any television camera cannot be input.

[0007] Furthermore, in a configuration that simulates various amounts of band compression, if the amount of transmitted information is reduced by thinning out the image information according to the transmission capacity of the transmission path, the image will become blurred and flicker, making it extremely difficult to see. There were cases where it became. Even if such an image is taken into an image processing device and processed, only meaningless data will be obtained. The reason for such an image is as follows. That is, for example, 1/2 in the vertical direction and 1 in the horizontal direction with respect to the frame.
/2, the resolution will be 1/4, but if this image is updated once per second on the receiving and reproducing side, on the reproducing side, the odd field of one image will be updated 30 times, and the even field will be updated 30 times. It will be played alternately. Therefore, if there is a fast-moving object in the image, the distance traveled in 1/60 seconds will be alternately played back for 1 second on the playback side. This results in an image that is very difficult to see for the human eye.

[0008] The present invention has been made in view of the above points, and it is an object of the present invention to make it possible to easily simulate even satellite lines with large delay times. Another object of the present invention is to realize a configuration that simulates various band compression amounts, and to make the image free from blurred outlines and flickering.

[0009]

The image delay device of the present invention is capable of simulating an image signal transmission path under arbitrary conditions, and will be described with reference to FIG.

A coder section 1 converts an input image signal into a digital signal, a setting control section 2 sets delay time and band compression amount, writes the digital image signal from the coder section 1, and controls the setting of this digital image signal. The image forming apparatus includes a delay memory section 3 which is read out after a delay time set in the delay memory section 2, and a decoder section 2 which converts the digital image signal read out from the delay memory section 3 into an analog image signal and outputs it. .

Further, the setting control section 2 has a configuration for setting parameters including delay time and band compression amount, and the delay memory section 3 includes an image memory, a write control section, and a read control section. The control section writes only valid pixels in the digital image signal to the image memory in synchronization with the synchronization signal of the input image signal, and the readout control section reads the digital image from the image memory according to the setting parameters in the setting control section 2. It has a configuration for controlling signal readout. In that case, for example, the readout control section of the delay memory section (3) reads out the digital image signal written in the image memory according to the parameters set by the setting control section (2) to reduce the resolution in units of fields. It may also be configured to perform control.

The coder section 1 also includes a selection section for a plurality of input image signals, an analog-to-digital conversion section for converting the selected input image signals into digital signals, and an analog-to-digital conversion section for converting the selected input image signals into digital signals according to the setting parameters of the setting control section 2. The apparatus includes a compression processing section that performs band compression processing on the digital image signal converted by the section and adds a control signal indicating the band compression. In that case, the coder section (1) is configured to reduce the resolution of one frame of digital image signals, multiplex and transmit the signals in accordance with the parameters set by the setting control section (2) to reduce the resolution in units of fields. You can also use it as

The decoder section 4 also includes a detection section that detects a control signal included in the digital image signal read out from the delay memory section 3, and restores the digital image signal to its original state based on the control signal detected by this detection section. It has an interpolation processing section and a digital/analog conversion section.

[0014]

[Operation] The delay time, resolution, number of transmission frames, number of quantization bits (gradation), and other band compression amounts are set in the setting control section 2. When an image signal from a television camera is input to the coder section 1, the coder section 1 digitizes it pixel-by-pixel according to the set number of quantization bits, and adds the digital image signal to the delay memory section 3. The delay memory unit 3 includes an image memory, and writes digital image signals in units of fields or frames. Then, after a set delay time, the digital image signal is read out and added to the decoder section 4, where it is returned to the original image signal and added to the monitor television. When processing according to the set number of transmission frames, the fields or frames written to the image memory of the delay memory section 3 are thinned out, or when reading the digital image signal from the image memory, the fields or frames are thinned out and read out. It turns out. Optimal conditions can then be obtained by observing the monitor television and arbitrarily setting parameters according to various transmission conditions for image signals.

The setting control section 2 sets parameters including the delay time of the transmission line and the amount of band compression corresponding to the transmission capacity using a switch or the like, and the delay memory section 3
The write control section of the 1000 is configured to write in synchronization with the synchronization signal of the input image signal.
By controlling so that only valid pixels in the digital image signal are written into the image memory, the capacity of the image memory is reduced.
Further, the read control section performs thinning-out reading of fields or frames according to the setting parameters in the setting control section 2. In that case, for example, 1
To provide a function to set parameters such that a field is treated as one unit when lowering the resolution of a digital image signal for a frame. According to this parameter, the readout control section of the delay memory section (3) performs readout control of the digital image signal written in the image memory. Therefore, on the receiving and reproducing side, only one of the odd and even fields is reproduced, resulting in an image without blurred outlines or flickering.

The coder section 1 also has a selection section and a compression processing section for a plurality of input image signals when the transmitting side is equipped with a plurality of television cameras, and converts the input image signals selected by the selection section into digital signals. It performs band compression processing such as reducing the number of bits per pixel and thinning out fields or frames according to the setting parameters of the setting control unit 2, adds a control signal indicating the band compression processing, and performs delay processing. Add to memory section 3. In that case, for example, the coder section (1) may
The resolution of one frame's worth of digital image signals is reduced, multiplexed, and transmitted in accordance with parameters for reducing resolution in units of fields.

Further, the detection section of the decoder section 4 detects a control signal from the digital image signal read out from the delay memory section 3, and based on the control signal, returns the original digital image signal to the original digital image signal in the interpolation processing section.・It is converted into an image signal by an analog converter and then added to a monitor TV.

[0018]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 is a block diagram of an embodiment of the present invention, in which 10 is an input terminal, 11 is a signal processing circuit, and 12 is a block diagram of an embodiment of the present invention.
1 is a synchronization separation circuit, 13 is an AD converter (A/D), 14 is an image memory, 15 is a write control section, 16 is a read control section, 1
7 is a delay time setting section, 18 is a resolution setting section, 19 is a frame dropping setting section, 20 is a tone dropping setting section, 21 is a DA converter (D/A), 22 is a signal processing circuit, and 23 is an output terminal. A coder section 1 is configured by a signal processing circuit 11, a synchronization separation circuit 12, and an AD converter 13, and a delay time setting section 1 is configured.
7, a resolution setting section 18, a frame drop setting section 19, and a tone drop setting section 20 constitute a setting control section 2, and an image memory 14, a write control section 15, and a read control section 16 constitute a delay memory section 3. Furthermore, the DA converter 21 and the signal processing circuit 22 constitute the decoder section 4.

An image signal from a television camera (not shown) is applied to a signal processing circuit 11 from an input terminal 10, subjected to filter processing, etc., and applied to a synchronous separation circuit 12 and an AD converter 13. A synchronization signal is separated in the synchronization separation circuit 12, and this synchronization signal is supplied to each section. Also A
The digital image signal is converted into a digital image signal by the D converter 13 and added to the image memory 14, and the digital image signal is written into the image memory 14 under the control of the write control section 15. At this time, the write control unit 15 performs control to write only valid pixels in the digital image signal into the image memory 14 in synchronization with the synchronization signal.

One screen in the NTSC system consists of 858×525 pixels, as shown in FIG. 3, and the effective pixel areas in the odd and even fields are 704×240, respectively. Therefore, the image memory 14 stores 704 pixels per frame when the resolution is set to maximum.
Since an effective digital image signal consisting of ×480 pixels will be written, which is an image signal of 30 images per second,
If the maximum delay time is 4 seconds, it will have a capacity that can store 120 effective digital image signals.

Furthermore, when the delay time is set by the delay time setting section 17, the readout control section 16 adds a readout address signal corresponding to the set delay time to the image memory 14. The digital image signal written by the address signal is read out after a set delay time and is applied to the DA converter 21.

When the normal mode is set by the resolution setting section 18, the readout control section 16 outputs a readout address signal for reading out all the valid pixels of each frame, and when the subsample mode is set, for example, By thinning out every other pixel, a read address signal for reading out 352×240 pixels is output.

When frame dropping is set by the frame dropping setting unit 19, the read control unit 16 repeatedly outputs the same read address signal in accordance with the set number of frames. For example, if the number of images is 15 per second due to frame dropping, the digital image signal of the same frame will be repeatedly read out twice every other frame.

Further, when the gradation level is set by the gradation drop setting section 20, the readout control section 16 outputs a readout address signal for reading out the number of bits corresponding to the set gradation level. For example, when one pixel is digitized with 8 bits, 256
In terms of gradations, in the case of 125 gradations, it is sufficient to read out a configuration of 7 bits per pixel.

The digital image signal read from the image memory 14 is converted into an analog image signal by the DA converter 21, and the signal processing circuit 22 restores the band-compressed image signal to the original image signal. This will be added to the monitor television, which is not shown.

As mentioned above, since it is possible to perform band compression processing in accordance with the transmission state and to provide a delay time corresponding to the transmission delay, various parameters can be set to simulate various transmission path conditions. The received and reproduced image quality can be evaluated by observing the image on a monitor television corresponding to the receiving side.

FIG. 4 shows an example of the front panel of the above-mentioned image delay device, where "POWER" is a power switch that controls power ON/OFF, and "BIT WIDE" is a switch that controls the number of bits, 3, 4, 5, 6, and 7. The gradation setting switch "RESOLUTION" sets the gradation by selecting the normal mode (NORM) (1 frame 704 x 480
pixel accumulation mode) and sub-sample mode (SU
B) Resolution setting switch to switch between (mode that accumulates 352 x 240 pixels per frame), "RATE" is 2
, 5, 10Mbps, "DELAY" is a transmission line delay on/off setting switch that sets transmission delay ON and OFF.
"TIME" is a transmission delay time setting switch consisting of a switch that sets 0, 1, 2, 3, 4 in units of 1 second, and a switch that sets settings in units of 0.1 seconds.

"VIDEO IN" is a channel setting switch that selects one or both of channels CH1 and CH2 for the input image signal, and "SYNC" is an external synchronization switch (EXI) that uses a clock signal synchronized with the input image signal.
T) and internal synchronization (IN) using an internal clock signal.
This is a clock synchronization setting switch. Also 25
is the display section for the transmission rate "RATE", and 26 is the delay time "
27 is the number of transmission frames “FRA”.
ME" display section. The space on the right is for inserting a printed board with the desired circuit.

The delay time can be set using the transmission delay time setting switch, for example, in units of 0.1 seconds for 1 second or less, and in units of 1 second for delay times greater than 1 second. When the delay time is set in the delay time setting section 17, the set delay time is displayed on the display section 26 using two digits in units of 0.1 seconds and 1 second. When the transmission line delay on/off setting switch is turned on, a read address signal is applied from the read control unit 16 to the image memory 14 according to the set delay time, a digital image signal of the set delay time is applied to the DA converter 21, The signal is converted into an analog image signal, and is applied to a monitor television (not shown) from an output terminal 23 via a signal processing circuit 22.

[0030] Also, the settings made by the resolution setting switch are set in the resolution setting section 18, and the normal mode (NORM
), the number of frames per second (30) is displayed on the display unit 27, the read address signal from the read control unit 16 is for the entire effective pixel area, and the sub-sample mode (SUB) is set. If set, display section 2
7 displays the number of frames per second, 15, and by thinning out the bits in the effective pixel area of the odd field, 3
A read address signal for reading out 52×240 pixels is output. That is, this corresponds to the case where the amount of transmitted information is reduced to 1/4 of that in the normal mode.

When a transmission rate of 2, 5, or 10 Mbps is set using the transmission rate setting switch in accordance with the transmission capacity of the transmission line to be simulated, the set transmission rate is displayed on the display section 25.

FIG. 5 is a block diagram of a second embodiment of the present invention, in which 31 is a selector, 32 is a filter, 33 is a clamp circuit, 34 is an AD converter (A/D), 35 is a bit control section, 36 is a limiter, 37 is a multiplexer (MU
X), 38 is a buffer memory (BF), 39 is a synchronization separation circuit (SYN), 40 is a selector, 41 is a phase synchronization circuit (PLL), 42 is a synchronization signal generation circuit (VH), 43 is a transmission control section, 44 45 is a delay memory section, 45 is an image memory,
46 is a write control section, 47 is a read control section, 51 and 52 are channel correspondence sections, 53 is a buffer memory (BF), 54 is a detection section, 55 is an interpolation processing section, 56 is a reception control section, 57 is a memory, 58 is a selector, 59 is a DA converter (D/A)
, 60 is a synchronization signal insertion section, and 61 is a filter.

[0033] CH1 and CH2 are channel image signals,
a is a setting signal from the clock synchronization setting switch "SYNC", b is a bit number setting signal from the gradation setting switch "BIT WIDE", and c is a resolution setting switch "RE".
d is the delay time setting signal by the transmission delay time setting switch "DELAY TIME", e is the transmission rate setting switch "RA"
TE” transmission rate setting signal. Further, UW1 and UW2 input to the multiplexer 37 are unique words, and CNT is a control signal.

In this embodiment, each of the above-mentioned setting signals a to
The setting control section 2 of FIG. 1 is configured including the input section of e and the transmission control section 43, the delay memory 44 corresponds to the delay memory section 3 of FIG. 1, and the other configurations correspond to the coder section 1 of FIG. This corresponds to the configuration of the decoder section 4 and the decoder section 4.

The input image signals of the two channels CH1 and CH2 are selected either one or alternately by the selector 31, and the selected input image signal is band-limited to, for example, 3.2 MHz by the filter 32 and synchronized with the clamp circuit 33. It is added to the separation circuit 39. This synchronous separation circuit 39
Then, the synchronization signal is separated from the input image signal and the selector 40
internal synchronization (IN
), the selector 40 selects the output of the phase synchronization circuit 41, a clock signal in a free running state is applied from the phase synchronization circuit 41 to the synchronization signal generation circuit 42, and when external synchronization (EXIT) is designated. Since the selector 40 selects the synchronization signal separated by the synchronization separation circuit 39 and applies it to the phase synchronization circuit 41, a clock signal synchronized with the input image signal is applied to the synchronization signal generation circuit 42.

Furthermore, the clamp circuit 33 performs DC reproduction by clamping the input image signal to the pedestal level and applies it to the AD converter 34. sampled by the sampling clock signal, e.g.
It is converted into a bit digital signal. This sampling clock signal is generated by a circuit (not shown) in synchronization with a clock signal from the phase synchronization circuit 41.

The digital image signal converted by the AD converter 34 is applied to the bit control section 35, and the transmission control section 43 controls the number of bits corresponding to one pixel according to the bit number setting signal b and the resolution setting signal c. . Also, the limiter 36 restricts the effective data so that FF,00 is not included, and the multiplexer 37 replaces the first effective pixel of the effective first line of the frame with the FF (all "1") unique word UW1. Replace the next effective pixel with the control signal CNT, and replace the first effective pixel of the other effective first line with the unique word UW of 00 (all “0”).
1, the transmission frame is configured,
The signal is applied to the delay memory section 44 via the buffer memory 38.

FIG. 6 is an explanatory diagram of the transmission frame format, and the effective pixel area shown in FIG. The 131st pixel of the 22nd line in one frame shown in FIG. A unique word UW2 (00) is used, and the pixel position next to the unique word UW1 is used as a control signal CNT.

As mentioned above, the unique word UW1 is
It has an 8-bit configuration of all "1" (FF), which indicates the beginning of the effective pixel area, and also indicates the unique word UW.
2 has an 8-bit configuration of all "0" (00), and indicates the beginning of each line from the second line onwards in the effective pixel area. Further, the control signal CNT has 8 bits b0 to b as shown in FIG.
The gradation (
(number of bits/pixel) 3, 4, 5, 6, 7. For example, if bits b7, b6, and b5 are set to "101", this indicates gradation 6 (number of bits/pixel).

The fourth bit, b4, indicates resolution; "1" indicates normal mode, and "0" indicates subsample mode. Also, 3 from the 5th bit to the 7th bit
Bits b3, b2, b1 indicate the number of transmission frames, and these three bits indicate the number of transmission frames.
For example, if these 3 bits b3, b2, b1 are set to "110", the number of transmission frames per second is designated as 15. Further, 1 bit b0 of the least significant bit LSB indicates channel selection; "0" indicates channel CH1, and "1" indicates channel CH2.

In the above-mentioned bit control section 35, when the set gradation is the maximum 256, the effective pixel data has an 8-bit configuration, and as shown in FIG. 8, the effective pixel data D1-1 ~D1-8, D2-1~D2-8,...
will be added to the limiter 36 as is.

In the limiter 36, each valid pixel data includes FF and 00 so that the above-mentioned unique word UW1 of FF and unique word UW2 of 00 can be detected separately from other valid pixel data. It is intended to limit the number of For example, in the case of FF (all “1”) effective pixel data, the least significant bit is “0” and 00
In the case of valid pixel data (all "0"), the least significant bit is "1".

Further, when the set gradation is 64, the effective pixel data is composed of 6 bits, and the bit control section 35 changes the lower 2 bits to a fixed value as shown in FIG. , for example, the least significant bits D1-1, D2-
2,... are "0", 2nd bit from the bottom D1-2,D
2-2, . . . are set to “1”.

Further, when the set gradation is 16, the effective pixel data is composed of 4 bits, and the bit control section 35 controls the lower 4 bits D1-1 to D1 as shown in FIG.
-4, D2-1 to D2-4, ... are deleted, and the upper 4 bits of the adjacent pixels D1-5 to D1-8, D2-5 to D2
-8, to create 8-bit data.

When the set gradation is 4, the effective pixel data has a 2-bit configuration, and the bit control unit 35 reduces the lower 4 bits to a fixed value of 2 bits, as shown in FIG. , fixed value “1” in the upper 2 bits, “
0'' is added to form a 4-bit structure, and the data is combined to form an 8-bit structure.

As described above, when the resolution, the transmission rate, the number of bits indicating gradation, and the number of transmission frames are set, the relationship between them and the actual transmission rate is shown in FIG. In the figure, the resolution is 704 x 480 in normal mode.
In pixel and sub-sample modes, the case of 352 x 240 pixels is shown, and RAT is the set transmission rate (10, 5, 2M
bps), BIT is the number of bits of the set gradation (7 to 3), F
RM is the number of transmission frames (30, 15, 6, 5), RRA
T indicates the actual transmission rate (Mbps).

For example, if the resolution is set to normal mode, the transmission rate is set to 10 Mbps, the number of gradation bits is set to 4, and the number of transmission frames is 6, the actual transmission rate is 8.2 Mbps. Further, if the resolution is set to subsample mode, the transmission rate is set to 5 Mbps, the number of gradation bits is set to 4, and the number of transmission frames is 10, the actual transmission rate is 3.4 Mbps.

As described above, the image signal subjected to band compression processing on the transmitting side is added to the delay memory section 44 corresponding to the transmission path, and is sequentially transferred to the image memory 45 by the write control section 46.
By writing the image signal to the address corresponding to the set delay time and reading it under the control of the readout control unit 47, the image signal with a maximum delay of about 4 seconds is sent to the channel corresponding units 51 and 5.
Added to 2.

Channel correspondence sections 51 and 52 have the same configuration and are added to detection section 54 and interpolation processing section 55 via buffer memory 53. The detection unit 54 detects the unique words UW1, UW2 and the control signal CNT and adds them to the reception control unit 56. The reception control unit 56 identifies the beginning of the effective pixel area by the detection signal of the unique word UW1, identifies the beginning of the effective line by the detection signal of the unique word UW2, and recognizes the band compression parameter by the detection signal of the control signal CNT. Then, the interpolation processing section 55, interpolation memory 57, selector 58, and synchronization signal insertion section 60 are controlled.

For example, when the number of transmission frames is 10, the first frame from the interpolation processing unit 55 is added to the interpolation memory 57 and the selector 58, the selector 58 selectively outputs the first frame, and the second frame and During the time corresponding to the third frame, the contents of the first frame repeatedly read from the interpolation memory 57 are selectively output. As a result, the number of frames becomes 30, which is converted into an analog image signal by the DA converter 59, and a synchronization signal formed based on the unique words UW1 and UW2 is inserted in the synchronization signal inserting section 60, and then passed through the filter 61. channel CH1 or C
The signal is added to a monitor television (not shown) as an H2 image signal.

Further, when the number of gradation bits is set to 4, for example, the reception control section 56 controls the interpolation processing section 55 according to the number of gradation bits of the control signal CNT, and by the reverse processing of the bit control shown in FIG. After separating into bits, a fixed value of the lower 4 bits is added to each 4 bits to form an 8-bit configuration, which is then applied to the DA converter 59 via the selector 58. Similarly, when the resolution is in the sub-sample mode, the interpolation processing unit 55 performs interpolation between pixels so that the pixel data becomes valid pixel data in the normal mode. In addition, the reception control section 56 of the channel correspondence sections 51 and 52 performs reception processing in accordance with the channel selection bit.

In this embodiment, the delay memory section 44
Since it performs bandwidth compression processing before inputting to
Even if the set delay time is increased, there is an advantage that the capacity of the image memory 45 does not need to be increased too much, and the transmission state of a band-compressed digital image signal can be simulated.

[0053] The present invention is not limited to the above-described embodiments; for example, it is also possible to automatically set the number of transmission frames and the number of gradation bits so that the transmission rate is within the set transmission rate. In addition, it is also possible to configure the resolution to be switched in more steps. It is also applicable to color image signals.

Next, a method of lowering the resolution using a field as a unit will be explained based on FIGS. 13 and 14. FIG. 13 is a diagram showing the image configuration of one screen, (A)
1 shows a frame structure, (B) shows one image obtained by interlaced scanning, and (C) shows a conventional example in which the resolution is reduced to 1/2. A frame 100 is composed of an odd field 101 consisting of scans of each line from 1 to 263, and an even field 102 consisting of scans of each line from 264 to 525, and one image 110 is constituted by interlaced scanning of each of these lines. On the other hand, when there is a limit to the transmission capacity, it is necessary to reduce the resolution of one image 110. In that case, a method is usually adopted in which the resolution is reduced in units of frames. That is, as shown in FIG. 13C, the resolution of each field is halved, and the halved fields are alternately scanned. If the image 120 obtained in this manner is updated once per second on the receiving and reproducing side, the odd fields will be alternately reproduced 30 times and the even fields will be alternately reproduced 30 times. Therefore, if there is a fast-moving object in the image, the distance traveled in 1/60 seconds will be alternately played back for 1 second on the playback side. As a result, the straight line shown in FIG. 13(B) is
This results in a line with steps with large variations as shown in C). This results in an image that is very difficult to see for the human eye.
Even if such an image is taken into an image processing device and processed, only meaningless data will be obtained.

FIG. 14 is a diagram showing an image obtained by reducing the resolution using a field as a unit. frame 10
Do not transmit even field 102 among 0,
Only the odd field 101 is transmitted to the transmission path. On the reproduction side, odd fields are reproduced 60 times for one image, resulting in an image 130 as shown in FIG. 14. This image 130 is shown in FIG.
Compared to 3(C), the image has smaller variations and is free from blurred outlines and flickering. Furthermore, even when this image is imported into an image processing device and processed, it can be processed into meaningful data. Although the case where the resolution in the vertical direction is lowered has been described here, a similar method can be adopted when the resolution in the horizontal direction is lowered.

The method of lowering the resolution using each field as a unit is performed according to the parameters set with the resolution setting switch (FIG. 4). For example, the readout control unit 16 (FIG. 2) controls the readout of the digital image signal written in the image memory 14 (FIG. 2) according to the parameters, and reduces the resolution in units of fields. Further, the multiplexer 37 (FIG. 5) multiplexes and transmits the digital image signals processed according to the parameters. Furthermore, it is also possible to reduce the resolution in the circuit configuration of the multiplexer 37, regardless of the parameters of the resolution setting switch 16.

Furthermore, in the above description, this method of reducing the resolution using a field as a unit was applied to an image delay device, but it can also be configured to be applied to an image transmission device. An example of the configuration in that case is shown in FIG.

FIG. 15 is a diagram showing a case where a method of reducing resolution using a field as a unit is applied to an image transmission apparatus. The difference from the image delay device of FIG. 5 is that the delay memory section 44 is removed and line interfaces 71 and 72 are provided on the transmitting side and the receiving side, respectively. This image transmission device can be effectively used when it is necessary to transmit still images with reduced resolution, such as in videophones, for example.

[0059]

As explained above, the present invention allows the setting control section 2 to set the delay time and the amount of band compression, and to write only valid pixel data to the image memory of the delay memory section 3. Therefore, even for a transmission line such as a satellite line that has a large delay time and has a limited transmission capacity, the present invention can be realized without increasing the capacity of the image memory too much. Therefore, there is an advantage that various transmission paths can be simulated economically.

[0060] Furthermore, during transmission, the resolution is reduced, for example, using a field as a unit. Therefore, the image is free from blurred outlines and flickering, and even when the image is imported into an image processing device and processed, it can be treated as meaningful data.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a block diagram of one embodiment of the invention.

FIG. 3 is an explanatory diagram of effective pixels.

FIG. 4 is an explanatory diagram of the front panel.

FIG. 5 is a block diagram of another embodiment of the invention.

FIG. 6 is an explanatory diagram of a transmission frame format.

FIG. 7 is an explanatory diagram of control signals.

FIG. 8 is an explanatory diagram of control bits.

FIG. 9 is an explanatory diagram of control bits.

FIG. 10 is an explanatory diagram of control bits.

FIG. 11 is an explanatory diagram of control bits.

FIG. 12 is a diagram showing an actual transmission rate with respect to a set transmission rate, etc.

FIG. 13 is a diagram showing the image structure of one screen, in which (A) shows the frame structure, (B) shows one image by interlaced scanning, and (C) shows the conventional example when the resolution is reduced to 1/2. Each is shown below.

FIG. 14 is a diagram showing an image obtained by lowering the resolution using a field as a unit.

FIG. 15 is a diagram illustrating a case where a method of reducing resolution in units of fields is applied to an image transmission device.

[Explanation of symbols]

1 Coder section 2 Setting control section 3 Delay memory section 4 Decoder section

Claims (6)

[Claims] 1. An image delay device for simulating an image signal transmission path, comprising: a coder section (1) that converts an input image signal into a digital signal; and a setting control section that sets a delay time and a band compression amount. (2), a delay memory section (3) into which the digital image signal from the coder section (1) is written and which reads out the digital image signal after a delay time set in the setting control section (2); An image delay device comprising: a decoder section (4) that converts a digital image signal read from a memory section (3) into an analog image signal and outputs the analog image signal. 2. The setting control unit (2) has a configuration for setting parameters including a delay time and a band compression amount,
The delay memory section (3) includes an image memory, a write control section, and a read control section, and the write control section reads effective pixels in the digital image signal in synchronization with a synchronization signal of the input image signal. 2. The digital image signal according to claim 1, wherein the digital image signal is written in the image memory, and the readout control section controls the readout of the digital image signal from the image memory according to setting parameters in the setting control section (2). Image delay device. 3. The readout control section of the delay memory section (3) reads the digital image written into the image memory according to a parameter set by the setting control section (2) for reducing the resolution in units of fields. 3. The image delay device according to claim 2, wherein the image delay device performs signal readout control. 4. The coder section (1) includes a selection section for a plurality of input image signals, and an analog-to-digital conversion section for converting the selected input image signal into a digital image signal.
and a compression processing section that performs band compression processing on the digital image signal converted by the analog-to-digital conversion section according to the setting parameters of the setting control section (2) and adds a control signal indicating the band compression. The image delay device according to claim 1, characterized in that: 5. The coder section (1) lowers the resolution of one frame of digital image signals and multiplexes them in accordance with parameters set by the setting control section (2) for lowering the resolution in units of fields. 5. The image delay device according to claim 4, wherein the image delay device transmits the image. 6. The decoder section (4) includes a detection section that detects a control symbol included in the digital image signal read from the delay memory section (3), and a detection section that detects a control symbol included in the digital image signal read out from the delay memory section (3), and a 2. The image delay device according to claim 1, further comprising an interpolation processing section for restoring the digital image signal, and a digital-to-analog conversion section.