JPH0422923A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH0422923A
JPH0422923A JP12798990A JP12798990A JPH0422923A JP H0422923 A JPH0422923 A JP H0422923A JP 12798990 A JP12798990 A JP 12798990A JP 12798990 A JP12798990 A JP 12798990A JP H0422923 A JPH0422923 A JP H0422923A
Authority
JP
Japan
Prior art keywords
liquid crystal
voltage
electrode
crystal display
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12798990A
Other languages
Japanese (ja)
Inventor
Yutaka Marushita
丸下 裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP12798990A priority Critical patent/JPH0422923A/en
Publication of JPH0422923A publication Critical patent/JPH0422923A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a liquid crystal device from being degraded in display quality due to the uneveness in the positive and negative sizes of voltages impressed on the liquid crystal by detecting voltage impressed on a pair of electrodes and correcting the voltage. CONSTITUTION:Voltage impressed between a display electrode 9 and a counter electrode 12 is detected through a filter 22 such as a low pass filter and inputted to a voltage generating circuit 23. A DC bias DELTAV' is outputted from the means 23 to a data line driving circuit 5 or the electrode 12 in accordance with the voltage drop DELTAV of a source signal. Since the value DELTAV' corresponding to each voltage impressed on a liquid crystal panel can be set up, a DC component is not impressed on the liquid crystal, flicker or the deterioration of the liquid crystal is not generated and stable display corresponding to an operation environment and driving conditions can be obtained.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明はTPTなどの能動素子を用いた液晶表示装置に
関し、特に液晶パネルの駆動電圧の制御に関する。
DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a liquid crystal display device using active elements such as TPT, and particularly to control of driving voltage of a liquid crystal panel.

(ロ)従来の技術 従来よりアモルファスシリコン(a−5i)などの材料
で構成された薄膜トランジスタ(TPT)を駆動素子と
して用いたアクティブマトリックス型液晶表示装置にお
いては、構造上TPTの寄生容量による電圧降下が発生
し、直流(DC)成分の液晶への印加にともなうフリッ
カ等の問題が指摘されている(TV学会技術報告10.
N。
(b) Conventional technology Conventionally, in active matrix liquid crystal display devices that use thin film transistors (TPT) made of materials such as amorphous silicon (A-5I) as driving elements, voltage drop due to the parasitic capacitance of the TPT is due to the structure. It has been pointed out that problems such as flicker occur due to the application of direct current (DC) components to liquid crystals (TV Society Technical Report 10.
N.

45、pp25〜29.ED“ 87−5)。45, pp25-29. ED “87-5).

以下、上記問題発生の概要について簡単に説明する。The following is a brief explanation of the occurrence of the above problem.

第11図はアクティブマトリクス型液晶表示装置のアク
ティブマトリクス基板の1画素単位の模式図である。
FIG. 11 is a schematic diagram of each pixel of an active matrix substrate of an active matrix liquid crystal display device.

同図において、ゲート線駆動回路(1)からのゲート信
号はゲート!(2)を伝わって、TPT(3)のゲート
(4)に印加されてこのTPTを導通させる。
In the figure, the gate signal from the gate line drive circuit (1) is gate! (2) and is applied to the gate (4) of TPT (3), making this TPT conductive.

一方、データ線駆動回路(5)からのデータ信号はデー
タ線(6)を伝わって、導通されたTFTのドレイン(
7)からソース(8)へ経た後、表示電極(9)に印加
される。
On the other hand, the data signal from the data line drive circuit (5) is transmitted through the data line (6), and the drain (
7) to the source (8) and then applied to the display electrode (9).

このようなアクティブマトリクス型液晶表示装置の1画
素単位の等価回路図を第12図に示す。
FIG. 12 shows an equivalent circuit diagram of each pixel of such an active matrix liquid crystal display device.

第12図においてゲート線(2)とデータ線(6)がそ
れぞれTPT (3)のゲート(4)とドレイン(7)
に接続されている。
In Figure 12, the gate line (2) and data line (6) are the gate (4) and drain (7) of TPT (3), respectively.
It is connected to the.

TPT (3)はゲート(4)とソース(8)間で寄生
容量[Cgsコ (]O)を持ち、液晶(11)は表示
電極(9)と対向電極(12)間で液晶の容量[C1c
]  (13)を持っている。
The TPT (3) has a parasitic capacitance [Cgsco (]O) between the gate (4) and the source (8), and the liquid crystal (11) has a liquid crystal capacitance [Cgsco (]O) between the display electrode (9) and the counter electrode (12). C1c
] I have (13).

液晶の容量(13)が小さい場合、補助容量[Csc]
  (14)を設けることが多い。
If the liquid crystal capacitance (13) is small, the auxiliary capacitance [Csc]
(14) is often provided.

これ等容量[CIc]、[esc]は共に各画素を表示
させるための容量である。
Both of these capacitances [CIc] and [esc] are capacitances for displaying each pixel.

前記の寄生容量[Cgs]は、一般的にTPTのゲート
(4)とソース(8)が絶縁層を介して一部重なり合う
ような構成をとるために存在するものである。
The above-mentioned parasitic capacitance [Cgs] exists because the gate (4) and source (8) of the TPT are generally configured to partially overlap with each other with an insulating layer interposed therebetween.

この寄生容量[Cgs]は容量結合(カップリング)に
より、次式で示される電圧降下ΔVを引き起こす要因に
なっている。
This parasitic capacitance [Cgs] causes a voltage drop ΔV expressed by the following equation due to capacitive coupling.

ΔV=VgXCgs/(C1c+Csc+Cgs)■こ
こでVgはゲート信号の電圧振幅値である。
ΔV=VgXCgs/(C1c+Csc+Cgs) (2) Here, Vg is the voltage amplitude value of the gate signal.

第13図は前記説明による電圧降下を示す信号波形図で
あり、同図(a)はフィールド毎に反転するデータ信号
の波形図、同図(b)は同図(a)のデータ信号に対す
るソース信号の波形図、同図(c)はそのデータ信号に
対するDCバイアス図である。
FIG. 13 is a signal waveform diagram showing the voltage drop according to the above explanation, FIG. 13(a) is a waveform diagram of a data signal that is inverted for each field, and FIG. The signal waveform diagram (c) is a DC bias diagram for the data signal.

同図(d)はフィールド毎に反転するデータ信号の波形
図であって、その信号レベルは同図(a)より大きい。
FIG. 3(d) is a waveform diagram of a data signal that is inverted for each field, and its signal level is higher than that in FIG. 4(a).

同図(e)は同図(d)のデータ信号に対するソース信
号の波形図、同図(f)はそのデータ信号に対するDC
バイアス図を示している。
The figure (e) is a waveform diagram of the source signal for the data signal in the figure (d), and the figure (f) is a DC waveform diagram for the data signal.
A bias diagram is shown.

これ等の図に於て、TPTを導通させる1個のゲート信
号(15)に対してデータ信号(16)は通常1フイー
ルドごとに反転しており、1組の奇数番目と偶数番目の
フィールドのデータ信号の時間を1フレームと称する。
In these figures, the data signal (16) is normally inverted for each field for one gate signal (15) that makes the TPT conductive, and a pair of odd and even fields are inverted. The time of the data signal is called one frame.

データ信号(16)はTPTを通過するとソース信号(
17)となるので、データ信号(16)の中央値[Vc
enter]  (18)に対向電極信号[Vc]  
(19)を設定するとソースに接続された表示電極によ
って液晶に好ましくないDC成分が加わる慣れがあった
When the data signal (16) passes through the TPT, the source signal (
17), the median value of the data signal (16) [Vc
enter] (18) is the counter electrode signal [Vc]
When (19) is set, an undesirable DC component is added to the liquid crystal due to the display electrode connected to the source.

第】3図の(b)、 (e)が示すように奇数、偶数フ
ィールド間で液晶印加電圧は非対称となり、液晶の光学
応答波形に駆動周波数の振動成分が含まれることになる
As shown in FIGS. 3(b) and 3(e), the voltage applied to the liquid crystal becomes asymmetric between the odd and even fields, and the optical response waveform of the liquid crystal includes an oscillating component of the driving frequency.

このような奇、偶数フィールド間の液晶印加電圧の非対
称性を補正する方法としては共通電極の電圧Vcをデー
タ信号の中心電圧Vcenterに対して全表示電極で
一律に電圧降下ΔVだけシフトさせる(DCバイアス電
圧)ことが一般的である。
A method for correcting such asymmetry in the voltage applied to the liquid crystal between odd and even fields is to uniformly shift the voltage Vc of the common electrode by a voltage drop ΔV across all display electrodes with respect to the center voltage Vcenter of the data signal (DC (bias voltage) is common.

ところが、■式の液晶容量[C]c]は第13図に示す
ようにデータ信号の大きさにより変化するため、第12
図のように補助容量[Csc]を付加して液晶の容量[
Cl c]の変化をカバーすることが必要となるがこの
補助容量[esc]付加は表示電極(9)と重なる電極
が必要であるために開口率低下等の問題とも関係し、必
要面積分大きくすることが困難である。
However, since the liquid crystal capacitance [C]c] in equation (2) changes depending on the magnitude of the data signal as shown in FIG.
As shown in the figure, by adding an auxiliary capacitor [Csc], the liquid crystal capacitance [
It is necessary to cover changes in the auxiliary capacitance [esc], but the addition of this auxiliary capacitance [esc] requires an electrode that overlaps with the display electrode (9), which is related to problems such as a reduction in the aperture ratio, and the required area increases. difficult to do.

このため、DCバイアス△■′を液晶の印加電圧に応じ
て変化させる手法が必要となる。
Therefore, a method is required for changing the DC bias Δ■' in accordance with the voltage applied to the liquid crystal.

一方、カップリングによる電圧降下Δ■は経時変化する
場合もあり得る。
On the other hand, the voltage drop Δ■ due to coupling may change over time.

この場合もDCバイアスΔV゛を変えて対応しなければ
ならない。
In this case as well, the DC bias ΔV' must be changed.

この他にも、ソース信号の放電に伴う実効電圧の低下が
アクティブマトリクス型液晶表示装置では発生する[”
パーソナル情報機器への応用性”電子技?F15月臨時
増刊号、第32巻、第7号、P36 (1990年)に
詳しい]。
In addition to this, active matrix liquid crystal display devices also experience a drop in the effective voltage due to discharge of the source signal.
Applicability to personal information equipment, "Electronic Technology? F15 Special Issue, Volume 32, No. 7, P36 (1990) for details.

そこで、従来から対向電極を各行ごとにセグメント化し
て分離形成し、該各対向電極に、そのラインに対応する
表示電極電位のその保持期間内の変動による輝度変化を
キャンセルし得る交流餘輻変調パルスを対向電極信号に
重畳して供給する対向電極駆動手段を備えたアクティブ
マトリクス型液晶表示装置の駆動方法が提案されている
(特開平2−7780号公報)。
Therefore, conventionally, counter electrodes are segmented and formed separately for each row, and each counter electrode is supplied with an alternating current radiation modulation pulse that can cancel the brightness change due to fluctuations in the display electrode potential corresponding to that line within its holding period. A method for driving an active matrix liquid crystal display device has been proposed (Japanese Unexamined Patent Publication No. 2-7780), which includes a counter electrode driving means for supplying a counter electrode signal superimposed on a counter electrode signal.

第14図は従来の放電に伴う電圧低下を補償する駆動方
法の説明図であり、同図(a)はソース信号とゲート信
号の波形図、同図(b)はソース信号と対向電極信号の
波形図、同図(C)は液晶印加電圧の波形図を示してい
る。
FIG. 14 is an explanatory diagram of a conventional driving method for compensating for a voltage drop accompanying discharge. FIG. 14(a) is a waveform diagram of a source signal and a gate signal, and FIG. Waveform diagram: (C) of the same figure shows a waveform diagram of the voltage applied to the liquid crystal.

第14図(a)のソース信号(17)は寄生容量による
電圧降下ΔVと放電による電圧低下によりデータ信号の
中央値(18)に対して非対称な波形となっている。
The source signal (17) in FIG. 14(a) has an asymmetrical waveform with respect to the median value (18) of the data signal due to the voltage drop ΔV due to parasitic capacitance and the voltage drop due to discharge.

これに対して、同図(b)に示す如く、対向電極電位(
19)にはデータ信号の中央値を中心としてフィールド
毎に反転する漸増パルスを重畳する。
On the other hand, as shown in the same figure (b), the counter electrode potential (
19) is superimposed with a gradually increasing pulse that is inverted for each field with the center value of the data signal as the center.

この結果、液晶印加電圧(20)は同図(C)のように
データ信号の中央値(18)に対して放電部分において
平行になり放電による電圧低下は補1賞される。
As a result, the voltage applied to the liquid crystal (20) becomes parallel to the median value (18) of the data signal at the discharge portion, as shown in FIG.

しかるに、この駆動方法ではフィールド毎に対向電極に
印加するパルスを反転する手段の付加が必要であり、し
かもそのタイミング設定は困難を極める。さらに、この
駆動方法の場合には、異なる大きさのソース信号が印加
される多数の表示電極に対向する1つのセグメント化さ
れた対向電極のDCバイアスが一定になり、多数の表示
電極から液晶にDC成分が印加される慣れがあった。
However, with this driving method, it is necessary to add a means for inverting the pulse applied to the counter electrode for each field, and setting the timing thereof is extremely difficult. Furthermore, in the case of this driving method, the DC bias of one segmented counter electrode facing a large number of display electrodes to which source signals of different magnitudes are applied is constant, and the There was a habit of applying a DC component.

以上のようにDCバイアス電圧ΔV゛は一律で決めるこ
とはできず、液晶パネル内のキャパシタの変動に応じて
フレキシブルに対応する必要があった。
As described above, the DC bias voltage ΔV' cannot be uniformly determined, and it is necessary to respond flexibly to variations in the capacitor within the liquid crystal panel.

(ハ)発明が解決しようとする課題 しかるに現状はある一定の印加電圧条件で駆動されてい
る液晶表示装置の任意の一点(人間がよく見る中央部と
することが多い)の透過光から検出した光量から最適な
りCバイアス電圧ΔV°を決定し、液晶表示装置に固定
したDCバイアス電圧△V°を最終駆動条件として装置
に組み込んでいたため、液晶表示装置の駆動条件の変動
や環境変化等により直流成分が液晶に印加されることに
なりフリッカの発生、液晶の劣化等の問題があった。
(c) Problems to be solved by the invention However, at present, it is possible to detect light transmitted from an arbitrary point (often at the center, which is often seen by humans) of a liquid crystal display device that is driven under a certain applied voltage condition. The optimum C bias voltage ΔV° was determined from the amount of light, and the DC bias voltage ΔV° fixed to the liquid crystal display device was incorporated into the device as the final driving condition. Since a direct current component is applied to the liquid crystal, there are problems such as occurrence of flicker and deterioration of the liquid crystal.

本発明は一対の電極間の電圧を検出して電圧補正を行う
ことにより液晶印加電圧の正負方向の大きさの不均一性
に基づく液晶表示装置の表示品位の劣化問題の解決を図
ることを目的とする。
An object of the present invention is to detect the voltage between a pair of electrodes and perform voltage correction to solve the problem of deterioration in display quality of a liquid crystal display device due to non-uniformity in the magnitude of the voltage applied to the liquid crystal in the positive and negative directions. shall be.

(ニ)課題を解決するための手段 上記課題を解決するためには、ある一定条件下での電圧
降下ΔVの検出とDCバイアスΔV′の設定を行うので
はなく、常時ΔVを検出しその検出結果をΔ■“にフィ
ードバックさせて△V°を可変に設定すれば良い。
(d) Means for solving the problem In order to solve the above problem, instead of detecting the voltage drop ΔV under certain conditions and setting the DC bias ΔV', it is necessary to constantly detect ΔV and detect it. The result may be fed back to Δ■" and ΔV° may be set variably.

従って、本発明のアクティブマトリクス型液晶表示装置
は、液晶印加電圧を検出する検出手段と、検出手段によ
って検出した液晶印加電圧に応じて変化する出力電圧を
発生する電圧発生手段と、電圧発生手段の出力電圧によ
り液晶パネルの対向電極又はデータ信号のDCバイアス
電圧を補正する電圧補正手段とを備える液晶表示装置と
し、また、データ信号、対向を種信号、補助容量信号の
内、いずれかの信号にDCバイアスを重畳するものであ
る。
Therefore, the active matrix type liquid crystal display device of the present invention includes a detection means for detecting the voltage applied to the liquid crystal, a voltage generation means for generating an output voltage that changes according to the voltage applied to the liquid crystal detected by the detection means, and a voltage generation means for generating an output voltage that changes according to the voltage applied to the liquid crystal detected by the detection means. The liquid crystal display device is provided with voltage correction means for correcting the DC bias voltage of the counter electrode of the liquid crystal panel or the data signal according to the output voltage, and the data signal and the counter electrode are set to either a seed signal or a storage capacitance signal. This superimposes a DC bias.

(ホ)作用 上記の手段を有した液晶表示装置においては従来のある
一定の条件下でのDCバイアスΔV゛により駆動するの
ではなく、液晶パネル内の各印加電圧に応じたΔV“を
設置できるため、液晶に直流成分が印加されることなく
フリッカや液晶の劣化の問題が発生せず、動作環境及び
駆動条件に即した安定した表示が提供できることになる
(e) Effect In the liquid crystal display device having the above means, instead of driving with the conventional DC bias ΔV′ under certain conditions, it is possible to set ΔV′ according to each applied voltage in the liquid crystal panel. Therefore, since no direct current component is applied to the liquid crystal, problems such as flicker and deterioration of the liquid crystal do not occur, and stable display can be provided in accordance with the operating environment and driving conditions.

(へ)実施例 以下本発明の一実施例を図面に基づいて説明する。(f) Example An embodiment of the present invention will be described below based on the drawings.

第1図は本発明の第1実施例の液晶表示装置の等価回路
図である。
FIG. 1 is an equivalent circuit diagram of a liquid crystal display device according to a first embodiment of the present invention.

第1図において表示電極(9)と対向電極(12)との
間の電圧をローパスフィルター(LPF)などのフィル
ター(22)に通してから検出して電圧発生手段(23
)に入力し、電圧発生手段(23)からソース信号の電
圧降下ΔVに応じてデータ線駆動回路(5)または対向
電極(12)にDCバイアスΔ■゛が出力される。
In FIG. 1, the voltage between the display electrode (9) and the counter electrode (12) is passed through a filter (22) such as a low-pass filter (LPF) and then detected.
), and the voltage generating means (23) outputs a DC bias Δ■'' to the data line driving circuit (5) or the counter electrode (12) according to the voltage drop ΔV of the source signal.

第2図は本発明の第2実施例の液晶表示装置の等価回路
図である。
FIG. 2 is an equivalent circuit diagram of a liquid crystal display device according to a second embodiment of the present invention.

第2図は対向電極(12)と補助容量電極(21)にそ
れぞれ異なったDCバイアス△V゛を印加している。
In FIG. 2, different DC biases ΔV' are applied to the counter electrode (12) and the auxiliary capacitance electrode (21).

より具体的なある時刻における電極の電圧を第3図に示
す。
More specifically, the voltage of the electrode at a certain time is shown in FIG.

第3図においてフィールド毎に反転している表示電極(
9)の電圧が+5v、表示電極と液晶を挟んで対向して
いる対向電極(12)の電圧が一4V、1ドツト毎に分
離している表示電極と絶縁膜を挟んでゲート線に平行で
且つゲート線と重ならない帯状パターンの補助容量電極
(例えば特公平1−55460号公報に詳しい。)の電
圧が−3vのとき、表示電極(9)と対向電極(12)
間の容量CIは誘電率ε1、有効面積S1、電極間距[
dlとして CI=clS1/di            C)で
あられされ、表示電極(9)と対向電極(12)ffJ
Jの電気量Q1は Q 1= CIV 1               
■であられされる。
In Figure 3, the display electrodes (
9) voltage is +5V, the voltage of the counter electrode (12) facing the display electrode with the liquid crystal in between is 14V, and the voltage of the counter electrode (12), which is separated every dot, is parallel to the gate line with an insulating film in between. In addition, when the voltage of the auxiliary capacitor electrode in a band-like pattern that does not overlap with the gate line (for example, see Japanese Patent Publication No. 1-55460 for details) is -3V, the display electrode (9) and the counter electrode (12)
The capacitance CI between the electrodes is determined by the dielectric constant ε1, the effective area S1, and the distance between the electrodes [
CI=clS1/di C) as dl, and the display electrode (9) and the counter electrode (12)ffJ
The quantity of electricity Q1 of J is Q1=CIV1
■It will be hailed.

同様にして表示電極(9)と補助容量電極(21)間の
容量C2、電気量Q2が求められるが、第3図のように
補助容量電極の電圧の絶対値が対向電極の電圧の絶対値
より小さく、V2<Vlでも容量Cを調整することによ
りQ2>Qlとすることができ、ソース電圧の放電を補
償することが可能になる。
In the same way, the capacitance C2 and the quantity of electricity Q2 between the display electrode (9) and the auxiliary capacitor electrode (21) are obtained, but as shown in Figure 3, the absolute value of the voltage of the auxiliary capacitor electrode is the absolute value of the voltage of the counter electrode. Even if V2<Vl, it is possible to make Q2>Ql by adjusting the capacitance C, making it possible to compensate for the discharge of the source voltage.

また、正の誘電異方性を示す混合液晶を用いたアクティ
ブマトリクス型液晶表示装置においてデータ信号とソー
ス信号間で見られる0式の電圧降下ΔVはデータ信号(
16)に対して第4図で示されるような反比例の関係と
なることが見いだされた。
In addition, in an active matrix liquid crystal display device using a mixed liquid crystal exhibiting positive dielectric anisotropy, the voltage drop ΔV of the equation 0 observed between the data signal and the source signal is the data signal (
16), it was found that there is an inversely proportional relationship as shown in FIG.

第4図でデータ信号の絶対値が1〜3■になるとき、電
圧降下Δ■は1,3〜0,5Vまで変化する。
In FIG. 4, when the absolute value of the data signal ranges from 1 to 3V, the voltage drop Δ■ changes from 1.3V to 0.5V.

上記の電圧降下△Vとデータ信号との関係をRAMに書
き込み、ラインメモリやフィールドメモリ中のデータ信
号と参照してDCバイアスΔV゛を間歇的に補正する方
法も可能である。
It is also possible to write the relationship between the voltage drop ΔV and the data signal in the RAM and refer to the data signal in the line memory or field memory to intermittently correct the DC bias ΔV.

上記の方法は短時間の液晶表示装置の使用に適し、始動
時に各電極に加えられるDCバイアスΔV° を決定し
、電源切断時まで始動時のデータ信号とDCバイアスと
の相関関係を固定して、より低消費電力の液晶表示装置
を構成できる。
The above method is suitable for short-term use of liquid crystal display devices, and determines the DC bias ΔV° applied to each electrode during startup, and fixes the correlation between the data signal and DC bias during startup until power-off. , it is possible to configure a liquid crystal display device with lower power consumption.

次に、各電極にどのようにDCバイアス八へ゛を重畳す
るかを説明する。
Next, how to superimpose the DC bias on each electrode will be explained.

第5図に、対向電極(12)が1枚の共通電極で構成さ
れた液晶表示装置の各電極の立体図を示す。
FIG. 5 shows a three-dimensional diagram of each electrode of a liquid crystal display device in which the counter electrode (12) is composed of one common electrode.

第5図で補助容量電極(21)は1ドア)毎に分離して
いる表示電極と絶縁膜を挟んでゲート線に平行で且つ表
示電極と重なっている。
In FIG. 5, the auxiliary capacitance electrode (21) is parallel to the gate line and overlaps the display electrode, which is separated for each door, with an insulating film in between.

対向電極が共通電極となっている第5図の構成の各電極
に加えるDCバイアスΔV′を第6図に示し、同図(a
)は液晶表示装置を上下に走るN本のデータ線における
データ信号バイアス△V゛1の分布図、同図(b)は液
晶表示装置を左右に走るM本の補助容量電極における補
助容量電極バイアスΔV’  2の分布図である。
The DC bias ΔV' applied to each electrode in the configuration shown in FIG. 5, in which the opposing electrode is a common electrode, is shown in FIG.
) is a distribution diagram of data signal bias △V゛1 in N data lines running vertically in the liquid crystal display device, and (b) of the same figure shows the auxiliary capacitor electrode bias in M auxiliary capacitor electrodes running left and right in the liquid crystal display device. It is a distribution diagram of ΔV'2.

第6図でデータ線は列を、補助容量電極は行を形成して
いるのでデータ信号バイアスΔV’  1と補助容量電
極バイアスΔV’  2で組み合わせにより各表示電極
毎に異なるDCバイアスΔV°を加えることができる。
In Figure 6, the data lines form columns and the auxiliary capacitor electrodes form rows, so a different DC bias ΔV° is applied to each display electrode by combining the data signal bias ΔV' 1 and the auxiliary capacitor electrode bias ΔV' 2. be able to.

第7図に対向電極が補助容量電極と平行に分割された液
晶表示装置の各電極の立体図を示す。
FIG. 7 shows a three-dimensional view of each electrode of a liquid crystal display device in which a counter electrode is divided parallel to an auxiliary capacitance electrode.

第7図の構成では補助容量電極(21)への異なる信号
の印加は必要なく対向電極(12)と表示電極(9〕に
接続されたデータ線に異なるDCバイアスΔV°を加え
ることになる。
In the configuration of FIG. 7, it is not necessary to apply different signals to the auxiliary capacitance electrode (21), and different DC biases ΔV° are applied to the data lines connected to the counter electrode (12) and the display electrode (9).

第8図に対向電極(12)が補助容量電極(21)と垂
直に分割された液晶表示装置の各電極の立体図を示す。
FIG. 8 shows a three-dimensional view of each electrode of a liquid crystal display device in which a counter electrode (12) is divided perpendicularly to an auxiliary capacitance electrode (21).

対向電極が共通電極となっている第8図の構成の各電極
に加えるDCバイアスΔV°を第9図に示し、同図(a
、 )は液晶表示装置を上下に走るN本の対向電極にお
ける対向電極バイアスΔV’  3の分布図、同図(b
)は液晶表示装置を左右に走るM本の補助容量電極にお
ける補助容量電極バイアスΔV’  2の分布図である
FIG. 9 shows the DC bias ΔV° applied to each electrode in the configuration shown in FIG. 8, in which the opposing electrode is a common electrode.
, ) is a distribution diagram of the counter electrode bias ΔV'3 in the N counter electrodes running vertically in the liquid crystal display device, and the same figure (b
) is a distribution diagram of auxiliary capacitor electrode bias ΔV′ 2 in M auxiliary capacitor electrodes running left and right in the liquid crystal display device.

第9図で対向電極は列、補助容量電極は行を形成してい
るので対向電極バイアスΔV’  3と補助容量電極バ
イアス△V’  2で組み合わせにより各表示電極毎に
異なるDCバイアスΔ■′を加えることができる。
In Fig. 9, the counter electrodes form columns and the auxiliary capacitor electrodes form rows, so a different DC bias Δ■' can be applied to each display electrode by combining the counter electrode bias ΔV' 3 and the auxiliary capacitor electrode bias ΔV' 2. can be added.

第10図にデジタルIC制御器を用いた液晶表示装置に
本発明の構成を適用した赤色信号の回路図を示す。
FIG. 10 shows a circuit diagram of a red signal in which the configuration of the present invention is applied to a liquid crystal display device using a digital IC controller.

第1O図においてマトリックス回路(24)で分離され
た赤色信号はLPF (25)を通って、A/D変換器
(26)で変換され、ラインメモリ(27)、フィール
ドメモリ(28)、信号調整(29)を経て、D/A変
換器(30)で分割されたアナログ信号となる。
In Fig. 1O, the red signal separated by the matrix circuit (24) passes through the LPF (25), is converted by the A/D converter (26), and is sent to the line memory (27), field memory (28), and signal adjustment. (29), it becomes an analog signal divided by a D/A converter (30).

さらに赤色信号はLPF(31)を通って、輝度調整器
(32) 、スイッチング(33)、レベルシフト(3
4)を通って1列おきに液晶パネル(35)の上下に配
置されたデータ線駆動回路(5)からTPTに印加され
る。
Furthermore, the red signal passes through the LPF (31), the brightness regulator (32), the switching (33), and the level shifter (33).
4) and is applied to the TPT from data line drive circuits (5) arranged above and below the liquid crystal panel (35) every other column.

一方、A/D変換!(26)からの同期信号はデジタル
IC制御器(36)によりゲート線駆動回路(1)とデ
ータ線駆動回路(5)に加えられる。
On the other hand, A/D conversion! The synchronization signal from (26) is applied to the gate line drive circuit (1) and data line drive circuit (5) by the digital IC controller (36).

液晶パネル(35)のITPTまたは数TFTからフィ
ルター(22)に取り出された電圧降下ΔVは電圧発生
手段(23)によってDCバイアスΔV° として赤色
信号に印加される。
The voltage drop ΔV extracted from the ITPT or several TFTs of the liquid crystal panel (35) to the filter (22) is applied to the red signal as a DC bias ΔV° by the voltage generating means (23).

(ト)発明の効果 本発明によれば環境などの外部要因に左右されず常に直
流成分が印加されない条件で液晶を交流駆動できるため
、従来、液晶へ直流成分が印加去れることにより発生し
ていたフリッカ等のない均一で高品位な表示が得られる
(g) Effects of the Invention According to the present invention, the liquid crystal can be driven with AC under conditions where no DC component is always applied, regardless of external factors such as the environment, so that problems that conventionally occur due to the DC component being applied to and leaving the liquid crystal can be avoided. A uniform, high-quality display with no flicker or the like can be obtained.

また、多少のパネルのTPT及びギャップのバラツキは
DCバイアスの調整で補償できるため、液晶パネルの歩
留り向上にも寄与することになる。
Further, since some variations in TPT and gap of the panel can be compensated for by adjusting the DC bias, it also contributes to improving the yield of liquid crystal panels.

以上のように本発明によれば環境など外部要因に左右さ
れず、常に最適条件で液晶パネル全域を駆動することが
できるため、液晶への直流成分印加による問題が発生せ
ず、安定で高画質な液晶表示装置が実現できる。
As described above, according to the present invention, the entire area of the liquid crystal panel can always be driven under optimal conditions without being affected by external factors such as the environment, so there are no problems caused by applying a DC component to the liquid crystal, and the image quality is stable and high. A liquid crystal display device can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1実施例のDCバイアスの自動調整
システムのブロック図、第2図は本発明の第2実施例の
DCバイアス自動調整システムのブロック図、第3図は
本発明の各電極への電気量供給の説明図、第4図は電圧
降下とデータ信号との相関図、第5図は共通電極を持つ
液晶表示装置の主電極の立体図、第6図は共通電極を持
つ本発明の液晶表示装置の波形図、第7図はゲート線に
平行に分割された対向電極を持つ液晶表示装置の主電極
の立体図、第8図はデータ線に平行に分割された対向電
極を持つ液晶表示装置の主電極の立体図、第9図は対向
電極と補助容量電極が直交する本発明の液晶表示装置の
波形図、第10図はデジタルIC制御器を持つ本発明の
液晶表示装置の回路図、第11図はアクティブマトリク
ス型液晶表示装置のアクティブマトリクス基板の1画素
単位の模式図、第12図はアクティブマトリクス型液晶
表示装置の1画素単位の等価回路図、第13図は各信号
とDCバイアスの波形図、第14図は従来の信号の補償
波形図である。 (1)・・・ゲート線駆動回路、(2)・・・ゲート線
、(3)・・・TPT、(4)・・・ゲート、(5)・
・・データ線駆動回路、(6)・・・データ線、(7)
・・・ドレイン、 (8)・・・ソース、(9)・・・
表示電極、(10)・・・寄生容量、(11)・・・液
晶、(12)・・・対向電極、(13)・・・液晶の容
量、(14)・・・補助容量、(15)・・・ゲート信
号、(16)・・・データ信号、(17)・・・ソース
信号、(18)・・・データ信号の中央値、(19)・
・・対向電極信号、(20)・・・液晶印加電圧、(2
1)・・・補助容量電極、(22)・・フィルター、(
23)・・・電圧発生手段、(24)・・・マトリック
ス回路、(25)・・・LPF、(26)・・・A/D
変換器、(27)・・・ラインメモリ、(28)・・・
フィールドメモリ、(29)・・・信号調整、(30)
・・・D/A変換器、(31)・・・LPF、(32)
・・・輝度調整器、(33)・・・スイッチング、(3
4)・・・レベルシフト、(35)・・・液晶パネル、
(36)・・・デジタルICl1l制御器。 Cgs・
・・寄生容量、Clc・・・液晶の容量、Csc・・・
補助容量、Vg・・・ゲート信号の電圧振幅値、Vce
nter・・・データ信号の中央値、△V・・・電圧降
下、Vc・・・対向電極信号、ΔV°・・・DCバイア
ス電圧、ΔV’  1・・・データ信号バイアス、ΔV
’  2・・・補助容量電極バイアス、ΔV’ 3・・
・対向電極バイアス、ε・・・誘電率、S・・・有効面
積、d・・・電極間距離、■・・・電圧、Q・・・電気
量。 出願人      三洋電機株式会社 代理人  弁理士 西野卓嗣(外2名)第1図 第2図 第3図 Ql=CIVl 2V2 第4図 データ信号 第5図 第6図 (a) (b) 1列2列 N列 1行2行 M行 第7図 第8図 第9図 (a) (b) 1列2列 N列 1行 2行 M行 第1 図 第1 2図 第1 3図
FIG. 1 is a block diagram of a DC bias automatic adjustment system according to a first embodiment of the present invention, FIG. 2 is a block diagram of a DC bias automatic adjustment system according to a second embodiment of the present invention, and FIG. 3 is a block diagram of a DC bias automatic adjustment system according to a second embodiment of the present invention. An explanatory diagram of the amount of electricity supplied to each electrode, Figure 4 is a correlation diagram between voltage drop and data signal, Figure 5 is a three-dimensional diagram of the main electrode of a liquid crystal display device with a common electrode, and Figure 6 is a diagram showing the relationship between the voltage drop and the data signal. 7 is a three-dimensional diagram of the main electrode of a liquid crystal display device having counter electrodes divided parallel to the gate line, and FIG. 8 is a waveform diagram of the main electrode of the liquid crystal display device having counter electrodes divided parallel to the data line. 9 is a waveform diagram of the liquid crystal display device of the present invention in which the counter electrode and the auxiliary capacitance electrode are orthogonal to each other, and FIG. 10 is a diagram of the liquid crystal display device of the present invention having a digital IC controller. A circuit diagram of the display device, FIG. 11 is a schematic diagram of each pixel of an active matrix substrate of an active matrix type liquid crystal display device, FIG. 12 is an equivalent circuit diagram of each pixel of an active matrix type liquid crystal display device, and FIG. 13 14 is a waveform diagram of each signal and DC bias, and FIG. 14 is a compensation waveform diagram of a conventional signal. (1)...Gate line drive circuit, (2)...Gate line, (3)...TPT, (4)...Gate, (5)...
...Data line drive circuit, (6)...Data line, (7)
...Drain, (8)...Source, (9)...
Display electrode, (10) Parasitic capacitance, (11) Liquid crystal, (12) Counter electrode, (13) Liquid crystal capacitance, (14) Auxiliary capacitance, (15 )...Gate signal, (16)...Data signal, (17)...Source signal, (18)...Median value of data signal, (19)...
...Counter electrode signal, (20) ...Liquid crystal applied voltage, (2
1)...Auxiliary capacitance electrode, (22)...Filter, (
23) Voltage generating means, (24) Matrix circuit, (25) LPF, (26) A/D
Converter, (27)...Line memory, (28)...
Field memory, (29)...Signal adjustment, (30)
...D/A converter, (31) ...LPF, (32)
...Brightness adjuster, (33)...Switching, (3
4)... Level shift, (35)... Liquid crystal panel,
(36)...Digital ICl1l controller. Cgs・
...parasitic capacitance, Clc...liquid crystal capacitance, Csc...
Auxiliary capacitance, Vg...Voltage amplitude value of gate signal, Vce
nter...median value of data signal, △V...voltage drop, Vc...counter electrode signal, ΔV°...DC bias voltage, ΔV' 1...data signal bias, ΔV
'2...Auxiliary capacitor electrode bias, ΔV'3...
- Opposing electrode bias, ε... dielectric constant, S... effective area, d... distance between electrodes, ■... voltage, Q... quantity of electricity. Applicant Sanyo Electric Co., Ltd. Agent Patent attorney Takuji Nishino (2 others) Figure 1 Figure 2 Figure 3 Ql = CIVl 2V2 Figure 4 Data signal Figure 5 Figure 6 (a) (b) 1 column 2 Column N Column 1 Row 2 Row M Row 7 Figure 8 Figure 9 (a) (b) 1 Column 2 Column N Column 1 Row 2 Row M Row 1 Figure 1 2 Figure 1 3

Claims (3)

【特許請求の範囲】[Claims] (1)データ信号が供給されるデータ線とゲート信号が
供給されるゲート線との交点に能動素子が形成されたア
クティブマトリクス基板と対向電極が形成された対向基
板との間に液晶を挟持したアクティブマトリクス型液晶
表示装置において、液晶印加電圧を検出する検出手段と
、検出手段によって検出した液晶印加電圧に応じて変化
する出力電圧を発生する電圧発生手段と、電圧発生手段
の出力電圧により液晶表示装置の対向電極に印加される
直流バイアス電圧を補正する電圧補正手段とを備えた液
晶表示装置。
(1) A liquid crystal is sandwiched between an active matrix substrate in which active elements are formed at the intersection of a data line to which a data signal is supplied and a gate line to which a gate signal is supplied and a counter substrate in which a counter electrode is formed. In an active matrix type liquid crystal display device, there is a detection means for detecting a liquid crystal applied voltage, a voltage generation means for generating an output voltage that changes according to the liquid crystal applied voltage detected by the detection means, and a liquid crystal display using the output voltage of the voltage generation means. A liquid crystal display device comprising voltage correction means for correcting a DC bias voltage applied to a counter electrode of the device.
(2)データ信号が供給されるデータ線とゲート信号が
供給されるゲート線との交点に能動素子が形成されたア
クティブマトリクス基板と対向電極が形成された対向基
板との間に液晶を挟持したアクティブマトリクス型液晶
表示装置において、液晶印加電圧を検出する検出手段と
、検出手段によって検出した液晶印加電圧に応じて変化
する出力電圧を発生する電圧発生手段と、電圧発生手段
の出力電圧により液晶表示装置のデータ信号の直流バイ
アス電圧を補正する電圧補正手段とを備えた液晶表示装
置。
(2) A liquid crystal is sandwiched between an active matrix substrate in which active elements are formed at the intersection of a data line to which a data signal is supplied and a gate line to which a gate signal is supplied and a counter substrate in which a counter electrode is formed. In an active matrix type liquid crystal display device, there is a detection means for detecting a liquid crystal applied voltage, a voltage generation means for generating an output voltage that changes according to the liquid crystal applied voltage detected by the detection means, and a liquid crystal display using the output voltage of the voltage generation means. A liquid crystal display device comprising voltage correction means for correcting a DC bias voltage of a data signal of the device.
(3)データ信号が供給されるデータ線とゲート信号が
供給されるゲート線との交点に能動素子が形成されたア
クティブマトリクス基板と対向電極信号が供給される対
向電極が形成された対向基板との間に液晶を挟持したア
クティブマトリクス型液晶表示装置において、液晶印加
電圧を検出してデータ信号、対向電極信号、補助容量信
号の内、少なくとも2つ以上の信号に直流バイアス電圧
を重畳することを特徴とする液晶表示装置。
(3) An active matrix substrate in which active elements are formed at the intersection of a data line to which a data signal is supplied and a gate line to which a gate signal is supplied, and a counter substrate in which a counter electrode is formed to which a counter electrode signal is supplied. In an active matrix liquid crystal display device in which a liquid crystal is sandwiched between the electrodes, a voltage applied to the liquid crystal is detected and a DC bias voltage is superimposed on at least two of the data signal, the counter electrode signal, and the auxiliary capacitance signal. Characteristic liquid crystal display device.
JP12798990A 1990-05-17 1990-05-17 Liquid crystal display device Pending JPH0422923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12798990A JPH0422923A (en) 1990-05-17 1990-05-17 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12798990A JPH0422923A (en) 1990-05-17 1990-05-17 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH0422923A true JPH0422923A (en) 1992-01-27

Family

ID=14973700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12798990A Pending JPH0422923A (en) 1990-05-17 1990-05-17 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH0422923A (en)

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EP0634737A1 (en) * 1993-07-16 1995-01-18 Philips Electronics Uk Limited Feedback arrangement for improving the performance of an active matrix structure
US6466191B1 (en) 1998-12-24 2002-10-15 Samsung Electronics Co., Ltd. Liquid crystal display thin film transistor driving circuit
WO2003067316A1 (en) * 2002-02-06 2003-08-14 Mitsubishi Denki Kabushiki Kaisha Image display unit
WO2004013835A1 (en) * 2002-07-29 2004-02-12 Koninklijke Philips Electronics N.V. Method and circuit for driving a liquid crystal display
JP2004264677A (en) * 2003-03-03 2004-09-24 Hitachi Displays Ltd Liquid crystal display device
JP2007114577A (en) * 2005-10-21 2007-05-10 Toshiba Matsushita Display Technology Co Ltd Liquid crystal display
JP2007140475A (en) * 2005-11-22 2007-06-07 Prime View Internatl Co Ltd Circuit for setting up common voltage and method therefor
JP2007178987A (en) * 2005-12-28 2007-07-12 Lg Philips Lcd Co Ltd Apparatus and method for driving liquid crystal display element
US7362304B2 (en) 1999-07-23 2008-04-22 Nec Corporation Liquid crystal display device and method for driving the same

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Publication number Priority date Publication date Assignee Title
EP0570001A2 (en) * 1992-05-14 1993-11-18 Kabushiki Kaisha Toshiba Liquid crystal display device
EP0570001A3 (en) * 1992-05-14 1994-11-30 Toshiba Kk Liquid crystal display device.
US5434599A (en) * 1992-05-14 1995-07-18 Kabushiki Kaisha Toshiba Liquid crystal display device
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US5646643A (en) * 1992-05-14 1997-07-08 Kabushiki Kaisha Toshiba Liquid crystal display device
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