JPH04228177A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate the sure reading out of stored data at a high speed irrelevant of a CB/Cs ratio even when the trend toward larger capacities, ultrasmaller sizes and lower voltages progresses. CONSTITUTION:A transistor(TR) Q2 connected to a transistor(TR) Q1 acts as a cell capacitor and whether an inversion layer is formed in a channel region or not is determined according to the stored data. The inversion layer is formed in the channel region of the TR Q2 stored with the '1' as the stored data and the TR Q2 stored with this inversion layer is conducted when a prescribed voltage is supplied from a pulse generating circuit 11 at the time of reading out of the stored data. Current can be supplied to the bit line BL from the pulse generating circuit 11 via a transistor Q3 and the selected TR Q1 as this layer is conducted and, therefore, the data reading out is executed at the high speed and high margin without depending on the CB/Cs ratio.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] This invention is applicable to stacked and
DRAM with capacitor structure (Dynamic Rand
The present invention relates to memory cells (Access Memory), and particularly relates to semiconductor memory devices to which thin film technology is applied.

0002

2. Description of the Related Art FIG. 8 is an equivalent circuit showing a DRAM memory cell having a conventional stacked capacitor structure. This memory cell is composed of a selection transistor Q1 and a data storage capacitor Cs. The gate of the selection transistor Q1 is connected to the word line WL,
One end of the selection transistor Q1 is connected to the bit line BL, and the other end is connected to the capacitor Cs.

FIGS. 9 and 10 show the structure of the memory cell described above, and the same parts as in FIG. 8 are given the same reference numerals.

In FIGS. 9 and 10, the capacitor Cs
A pair of polysilicon layers 31 and 32 constituting the transistor are provided above the diffusion layer n+ of the selection transistor Q1. That is, the polysilicon layer 31 is connected to the selection transistor Q1.
A polysilicon layer 32, which serves as a plate electrode and is in valid contact with the diffusion layer n+ of the polysilicon layer 31 and is provided above this polysilicon layer 31 with an insulating film interposed therebetween, is biased to a constant potential. These pair of polysilicon layers 31 and 32 are formed to extend above the word line WL serving as the gate of the selection transistor Q1 in order to increase the storage capacitance.

Incidentally, in DRAMs, as memory cells become smaller, the number of memory cells connected to a bit line increases, and the capacitance of the bit line tends to increase. Furthermore, as processing technology becomes finer, the area occupied by a unit cell is being reduced. Therefore, in order to ensure the storage capacity Cs, techniques such as making the insulating film of the capacitor even thinner are required. However, there is a limit to how thin the insulating film can be made for reasons such as ensuring reliability of the capacitor. For this reason, it is becoming difficult to ensure the ratio of the bit line capacitance CB to the cell storage capacity Cs, the so-called CB/Cs ratio.

[0006] Furthermore, in the future generation of ultra-fine process LSIs, it is thought that the power supply voltage will drop below 5V. When the power supply voltage of DRAM is lowered, the amount of charge accumulated in the capacitor decreases, so the amount of charge transferred to the bit line when reading data also decreases, making it possible to reliably amplify data using a sense amplifier. It is expected that it will be difficult to do so.

[0007] Here, the relationship between the bit line capacitance CB and the cell storage capacitance Cs will be further explained.

FIG. 11 shows a conventional DRA including peripheral circuits.
12 illustrates the operation of FIG. 11. The potential VBL of the bit line is the initial setting level of the bit line before reading.

First, the read operation will be explained.

(1) Before starting the active cycle,
Since the EQL signal is at a high level, the bit lines BL0 to BL3 are precharged to the VBL level.

(2) One word line WL0 is selected by a row decoder (not shown), and the word line WL0 is set to Vcc (=5V) by a bootstrap circuit (not shown).
) or higher to 7.5 V.

(3) Dummy word lines DWL0 and /DWL0 (/ means an inverted signal) are selected corresponding to the selected word line, and the dummy word line DWL0 is set to V
BL level to Vcc level, /DWL0 is VB
It is set from L level to Vss level.

(4) Data “1” stored in the selected cell connected to bit line BL0 and bit line BL2
Data "0" stored in the selected cell connected to the bit line BL0 and BL2 appear on the bit lines BL0 and BL2, respectively. Assuming that the storage level of "1" in the memory cell is V1 and the storage level of "0" is V0, the level v1 of the bit line after reading data "1" is v1 = (V1 + CB /Cs ・VBL) / (1+
CB /Cs )...(1), and the level v0 of the bit line after reading data "0" is v0 = (V0 + CB /Cs ・VBL) / (1+
CB /Cs )...(2). V1 = 5 V, V
0 = 0 V, VBL = 2.5 V, CB /Cs =
15, v1 = 2.656V v0 = 2.344V. The reference level of bit line BL1 and bit line BL3 is VBL=2.5 V
Therefore, the potential difference Δ amplified by the sense amplifier is
v has the same value as Δv1 = 0.156V when reading data “1” and Δv0 = 0.156V when reading data “0”.

(5) The sense amplifier is activated,
Bit lines BL0 and BL3 are amplified to Vcc level, and bit lines BL1 and BL2 are amplified to Vss level.

(6) The levels of a pair of bit lines BL0 and BL1, or BL2 and BL3, selected by a selection signal supplied to a column selection line CSL from a column decoder (not shown) are transferred to output lines DQ and /DQ, respectively. be done.

Next, the write operation will be explained. In this write operation, (1) explained in the above read operation
The operations from (3) to (3) are the same, and after this, (4
), the write level supplied to the output lines DQ, /DQ is transferred to the sense amplifier through the column switch transistor selected by the column selection line CSL. The level of the pair of bit lines is set to Vcc by the sense amplifier.
becomes the Vss level, and this level is written into the selected memory cell.

[0017] Here, by transforming the above equations (1) and (2), v1 = VBL + (V1 - VBL) / (1 + CB /
Cs )...(3) v0 = VBL + (V0 - VBL)
/(1+CB/Cs)...(4).

As is clear from equations (3) and (4), as capacitance increases and ultra-fine design progresses, bit line capacitance CB increases and capacitor capacitance Cs decreases, v1
, v0 both approach VBL.

Since the amplification reference voltage of the sense amplifier is VBL, the potential differences Δv1 and Δv1 amplified by the sense amplifier
Both v0 become smaller. Therefore, it is difficult to reliably amplify data using the sense amplifier.

[0020]

[Problems to be Solved by the Invention] This invention solves the above-mentioned conventional problems, and its purpose is to solve the problems of the prior art. /Cs ratio, high speed,
Furthermore, it is an object of the present invention to provide a semiconductor memory device that can reliably read stored data.

[0021]

[Means for solving the problem] That is, this invention
In order to solve the above problem, the gate is connected to the word line, one end of the current path is connected to the bit line, a first transistor selects a memory cell, and the data selected by the first transistor is connected to the stored data. a second transistor whose conduction or non-conduction is determined accordingly; pulse generating means for supplying a voltage at a predetermined level to the second transistor when reading stored data; and when the second transistor becomes conductive; and a third transistor that is turned on and supplies a current output from the pulse generating means to the bit line.

[0022] Furthermore, the second and third transistors are
The gate electrode of the third transistor is formed of a thin film, and the gate electrode of the third transistor is formed of the channel region of the second transistor.

Furthermore, the second and third transistors are made of polysilicon, and the impurity concentration in their channel regions is lower than the impurity concentration in other parts.

Further, the pulse generating means includes an oscillation circuit that generates a pulse signal, a booster circuit that boosts the pulse signal generated by the oscillation circuit to a predetermined potential, and a booster circuit that boosts the pulse signal generated by the oscillation circuit to a predetermined potential. A predetermined potential output from the booster circuit is supplied to the second transistor before the transistor is selected, and the potential is supplied to the second transistor before the first transistor is deselected. It has a supply circuit that stops the operation.

Furthermore, the present invention provides a first transistor having a gate connected to a word line and one end of a current path connected to a bit line.
a second transistor whose gate is connected to the other end of the current path of the first transistor and selected by the first transistor; the second transistor is conductive or nonconductive depending on stored data; is determined, and the pulse generating means is connected to one end of the current path of the second transistor, and the pulse generating means has a gate that supplies a voltage at a predetermined level to the second transistor when reading stored data. a third transistor connected to the other end of the current path of the second transistor, one end of the current path connected to the other end of the current path of the first transistor, and the other end connected to the pulse generating means; , this third transistor is rendered conductive when the second transistor is rendered conductive, and supplies the current output from the pulse generating means to the bit line.

[0026] Furthermore, the second and third transistors are
The gate electrode of the third transistor is formed of a thin film, and the gate electrode of the third transistor is formed of the channel region of the second transistor.

Furthermore, the second and third transistors are made of polysilicon, and the impurity concentration in their channel regions is lower than the impurity concentration in other parts.

Further, the pulse generation means includes an oscillation circuit that generates a pulse signal, a booster circuit that boosts the pulse signal generated by the oscillation circuit to a predetermined potential, and a booster circuit that boosts the pulse signal generated by the oscillation circuit to a predetermined potential. A predetermined potential output from the booster circuit is supplied to the second transistor before the transistor is selected, and the potential is supplied to the second transistor before the first transistor is deselected. and a supply circuit that stops.

Further, the present invention provides a MOS type first transistor, and the first transistor includes a diffusion layer forming source and drain regions provided at a predetermined interval in a semiconductor substrate, and a diffusion layer forming a source and drain region provided on the semiconductor substrate. It has a gate as a word line provided insulated from the semiconductor substrate, and is formed on one diffusion layer of the first transistor that selects a memory cell, and forms the gate electrode of the second transistor. a first semiconductor layer; a second semiconductor layer provided insulated on the first semiconductor layer; the second semiconductor layer has a channel having a low impurity concentration in a portion corresponding to the first semiconductor layer; a third semiconductor layer provided insulated on the second semiconductor layer; One end of the third semiconductor layer is connected to the first
The third semiconductor layer is connected to the semiconductor layer, and the other end is connected to the plate electrode, and the impurity concentration of a portion of the third semiconductor layer corresponding to the second semiconductor layer is lower than that of the other portion. .

Further, the first to third semiconductor layers are made of polysilicon.

Furthermore, the third semiconductor layer is made of amorphous silicon.

Further, the first to third semiconductor layers are made of single crystal silicon.

Furthermore, the present invention includes a first transistor whose gate is connected to a word line, one end of a current path is connected to a bit line, and which selects a memory cell; a second transistor whose conductivity is determined to be conductive or non-conductive depending on data; pulse generating means for supplying a voltage at a predetermined level to the second transistor when reading stored data; a third transistor that is turned on when the current is turned on and supplies a current output from the pulse generation means to the bit line; a selection signal generation means that generates a selection signal for selecting the word line; and supply means for supplying the pulse signal output from the pulse generation means to the second and third transistors in accordance with the output selection signal.

[0034] Furthermore, the supply means is constituted by an AND circuit.

[0035]

[Operation] That is, according to the present invention, the second transistor connected to the first transistor acts as a cell capacitor, and whether or not an inversion layer is formed in the channel region is determined depending on the stored data. be done. An inversion layer is formed in the channel region of the second transistor in which “1” is stored as storage data, and the second transistor in which this inversion layer is formed
The transistor is turned on when a predetermined voltage is supplied from the pulse generating means when reading stored data, and the third transistor is accordingly turned on. Therefore, current can be supplied from the pulse generating means to the bit line through this third transistor and the selected first transistor, so that current can be supplied to the bit line at high speed and with a high margin, without depending on the CB /Cs ratio. Data can now be read.

Moreover, since the second and third transistors are formed of thin films, and the gate electrode of the third transistor forms the channel region of the second transistor, it is different from the conventional method of one transistor and one capacitor. It can be configured with an area equivalent to that of a memory cell.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Note that the same parts as in FIG. 8 are given the same reference numerals.

FIG. 1 shows an equivalent circuit of the present invention, and shows one memory cell MC.

For example, an n-channel selection transistor Q1
The gate of this selection transistor Q1 is connected to the word line WL, and the source of this selection transistor Q1 is connected to the bit line BL. The drain of this selection transistor Q1 is connected, for example, to the gate of an n-channel transistor Q2. The drain of this transistor Q2 is connected to the plate electrode PL, and the source is, for example, an n-channel transistor Q3.
connected to the gate. This transistor Q3 drives the current of the bit line, and the drain of this transistor Q3 is connected to the plate electrode PL, and the source is connected to the drain of the Q1 and the gate of the transistor Q2. A pulse generating circuit 11 is connected to the plate electrode PL. This pulse generating circuit 11 outputs a plate pulse φp that boosts the voltage of the plate electrode PL when reading data.

The gate of the transistor Q2 constitutes a storage node of a memory cell, and data "1" is input to this storage node.
” is stored, an inversion layer is formed in the channel region of this transistor Q2. Further, if data “0” is stored in the storage node, no inversion layer is formed in the channel region.

The principle of operation of the above configuration will be explained with reference to FIG.

When reading the data stored in the transistor Q2, first, before selecting the word line WL,
A plate pulse φ having a voltage Vp is generated from the pulse generation circuit 11.
p is output. This voltage Vp is set to be higher than the power supply voltage Vcc. The transistor Q2 is in an on state when data "1" is stored, and its gate potential is, for example, V1. Since the gate of transistor Q2 is capacitively coupled to plate electrode PL, plate pulse φp
is output, the potential Va at the connection node a between the drain of transistor Q1 and the gate of transistor Q2 is V1.
Increased to +Vp. The potential Va of connection node a is V1
When the voltage is increased to +Vp, the potential Vb of the connection node b between the source of the transistor Q2 and the gate of the transistor Q3
becomes V1+Vp-Vth2. Here, Vth2
is the threshold voltage of transistor Q2. Since this potential Vb is supplied to the gate of the transistor Q3, the transistor Q3 is turned on, and the potential Va of the connection node a is supplied with the lower voltage of V1+Vp-Vth2-Vth3 or the plate pulse Vp. Here, Vth3 is the threshold voltage of transistor Q3,
In FIG. 2, the potential Va of the connection node a is the plate pulse Vp.
The case is shown below.

Furthermore, when data "0" is stored in transistor Q2, no inversion layer is formed in the channel region, so transistor Q2 maintains the connection between connection nodes a and b even when plate pulse φp is supplied. Potential V
Both a and Vb do not change. Note that the potential of the bit line BL is initially set to VBL.

Next, when the word line WL is activated and the selection transistor Q1 is selected, the connection node a and the bit line BL are connected. Data “1” in transistor Q2
is stored, the charge on the connection node a is transferred to the bit line BL, and the potential of the bit line BL becomes as shown in equation (1). Further, when data "0" is stored in the transistor Q2, the potential of the bit line BL becomes as shown in equation (2).

Further, when reading data "1", transistor Q3 is turned on as described above, so a current flows from pulse generating circuit 11 to bit line BL via transistors Q3 and Q1. Therefore, connection node a,
And the bit line BL is charged with a constant slope.

Next, after a predetermined time has elapsed after the word line WL is selected, a sense amplifier (not shown) operates and the voltage read to the bit line is amplified.

In this embodiment, the level of the bit line when "1" data is read is raised to above bit line potential VBL by the current supplied from transistor Q3. Therefore, it is possible to obtain data at a predetermined level without using a sense amplifier.

Thereafter, the plate pulse φp is cut off while the word line WL is selected. Therefore, the potential Vb of the connection node b of the transistor Q2 in which data "1" is stored becomes 0V, the transistor Q3 is turned off, and the current supply to the bit line BL is stopped. Therefore, the transistor Q3 operates during the period from when the word line WL is selected until the plate pulse φp is cut off.
That is, a current is supplied to the bit line BL for a period indicated by t in FIG. 2.

When data "0" is stored in the transistor Q2, the condition that the potential of the connection node a does not rise above the "0" storage level due to capacitive coupling due to the plate pulse φp is V1 > Vth2. . Further, when the word line is selected, the "0" storage level approaches the bit line potential VBL, but the transistor Q2 must be turned off. Therefore, the threshold value of transistor Q2 and the potential VBL of the bit line are Vth2 > VBL
must satisfy the following conditions.

Furthermore, in the data write operation, since the plate voltage Vp remains at 0V, the transistor Q3 is not turned on.

FIG. 3 shows that transistor Q2 and transistor Q3 shown in FIG.
2 shows an equivalent circuit configured using a TFT (Transistor: TFT).

That is, transistor Q2 and transistor Q3 have a stacked structure, and the source and
The drain region and the gate of transistor Q3 are shared.

FIG. 4 shows the cross-sectional structure of FIG. 3. The transistors Q2 and Q3 are the selection transistor Q1
is formed on the diffusion layer. That is, a source S and a drain D forming an n-channel transistor Q1 are provided in the p-type semiconductor substrate 12. An oxide film 16 is provided on this semiconductor substrate 12, and this oxide film 16
A gate G1 serving as a word line WL is provided above. On the drain D of this transistor Q1, there is a polysilicon thin film 1 that constitutes the gate G2 of the transistor Q2.
3 is formed. An insulating film 17 is provided on top of this polysilicon thin film 13, and a polysilicon thin film 14 is provided on this insulating film 17. This polysilicon thin film 14 is provided with an n- region with a low impurity concentration, which constitutes the channel region CH2 of the transistor Q2 and the gate G3 of the transistor Q3.
An n+ region with a high impurity concentration constituting the plate electrode PL is provided. Further, a cell capacitor is constituted by the polysilicon thin film 13, the polysilicon thin film 14, and the insulating film 17 interposed between them.

An insulating film 18 is provided above the polysilicon thin film 14, and a polysilicon thin film 15 is provided on this insulating film 18. This polysilicon thin film 15
An n- region with a low impurity concentration constitutes the channel region CH3 of the transistor Q3, and an n+ region with a high impurity concentration constitutes the source and drain. One end of this polysilicon thin film 15 is connected to the polysilicon thin film 13, and the other end is connected to the polysilicon thin film 14.
is connected to the plate electrode PL.

A bit line BL is provided on these structures via an insulating film 19, and this bit line BL is connected to the source S of the transistor Q1. In the figure, when reading data "1" stored in the gate G2 as a storage node, the current supplied to the plate electrode PL flows through the polysilicon thin film 1 as shown by arrow A in the figure.
5, 13, and flows to the bit line BL through the drain and source of the transistor Q1 in sequence.

FIG. 5 shows an example of the pulse generating circuit 11, and FIG. 6 shows signals of each part. This pulse generating circuit 11, when reading stored data,
The voltage of the plate electrode is increased before the selection transistor is selected, and the voltage of the plate electrode is decreased before the selection transistor is deselected.

That is, this pulse generating circuit 11 has R
The power supply voltage is adjusted according to pulse signals φ1 and φ2 having a 90° phase difference output from a timing pulse generation circuit 21 and an oscillation circuit 22, which generate a pulse signal φtp for a predetermined time in response to the falling edge of an AS (Row Address Strobe). A booster circuit 23 that boosts Vcc to a predetermined voltage Vp;
The output circuit 24 outputs the voltage Vp output from the plate pulse φp as a plate pulse φp.

The timing pulse generating circuit 21 is mainly composed of a delay circuit 21a, a NAND circuit 21b, etc., and generates a pulse signal φtp in response to the falling edge of RAS. That is, when RAS is at a high level, the output of the timing pulse generation circuit 21 is at a low level. Also, when RAS becomes low level,
The timing pulse generation circuit 21 outputs a high level timing pulse signal φtp. This pulse signal φt
p has a pulse width corresponding to the delay time set in the delay circuit 21a.

The oscillation circuit 22 generates pulse signals φ1 and φ2 having a phase difference of 90°, and these pulse signals φ1 and φ2 are supplied to a capacitor constituting a booster circuit 23.

The booster circuit 23 includes a plurality of capacitors 23a.
A plurality of transistors 23b diode-connected to the pulse signal φ1 and a limiter 23c.
, φ2, a capacitor 23a and a plurality of transistors 23b are used to boost the power supply voltage Vcc, and a limiter 23c generates a predetermined voltage Vp.

The output circuit 24 converts the voltage Vp output from the booster circuit 23 into a plate pulse φ according to the pulse signal φtp output from the timing pulse generation circuit 21.
Output as p. That is, when RAS is at a high level, the pulse signal φtp is at a low level, so the output circuit 24 does not select the output of the booster circuit 23, and the plate pulse φp is at a low level. Also, R.A.S.
When becomes low level, the pulse signal φtp becomes high level, the output of the booster circuit 23 is selected by the output circuit 24, and the potential Vp is outputted as the plate pulse φp. The pulse width of this plate pulse φp corresponds to the delay time set in the timing pulse generation circuit 21.

According to the above embodiment, when data "1" is stored in the transistor Q2 constituting the cell capacitor, an inversion layer is formed in the channel region CH2. Therefore, when the plate electrode PL is boosted at the time of reading data, this transistor Q2 is turned on, and the transistor Q3 is also turned on. Current can be supplied to the line BL. Therefore, the operating margin of the sensor amplifier can be significantly improved.

Moreover, since the amount of charge transferred to the bit line is increased, when DRAM becomes larger in capacity and becomes ultra-fine,
Even when the power supply voltage is lowered to 5 V or less, data can be read out at high speed without depending on the CB /Cs ratio.

[0064] Also, by thin film technology, transistor Q2
and Q3 have a stacked structure, and the gate of transistor Q3 and the channel region of transistor Q2 are shared. Therefore, the area of the cell can be reduced to the same size or more than that of a conventional one-transistor, one-capacitor DRAM.

Furthermore, the pulse generating circuit 13 boosts the voltage of the plate electrode for a short time when reading data. Therefore, since the voltage on the plate electrode is not constantly increased as in the prior art, deterioration of the gate oxide film can be prevented and reliability can be improved.

Furthermore, since current is supplied to the bit line via transistor Q3 and transistor Q1 when reading stored data, the soft error rate can be improved.

Although the thin films 13 and 14 are formed of polysilicon, amorphous silicon may also be used.

Furthermore, the thin films 13 and 14 can also be formed of single crystal silicon. in this case,
It does not have to be a thin film.

Furthermore, in the above embodiment, the transistor Q2
, Q3 are formed by a stacked structure, but are not limited to this, and may be formed by a trench structure or a combination thereof.

FIG. 7 shows a third embodiment of the present invention, and the same parts as in FIGS. 1 and 3 are given the same reference numerals.

Memory cells MC are arranged in a matrix. One ends of the bit lines BL1 to BLn are connected to a column decoder 92 via a sense amplifier 91. Further, one end of the word lines WL1 to WLn is connected to a row decoder 93.
It is connected to the. Memory cell MC is selected by column decoder 92 and row decoder 93, and data read from memory cell MC is sent to sense amplifier 92.
supplied to

The other ends of the word lines WL1 to WLn are connected to one input terminal of AND circuits A1 to An. One input terminal of these AND circuits A1 to An is connected to the pulse generator 11. Output ends of these AND circuits A1-An are connected to plate electrodes PL1-PLn, respectively.

In the above configuration, AND circuits A1 to An
supplies a pulse signal output from the pulse generator 11 to the plate electrode only when selected by the word line. Therefore, since the pulse generator 11 only needs to drive the memory cells in the row direction selected by the word line, the driving capability of the pulse generator 11 can be reduced.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention.

[0075]

Effects of the Invention As detailed above, according to the present invention, even when large capacity, ultra-fine design, and low voltage have progressed, high speed and
In addition, a semiconductor memory device capable of reliably reading stored data is provided.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram shown to explain the operation of FIG. 1;

FIG. 3 is an equivalent circuit diagram showing a second embodiment of the invention.

FIG. 4 is a cross-sectional view showing the structure of the cell shown in FIG. 3.

FIG. 5 is a circuit diagram showing an example of the pulse generation circuit shown in FIG. 1;

FIG. 6 is a waveform diagram shown to explain the operation of FIG. 5;

FIG. 7 is a circuit configuration diagram showing a third embodiment of the invention.

FIG. 8 is an equivalent circuit diagram showing a memory cell of a conventional DRAM.

FIG. 9 is a plan view showing the configuration of the memory cell shown in FIG. 8;

10 is a cross-sectional view taken along line 10-10 in FIG. 9. FIG.

FIG. 11 is a circuit diagram showing a conventional DRAM including peripheral circuits.

FIG. 12 is a waveform diagram shown to explain the operation of FIG. 11;

[Explanation of symbols]

Q1, Q2, Q3...Transistor, 11...Pulse generation circuit, BL...Bit line, WL...Word line.

Claims (14)

[Claims] 1. A first transistor whose gate is connected to a word line, one end of a current path is connected to a bit line, and which selects a memory cell; a second transistor that is determined to be conductive or non-conductive; pulse generating means that supplies a voltage at a predetermined level to the second transistor when reading stored data; , and a third transistor that supplies a current output from the pulse generating means to the bit line. 2. The second and third transistors are formed of thin films, and the gate electrode of the third transistor is formed of a channel region of the second transistor. semiconductor storage device. 3. The second and third transistors are made of polysilicon, and the impurity concentration in their channel regions is lower than the impurity concentration in other parts. The semiconductor storage device described above. 4. The pulse generating means includes an oscillation circuit that generates a pulse signal, a booster circuit that boosts the pulse signal generated by the oscillation circuit to a predetermined potential, and a booster circuit that boosts the pulse signal generated by the oscillation circuit to a predetermined potential. A predetermined potential output from the booster circuit is supplied to the second transistor before the transistor is selected, and the potential is supplied to the second transistor before the first transistor is deselected. 2. The semiconductor memory device according to claim 1, further comprising a supply circuit for stopping the operation. 5. A first transistor having a gate connected to a word line and one end of a current path connected to a bit line; and a first transistor having a gate connected to the other end of the current path of the first transistor. the second selected by the transistor
transistor, this second transistor is determined to be conductive or non-conductive depending on the stored data, pulse generating means connected to one end of the current path of the second transistor, this pulse generating means is connected to one end of the current path of the second transistor, this pulse generating means is supplying a voltage at a predetermined level to the second transistor during reading;
a third transistor having a gate connected to the other end of the current path of the second transistor, one end of the current path connected to the other end of the current path of the first transistor, and the other end connected to the pulse generating means; A semiconductor memory device characterized in that the third transistor is made conductive when the second transistor is made conductive, and supplies the current output from the pulse generating means to the bit line. 6. The second and third transistors are formed of thin films, and the gate electrode of the third transistor is formed of a channel region of the second transistor. semiconductor storage device. 7. The second and third transistors are made of polysilicon, and the impurity concentration of these channel regions is lower than the impurity concentration of these other parts. The semiconductor storage device described above. 8. The pulse generating means includes an oscillation circuit that generates a pulse signal, a booster circuit that boosts the pulse signal generated by the oscillation circuit to a predetermined potential, and a booster circuit that boosts the pulse signal generated by the oscillation circuit to a predetermined potential. A predetermined potential output from the booster circuit is supplied to the second transistor before the transistor is selected, and the potential is supplied to the second transistor before the first transistor is deselected. 6. The semiconductor memory device according to claim 5, further comprising a supply circuit that stops. 9. A MOS type first transistor, the first transistor comprising a diffusion layer forming a source and drain region provided at a predetermined distance in a semiconductor substrate, and a diffusion layer formed on the semiconductor substrate and insulated from the semiconductor substrate. and a gate as a word line provided as a word line to select a memory cell,
formed on one diffusion layer of this first transistor,
a first semiconductor layer constituting a gate electrode of a second transistor; a second semiconductor layer provided insulated on the first semiconductor layer; the second semiconductor layer is the first semiconductor layer; The part corresponding to the channel region is a channel region with a low impurity concentration, and the other part is a plate electrode with a high impurity concentration.
a third semiconductor layer insulated and provided on the second semiconductor layer, which is set at a high level when reading stored data;
One end of the third semiconductor layer is connected to the first semiconductor layer, the other end is connected to the plate electrode, and the impurity concentration of a portion of the third semiconductor layer corresponding to the second semiconductor layer is A semiconductor memory device characterized by having a channel region lower than other parts. 10. The semiconductor memory device according to claim 9, wherein the first to third semiconductor layers are made of polysilicon. 11. The semiconductor memory device according to claim 9, wherein the third semiconductor layer is made of amorphous silicon. 12. The semiconductor memory device according to claim 9, wherein the first to third semiconductor layers are made of single crystal silicon. 13. A first transistor whose gate is connected to a word line, one end of a current path is connected to a bit line, and which selects a memory cell; a second transistor that is determined to be conductive or non-conductive; pulse generating means that supplies a voltage at a predetermined level to the second transistor when reading stored data; , a third transistor for supplying a current output from the pulse generation means to the bit line; a selection signal generation means for generating a selection signal for selecting the word line; and a selection output from the selection signal generation means. A semiconductor memory device comprising supply means for supplying a pulse signal output from the pulse generation means to the second and third transistors in accordance with a signal. 14. The semiconductor memory device according to claim 13, wherein the supply means is constituted by an AND circuit.