JPH0422670B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides feedback control in which input DC is converted into AC with a frequency higher than the commercial power supply frequency and then used as a welding load power source via a transformer and a rectifier circuit. The present invention relates to a power supply device for an arc welding machine with functions.

[Background of the invention]

In order to reduce the size and weight of the overall configuration of the power supply device for arc welding machines, the power frequency is converted to a frequency higher than the commercial power frequency at the stage before the transformer, and the power is transmitted through the transformer, rectifier, and reactor. There are configurations that supply the load.

FIG. 1 is a circuit diagram showing the overall configuration of a power supply device for an arc welding machine of this type which was previously developed by the present applicant, and this will be explained first.

In the figure, 1 is a rectifier that converts a three-phase AC power supply into a DC power supply, 2 is a smoothing capacitor, and 3 is a bridge connection of transistors T ₁ to _{T 4} , with diodes D ₁ to D ₄ connected between their collectors and emitters. An inverter (switching circuit) consists of an inverter (switching circuit) that alternately turns on and off between the pair of transistors T ₁ and T ₄ and the pair of transistors T ₂ and T ₃ , thereby switching the DC current from rectifier 1 from the commercial power frequency. It also outputs AC power at a much higher frequency. 4 is a transformer which inputs the AC output of the inverter 3 and outputs AC at a desired welding voltage.

A rectifier 5 is inserted into the secondary side of the transformer 4 and converts the output of the transformer 4 into direct current, and a reactor 6 is used to stably flow a smoothed direct current to the welding load 7. 8 is a shunt provided between the middle point of the secondary winding of the transformer 4 and the load 7;
Detects the welding current flowing through the The output of the shunt 8 is applied to the − input terminal of a differential amplifier 10 via an amplifier 9. Reference numeral 11 denotes a reference voltage generator for output setting, the output of which is applied to the positive input terminal of the operational amplifier 10. The operational amplifier 10 amplifies the difference signal between the output signal of the reference voltage generator 11 and the current detection signal obtained by amplifying the output signal of the shunt 8 with the amplifier 9, and outputs the output control signal V ₁ to the comparator 12. It is given as follows.

Reference numeral 13 denotes a sawtooth voltage generator, and its output signal (sawtooth wave signal) is input to the - input terminal of the comparator 12, and is also input to the signal distribution circuit 14. The comparator 12 compares the sawtooth wave signal with the output control signal V ₁ of the differential amplifier 10, and when the output control signal V ₁ is smaller, the transistors T ₁ , T ₄ and T ₂ of the inverter 3 Outputs pulse signal _V2 to alternately turn _T3 on and off.

The signal distribution circuit 14 receives the sawtooth wave signal from the sawtooth voltage generator 13 and the output pulse signal from the comparator 12.
V ₂ is input, two types of output pulses V ₃ and V ₄ which are alternately turned on and off are generated, one of which is given to the inverter drive circuit 15 and the other to the inverter drive circuit 16 . Inverter drive circuit 15, 16
creates two-phase pulse signals V _{5 ,} V ₆ ; V ₇ , V ₈ that alternately turn on and off in response to output pulses V 3 , V ₄ , and connects transistors T ₁ , T ₄ and T ₂ , T ₃ to Turn on and off alternately. Note that the inverter drive circuit 15,
Reference numeral 16 includes a transistor whose switching speed is faster than that of transistors T ₁ to T ₄ and a delay circuit, and the switching speed can be arbitrarily adjusted by the function of the delay circuit.

The power supply device for an arc welding machine configured in this manner has the following problems. That is _, an instantaneous _noise pulse Q as _shown in FIG. When superimposed, the output pulse signal V ₂ of the comparator 12 generates alternating short pulses within a short period of time. This disturbs the timing of the output pulses V ₃ and V ₄ to the transistor drive circuits 15 and 16, for example, the output pulse V ₃ causes the transistors T ₁ and T ₄
This will cause the other transistors T ₂ and T ₃ to become conductive before they are turned off, causing a short circuit in the power supply.

Also, if the nozzle pulse width is too short, the output pulses V ₃ , V ₄ , here V ₄ , may occur as transistors T ₁ , T ₄ or T ₂ , T ₃ , here T ₂ , T ₃ . may not turn on. in this case,
Even if it does not cause a power supply short circuit as described above, if the excitation current is continuously generated as the output pulse of the welding power source with the same polarity and the same pulse width as normal, as shown in the _V9 waveform in Figure 2. It flows to the transformer 4 multiple times (twice in the illustrated example). As a result, the transformer 4 becomes saturated and the switching transistors T ₁ ,
There was a problem in that an overcurrent flows through T ₄ or T ₂ , T ₃ , here T ₁ , T ₄ , causing destruction of those elements.

[Purpose of the invention]

An object of the present invention is to provide a power supply device for an arc welding machine that can prevent inverter circuits from malfunctioning due to noise pulses Q, power supply short circuits, and transformer saturation, and which can prevent destruction of switching elements, etc. It is about providing.

[Summary of the invention]

The present invention provides two-phase pulse signals V ₅ , V ₆ ; V ₇ , V ₈
an inverter 3 that converts the input DC into an AC with a frequency higher than the commercial AC power frequency, a transformer 4 connected to the inverter, and a rectifier circuit 5, 5 that converts the output of the transformer into DC. A current detector 8 that detects the welding current output from this rectifier circuit, a first comparison circuit 10 that compares the output of this current detector with a reference voltage for output setting, and an output of this first comparison circuit V ₁ and a predetermined sawtooth wave signal _S13 , and outputs a signal _V2 whose pulse width is controlled according to the first comparison circuit output.
2, and two types of pulse signals V ₃ for driving the inverter in response to the output of the second comparison circuit.
A signal distribution circuit 14 that outputs V ₄ and one pulse signal V 3 of two types of pulse signals from this signal distribution circuit are inputted to drive one of the two-phase pulse signals V ₃ that drives the inverter. ₅ , _V6 , and the other of the two types of pulse signals from the signal distribution circuit, _V4 , is inputted to drive the inverter. In a power supply device for an arc welding machine, the power supply device includes a second inverter drive circuit 16, the other of which is V ₇ and V ₈ , two types of pulse signals for driving the inverter in response to the output of the second comparison circuit. A signal distribution circuit main body 14a that outputs the original pulse signals v ₃ and v ₄ of V 3 and V ₄ , and a source of the pulse signal V ₃ (or V ₄ ) of one (or the other ₎ of the two types of pulse signals. pulse signal v ₃
(or v ₄ ) from the trailing edge of each pulse of pulse signal V ₄ ( or V ₃ ), the first timer circuit 21, R ₁ ,
_{C 1} ; 22, R ₁ , C ₁ and _the original pulse signal v ₃ (or
_v4 ) from the trailing edge of each pulse of the sawtooth signal _S13
A second time limit circuit 20, R 2 , which prohibits pulse-on of the one (or the other) pulse signal V ₃ (or V ₄ ) for a second predetermined period slightly exceeding one cycle of the pulse signal V 3 (or V ₄ ).
The interlock circuit 14b consisting of C ₂ ; 23, R ₂ and C ₂ constitutes the signal distribution circuit to prevent the inverter circuit from malfunctioning due to noise such as the noise pulse Q.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 3 to 5.

FIG. 3 is a circuit diagram showing the overall configuration of the power supply device for an arc welding machine according to the present invention, and FIG. 4 is a circuit diagram showing the main parts of the device. In both these figures, the first
The same reference numerals as in the figures indicate the same or corresponding parts. In addition,
14 in FIG. 3 is the signal distribution circuit 1 in FIG.
This is a signal distribution circuit consisting of a signal distribution circuit main body 14a and an interlock circuit 14b having the same configuration as that of 4.

As can be seen from FIG. 3, the IC 17 in FIG. 4 receives the signals from the amplifier 9 and the reference voltage generator 11 as input, and receives the pulse signal V ₂ after distribution before the interlock circuit 14b functions. Pulse (original pulse) v ₃ , v ₄ (output pulse in Figure 1)
V ₃ , V ₄ ), and the circuit portions of the differential amplifier 10, comparator 12, sawtooth voltage generator 13, and signal distribution circuit main body 14a in FIG. 3 are configured as an integrated circuit. be.

The pulses v ₃ and v ₄ after the distribution of the pulse signal V ₂ output from the IC 17 are the output control signal V ₁ of the operational amplifier 10 or the voltage generator, as described in the explanation regarding FIG. When a noise pulse Q is superimposed on the sawtooth wave signal S ₁₃ from 13, the timing is disturbed (output pulse in Fig. 1).
V ₃ , V ₄ ).

The present invention eliminates occurrence of power supply short circuit and saturation of the transformer 4 due to disturbance in the timing of pulses v ₃ and v ₄ , and prevents destruction of switching transistors T ₁ , T ₄ and T ₂ , T ₃ etc. Therefore, an interlock circuit 14b is provided.

In FIG. 4, 18 and 19 are NAND circuits. Flip-flop circuits 20 to 23 are used to set the off-time of the output pulse _V9 , and flip-flop circuits 21 and 22 are used to set the on-time of the output pulse _V9 . Furthermore, the flip-flop circuits 20 and 23 each include a resistor R ₂ and a capacitor.
C ₂ , from each trailing edge of the original pulse V ₃ (or V ₄ ) of one (or the other) pulse V ₃ (or V ₄ ) for a predetermined period of time slightly exceeding one period of said sawtooth signal S ₁₃ , here, 28 μs, as described later, constitutes a second time limit circuit that prohibits the pulse-on of the one (or the other) pulse V ₃ (or V ₄ ). The flip-flop circuits 21 and 22 each have a resistor R ₁ and a capacitor C ₁ , and one (or the other) pulse V ₃ (or
From each trailing edge of the original pulse v ₃ (or v ₄ ) of V ₄ ), a predetermined period of time approximately corresponds to the time required for the switching operation of the inverter 3, as will be described later.
5μs is the other (or one) pulse signal V ₄
(or V ₃ ) constitutes a first time limit circuit that prohibits pulse-on.

24 is an AND circuit that performs the logical product of the outputs of the NAND circuit 18 and the flip-flop circuit 20; 25 is
This is an AND circuit that takes the logical product of the outputs of the NAND circuit 19 and the flip-flop circuit 23. 26 is
An AND circuit 27 takes the logical product of the outputs of the AND circuit 24 and the flip-flop circuit 22, and 27 is the AND circuit 25.
and the output of the flip-flop circuit 21.
It is an AND circuit, and these AND circuits 26, 2
The output of 7 is an output pulse to the transistor drive circuits 15 and 16 that is not affected by the noise pulse Q.
Output as V ₃ and V ₄ .

The signal waveforms of each part in Fig. 3 and Fig. 4 are shown in Fig. 5.
As shown in the figure, the operation of the device of the present invention will be described below using this signal waveform diagram. In addition,
In FIG. 5, the same symbols as in FIG. 2 represent the same or corresponding signals and pulses. Further, as shown in FIG. 5, each pulse of the signal _V2 is given a symbol .about., and it is assumed that one of the pulses represents the disturbance caused by the noise pulse VQ.

First, the pulse train of the signal V ₂ from the comparator 12 in the IC 17 is transmitted to the main body 29 of the signal distribution circuit in the IC 17.
As a result of the alternating distribution, the even-numbered pulses of the signal _V2 are distributed to the signal a, and the odd-numbered pulses are distributed to the signal f. As a result, the 9th pulse of the signal V ₂ corresponding to the noise pulse Q is distributed to the signal f, and the 10th pulse is distributed to the signal a. Here, the signals a,
f is the pulses v ₃ and v ₄ (output pulses V ₃ and V ₄ in FIG. 1) outputted from the signal distribution circuit main body 14a in the IC 17, whose polarities are inverted by the NAND circuits 18 and 19. Therefore, the output of the pulse width-controlled pulses v ₃ and v ₄ from the signal distribution circuit main body 14a to the flip-flop circuits 20 to 23 is as follows.
This means the falling of the pulses V ₃ and V ₄ .

When the signal a is input to the flip-flop circuit 20, the polarity of the output signal b of the flip-flop circuit 20 is reversed (inverted from H level to L level in FIG. 5), but after 28 μs, the polarity is reversed again.
Returns to original polarity. When the signal a is input to the flip-flop circuit 21, the polarity of the output signal i is inverted, and after another 5 μs, the polarity is inverted again to the original polarity.

In the case of the signal f, as in the case of the signal a, when it is input to the flip-flop circuits 23 and 22,
The polarities of the output signals g and d from the flip-flop circuits 23 and 22 are inverted, and each of the output signals g and d is inverted for 28 μs.
After 5 μs, the polarity is reversed again to the original polarity.

Here, the reason for giving delay times (time limits) of 28 μs and 5 μs is as follows. In other words, in this example, the fundamental frequency of the illustrated circuit operation is 20KHz, and the period is
50μs, and based on this a sawtooth wave with a period of 25μs
Got _S13 . Therefore, the signal V ₂ is calculated as
Although the maximum period is 25 μs, the switching time of the transistors T ₁ , T ₄ and T ₂ , T ₃ of the inverter circuit 3 requires about 3 μs, and if it is shorter than this, a short circuit will occur in the power supply. Therefore, in this embodiment, 5 μs was set with some margin. This setting applies to each external capacitor C ₁ of the flip-flop circuits 21 and 22,
This is done by resistor R ₁ .

In addition, the above transistors T ₁ and T ₄ side or T ₂ and T _{3 side}
When the side is continuously conductive for two pulses of the signal V ₂ , biased magnetization occurs in the transformer 4 . In order to prevent this, it is necessary to set a minimum pulse interval of 25 μs in calculations, but in this embodiment, 28 μs is set with some margin. This setting is the flip-flop circuit 20,
This is performed using 23 external capacitors C ₂ and resistors R ₂ .

Now, the output signal c from the AND circuit 24 becomes the AND condition output of the signals a and b, and the AND circuit 2
The output signal h from 5 becomes an AND condition output of signals f and g. Output signal e from AND circuit 26
is the AND condition output of signals c and d, and
Output signal j from circuit 27 is the sum of signals i and h.
This is an AND conditional output.

Output signals e and j correspond to signals V ₃ and V ₄ to transistor drive circuits 15 and 16, respectively, shown in FIG.

Now, when a noise pulse Q is superimposed on the sawtooth wave signal S ₁₃ and a pulse is generated in the signal V ₂ , the same pulse becomes signals v ₃ and v ₄ , which are output from the IC 17 and processed by the NAND circuits 18 and 19. After the polarity is inverted, the signal becomes a pulse of signal a and a pulse of signal f. Then, the signal d falls for 5 μs from the fall of the pulse of the signal f, and the signal i falls for 5 μs from the fall of the pulse of the signal a. During the 5 μs period during which the signal d is at the L level, the input signal h of the AND circuit 27 is prohibited from being output, and the output signal j is not output. Similarly, for 5 μs while the signal i is at the L level, the input signal c of the AND circuit 26 is prohibited from being output, and the output signal e is not output. Therefore, signal e and signal j each start from the falling point of the other side's signal.
Since pulse V ₃ and pulse V 4 do not rise for 5 μs, pulses V 3 and V ₄ do not output continuous ON signals in a short period of time (within 5 μs), and transistors T ₁ , T ₄ and T of inverter circuit 3 ₂ and _T3 are prevented from shorting (short circuiting the power supply).

Next, the signal b is at the L level for 28 μs from the fall of the pulse of the signal a, and the signal g is at the L level for 28 μs from the fall of the pulse of the signal f. Since noise pulse Q entered while signal b was at L level due to the pulse of pulse signal a, a pulse was generated in signal a,
Signal b also maintains the L level for 28 μs from the fall of the pulse signal a. Therefore, while signal b is at L level, AND
The pulse of the signal a input to the circuit 24 is the signal c
Since it is not output to the signal e, it does not appear in the signal e either. That is, it does not appear in the output pulse _V9 either.

The signal g starts from the falling edge of the pulse of the signal f.
It stays at L level for 28μs, then rises and after a short time, the pulse caused by the noise pulse Q becomes the signal f.
When this pulse falls, the signal g falls and remains at L level for 28 μs.
The pulse of the signal f at this time satisfies the AND condition with the signal g in the AND circuit 25 and the AND condition with the signal i in the AND circuit 27, so it is output as the signal j, but since the pulse width is extremely narrow, the inverter Transistor of circuit 3 (or
FET) T ₁ , T ₄ and T ₂ , T ₃ are never turned on. That is, it does not appear in the output pulse _V9 .

As described above, the pulse in the signal _V2 generated by the noise pulse Q does not appear in the output pulse _V9 , and the waveform of the output pulse _V9 alternates between positive and negative polarity. Therefore, problems such as power supply short circuits and saturation of the transformer 4 due to biased magnetism, which have been problems in conventional devices, do not occur.

Next, an explanation will be given of the operation when the pulse width of the pulse _V2 in FIG. 5 is different from the illustrated example.

(1) When the pulse width of the pulse is opposite to that shown in the illustration (when is wide and is extremely narrow). In this case, the pulse width of the pulse in FIG. 5a becomes extremely narrow, and the pulse width of the pulse in FIG. 5f becomes wide. As a result, V ₉ (power supply output pulse) in FIG. 5 has a positive (upper) pulse waveform with a width corresponding to the pulse width at a location corresponding to the pulse. The pulse waveform does not appear in the part corresponding to the pulse, and the pulse waveform has the same polarity as the pulse waveform in the part corresponding to the pulse, but the width is reduced according to the pulse width of the pulse waveform. A pulse waveform 〓 occurs. This is because the falling point of the pulse in Figure 5 f is shifted backwards (toward the right in the figure) and a delay of 28 μs occurs from there, so the pulse in Figure 5 g shown below the pulse in Figure 5 f is delayed. This is because the width becomes narrower accordingly. Note that since the falling point of the pulse in FIG. 5a does not change, there is no change in the _V3 side of FIG. 5e.

(2) When the pulse widths of both pulses are valid, that is, both have medium pulse widths. This case is similar to case (1) above (where is wide and is extremely narrow). That is, in this case, it is considered that the falling point of the pulse in FIG. In this case as well, there is a delay of 28 μs from the falling point of the pulse in Fig. 5 f, which is slightly shifted forward, so the width of the pulse in Fig. 5 g shown below the pulse in Fig. 5 f becomes slightly wider. As a result, the waveform in Figure 5 V ₉ is:
A positive (upper) pulse waveform with a width corresponding to the pulse width is generated at a location corresponding to the pulse.
And the pulse waveform does not appear in the part corresponding to the pulse, and the pulse waveform has the same polarity as the pulse waveform in the part corresponding to the pulse, but the width increases (becomes wider) according to the pulse width of the pulse waveform. A pulse waveform is generated. In addition, Figure 5a
Since the falling point of the pulse does not change, there is no change in the _V3 side of Figure 5e.

Here, in the above embodiment (the example shown in FIG. 5), the polarity of the output pulse V ₉ is alternately positive and negative, whereas in the examples (1) and (2) above, the polarity of the output pulse V ₉ is are continuous with the same polarity. However, as mentioned above, this waveform of the same polarity is a pulse waveform and a pulse waveform whose width is narrower (or wider) by a width corresponding to the pulse width of this pulse waveform (the total width of these is
(The value is constant depending on the time set by each external capacitor C ₂ and resistor R ₂ of the flip-flop circuits 20 and 23), and according to experiments by the inventors, there is no biased magnetization during welding and in the welding result. No adverse effects were found, and it was concluded that at least the transformer 4 had not been saturated.

〔Effect of the invention〕

According to the present invention, the timing of pulses to the transistor drive circuit is not disturbed by noise such as noise pulses, and therefore short circuits of the power supply can be prevented, and output pulses of the same polarity are not continuously output. Even if output pulses of the same polarity occur consecutively, the sum of the pulse widths of the consecutive pulses will always be a small value that does not exceed a predetermined value, so the transformer will not be saturated, and switching elements etc. due to overcurrent will not be saturated. It has the effect of preventing destruction.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the overall configuration of a power supply device for an arc welding machine that was previously developed by the applicant.
The figure is a signal waveform diagram of each part of the device, FIG. 3 is a circuit diagram showing the overall configuration of the power supply device for an arc welding machine according to the present invention, FIG. 4 is a circuit diagram showing the main parts of the device, and FIG.
The figures are signal waveform diagrams of various parts in FIGS. 3 and 4. 1, 5... Rectifier, 3... Inverter circuit (inverter), _T1 to _T4 ... Switching transistor, 4... Transformer, 7... Welding load, 8... Shunt, 10... Differential amplifier , 11...Reference voltage generator for output setting, 12...Comparator, 13...Sawtooth voltage generator, 14...Signal distribution circuit, 14a...
...Signal distribution circuit main body, 14a...Interlock circuit, 15, 16...Transistor drive circuit, 1
7...IC.

Claims (1)

[Scope of Claims] 1. An inverter 3 that receives two-phase pulse signals V ₅ , _{V 6 ;} transformer 4, rectifier circuits 5, 5 that convert the output of this transformer into direct current, and a current detector 8 that detects the welding current output from this rectifier circuit.
A first comparison circuit 10 compares this current detector output with a reference voltage for output setting, and compares this first comparison circuit output V ₁ with a predetermined sawtooth wave signal S ₁₃ . a second comparison circuit 12 that outputs a signal _V2 whose pulse width is controlled according to the comparison circuit output of;
A signal distribution circuit 14 receives the output of this second comparator circuit and outputs two types of pulse signals V ₃ and V ₄ for driving the inverter, and a signal distribution circuit 14 that outputs two types of pulse signals V 3 and V 4 for driving the inverter, and one of the two types of pulse signals from this signal distribution circuit. One pulse signal
A first inverter drive circuit 15 receives V ₃ and drives one of the two-phase pulse signals V ₅ and V ₆ to drive the inverter, and one of the two types of pulse signals from the signal distribution circuit. the other pulse signal
A power supply device for an arc welding machine comprising a second inverter drive circuit 16 that receives V ₇ and V ₈ of the two-phase pulse signals that drive the inverter by inputting V ₄ , the signal distribution circuit a signal distribution circuit main body 14a that receives the output of the second comparator circuit and outputs original pulse signals v ₃ and v ₄ of two types of pulse signals V ₃ and V ₄ for driving the inverter; The original pulse signal of one (or the other) of the seed pulse signals V ₃ (or V ₄ )
A first predetermined time period from the trailing edge of each pulse of v ₃ (or v ₄ ), approximately corresponding to the time required for the switching operation of the inverter, is the pulse signal V of the other (or one) of the two types of pulse signals. ₄ (or V ₃ ), the first timer circuit 21, R ₁ ,
_{C 1} ; 22, R ₁ , C ₁ and _the original pulse signal v ₃ (or
_v4 ) from the trailing edge of each pulse of the sawtooth signal _S13
A second time limit circuit 20, R 2 , which prohibits pulse-on of the one (or the other) pulse signal V ₃ (or V ₄ ) for a second predetermined period slightly exceeding one cycle of the pulse signal V 3 (or V ₄ ).
A power supply device for an arc welding machine, comprising an interlock circuit 14b consisting of C ₂ ; 23, R ₂ and C ₂ .