JPH04226032A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a reliable semiconductor device, with high yield, having a structure in which a wiring layer is formed over a sloping region so that it may not become thin. CONSTITUTION:A semiconductor substrate 100 includes active regions 101 and isolation regions 102 on one main surface. An insulating film 110 is formed on the substrate, and a wiring layer 150 is formed on one surface 130 of the insulating film. There is a sloping region on the surface 130 of the insulating film 110, and the wiring layer 150 overlays the sloping region. The side edges 152 of the wiring layer 150 are located in areas outside the sloping region where the main surface and the surface 130 are parallel.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device having a wiring layer on an interlayer insulating film,
The present invention also relates to a semiconductor device having, on one surface of an interlayer insulating film, a stepped region caused by another wiring layer formed on a substrate or a boundary between an element region and an element isolation region, and a method for manufacturing the same.

0002

2. Description of the Related Art A conventional semiconductor device having a stepped region on one surface of an interlayer insulating film will be described using an EEPROM memory cell as an example.

FIG. 12 is a diagram showing a part of a planar pattern of a memory cell of a conventional EEPROM, and FIG.
A cross-sectional view taken along line 3-13, FIG. 14 is 12-1 in FIG.
FIG. 2 is a cross-sectional view along line 2;

As shown in FIGS. 12 to 14, the conventional E
An EPROM memory cell includes a silicon substrate 100 having an element region 101 and an element isolation region 102 on its main surface.
, a floating gate 104A formed on the substrate 100, a control gate 108A formed on the floating gate 104A so as to be capacitively coupled via an insulating film, and spaced apart from each other on both sides thereof. It is composed of a stacked structure selection gate 106A, a stacked structure readout gate 106B, and the like. An interlayer insulating film 110 is formed on the entire surface to electrically isolate these various gates from each other. A wiring layer 114 configuring column selection wiring and the like is formed on the interlayer insulating film 110.

[0005] In a memory cell configured as described above,
For example, due to restrictions on the wiring pattern, the wiring layer 114
For example, read gate 106B and control gate 1
08A is bent over a portion of each other.

At this time, conventionally, a wiring layer 114 having a width W2 narrower than the width W1 of the wiring layer 113 to be originally formed is formed above the above-mentioned mutual gap. this is,
This is a problem called "thin wiring."

[0007] This thinning of the wiring occurs not only between the wirings described above, but also when the side surface of the wiring layer 114 is placed near the boundary 103 between the element region 101 and the element isolation region 102. Also here, the wiring layer 114 is formed having a width W4 narrower than the width W3 of the wiring layer 113 to be originally formed.

Furthermore, as shown in FIG. 14, in the above-mentioned boundary portion 103, the element isolation region 102 is depressed from the surface of the element region 101 due to various etching steps during manufacturing. Therefore, the upper surface 130 of the interlayer insulating film 110 has a complicated uneven shape.

It is presumed that the thinning of the wiring as described above is a problem in the manufacturing method of the semiconductor device, especially when forming the wiring layer 114.

Next, a conventional manufacturing method will be explained with reference to FIGS. 15 to 22.

15 to 19 are views showing cross sections corresponding to the cross section in FIG. 13 in the order of manufacturing steps, and FIGS. 20 to 2
2 is a diagram illustrating a cross section corresponding to the cross section of FIG. 14 showing only important steps in order.

First, as shown in FIG. 15, an element isolation region 102 is selectively formed on the main surface of a silicon substrate 100 using ordinary element isolation technology, and then a floating region is formed using an ordinary manufacturing method. - gate 104A, control gate 108A,
A selection gate 106A and a read gate 106B are formed. Next, an interlayer insulating film 110 is formed on the entire surface, and then an aluminum layer 112 that will become a wiring layer is formed on the entire surface.

Next, as shown in FIG. 16, a photoresist 200 is applied onto the aluminum layer 112.

Next, as shown in FIGS. 17 and 20, a mask 20 having light blocking portions 203 with widths P1 and P3 is formed.
The photoresist 200 is selectively exposed by irradiating it with ultraviolet light 204 using UV light 204.

The light blocking section 203 has a predetermined wiring pattern including the wiring layer 114 shown in FIGS. 12 to 14 described above.

Further, the width P1 shown in FIGS. 17 and 20 corresponds to the wiring width W1 to be formed in the wiring layer 114, and similarly, the width P3 corresponds to the wiring width W3 to be formed. Furthermore, the wiring pattern drawn by the light blocking section 203
The readout gate 106B and control gate 108
In order to form a wiring layer which is bent over a portion of the portions A, the wiring layer is formed so as to extend over the stepped region caused by various gates of the interlayer insulating film 110, which is the underlying film of the aluminum layer 112. The step region refers to a region where the upper surface 130 of the interlayer insulating film 110 in contact with the aluminum layer 112 is inclined with respect to the main surface of the substrate 100.

Similarly, since the light shielding part 203 forms a wiring layer along the boundary part 103 between the element region 101 and the element isolation region 102, the step region (the above-mentioned complicated (referring to the uneven shape).

Here, the upper surface 1 of the underlying interlayer insulating film 110 is
Since aluminum layer 30 is inclined with respect to the main surface of substrate 100 due to the above-mentioned step region, aluminum layer 112 formed thereon is formed in a state that reflects this inclination. As a result, the photoresist 200 of the aluminum layer 112
The surface 132 in contact with is also inclined with respect to the main surface of the substrate 100. As a result, a portion of the ultraviolet light 205 that has passed through the photoresist 200 is reflected by the above-mentioned surface 132, and the area of the photoresist 200 that should be unexposed is narrowed as shown in the area 206 shown in FIGS. 18 and 21.

Photoresist 200 thus exposed
When developed, a photoresist pattern 208 is formed which is narrower in width than the photoresist pattern 207 that should originally be formed, as shown in FIGS. 19 and 22. When a wiring layer is formed by etching the aluminum layer 112 using this narrow pattern 208 as a mask, a wiring layer 114 having a width narrower than the wiring layer 113 to be originally formed as shown in FIGS. 12 to 14 is formed. It is formed.

Wiring layer 1 having such a narrow width portion
In No. 14, for example, the wiring layer 114 is easily cut when a surface protection film (not shown) is formed, resulting in a decrease in yield. Further, even if the wiring layer 114 is not cut at this time, the wiring is likely to deteriorate at the thinner part after being shipped from the market, which may lead to problems such as the wiring breaking while the device is in use. This may reduce the reliability of the device and, by extension, the reliability of the device itself.

[0021]

[Problem to be solved by the invention] As explained above,
In a conventional semiconductor device, a wiring layer pattern is obtained without taking into consideration the stepped region of a base film of a metal layer that is to become a wiring layer. As a result, the wiring becomes thinner,
This results in a reduction in yield and equipment reliability.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device having a wiring layer formed over a step region without causing thinning of the wiring layer. It has a structure that can be manufactured with high yield,
Another object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same.

[0023]

[Means for Solving the Problems] A semiconductor device of the present invention includes: a semiconductor substrate having an element isolation region and an element region on a main surface; an insulating film formed on the substrate; and one surface of the insulating film. A semiconductor device comprising a wiring layer formed on a semiconductor device, wherein one surface of the insulating film has a stepped region that is inclined with respect to the main surface of the substrate, and the wiring formed over the stepped region The layer is characterized in that a side surface of the layer that is substantially parallel to the step region is located outside the step region and in an area where the one surface and the main surface are substantially parallel to each other. .

Furthermore, a second wiring layer different from the wiring layer is present between the insulating film and the substrate in the vicinity of the step region, and a layer of the wiring layer is provided above the second wiring layer. It is characterized by having side surfaces that are approximately parallel to the stepped region.

Furthermore, a boundary between the element isolation region and the element region on the main surface of the substrate exists below the insulating film near the step region, and a step of the wiring layer is present above the element region. It is characterized by having side surfaces that are approximately parallel to the area.

The manufacturing method also includes: (a) forming an element isolation region for separating element regions on the main surface of a semiconductor substrate; and (b) forming a first wiring layer on the substrate. (c) forming an insulating film over the entire surface; and (d)
and forming a second wiring layer on one surface of the insulating film. There is a step region on one surface of the insulating film near the first wiring layer that is inclined with respect to the main surface of the substrate, and when forming the second wiring layer on the step region, the step (d) In the step, a side surface of the second wiring layer that is substantially parallel to the step region is removed from the step region and placed in an area where the one surface and the main surface are substantially parallel to each other. The method is characterized in that the second wiring layer is formed using a mask with a pattern drawn thereon.

[0027]

[Function] In the semiconductor device as described above, the wiring layer formed over the step region has a side surface extending approximately parallel to the step region out of the side surface thereof, and a side surface extending substantially parallel to the step region. One surface of the interlayer insulating film and the main surface of the substrate are arranged in substantially parallel and equal regions. That is, since the wiring layer is formed so as to straddle the step region, the wiring does not become thin in the step region, and the wiring layer has a sufficiently wide width. As a result, the wiring layer is difficult to break both during the manufacturing process and during use of the device, resulting in a structure that can be manufactured with high yield and the device itself having high reliability.

Further, in the manufacturing method, the second wiring layer is formed such that, of the side surfaces of the second wiring layer, a side surface substantially parallel to the step region is removed from the step region, and Since the one surface and the main surface are formed using a mask arranged in substantially parallel and equal areas, even if some of the light transmitted through the photoresist is reflected on the surface of the metal layer that will become the second wiring layer, The light is reflected approximately in the direction in which it is incident. This allows the pattern drawn on the mask to be faithfully drawn on the photoresist.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described by way of examples with reference to the drawings.

This embodiment will be explained using an EEPROM memory cell as an example.

FIG. 1 shows an EEP according to an embodiment of the present invention.
2 is a cross-sectional view taken along line 2-2 in FIG. 1, and FIG. 3 is a cross-sectional view taken along line 2-2 in FIG. 1.
It is a cross-sectional view along line -3.

As shown in FIGS. 1 to 3, EEPROM
The memory cell has an element region 101 and an element isolation region 1.
Silicon substrate 100 having 02 on the main surface, substrate 10
Floating gate 104A formed on 0, floating gate 10
The control gate 108A is formed on the control gate 4A so as to be capacitively coupled through an insulating film, and the stacked structure selection gate 106A and the stacked structure readout gate 106B are formed separately on both sides of the control gate 108A. has been done. An interlayer insulating film 110 is formed on the entire surface to electrically isolate these various gates from each other. Interlayer insulation film 11
0, there is a wiring layer 150 that constitutes column selection wiring, etc.
is formed.

In the memory cell configured as described above,
For example, due to restrictions on the wiring pattern, the wiring layer 150
For example, read gate 106B and control gate 1
Suppose that it is bent and placed on a part of the 08A. Furthermore, it is assumed that the wiring layer 150 is arranged along the boundary 103 between the element region 101 and the element isolation region 102. In addition, above-mentioned mutually and above the boundary part 103,
This is a step region where the upper surface 130 of the interlayer insulating film in contact with the wiring layer is inclined with respect to the main surface of the substrate 100.

In the case where a wiring layer is formed over a step region, in the present invention, the side surface 152 of the wiring layer 150, which is approximately parallel to the step region, is formed so that the upper surface 130 and the main surface of the substrate 100 are approximately parallel to each other. Extend to equal area. As for the above-mentioned substantially parallel regions, it is desirable to select, for example, regions above the control gate 108A and the readout gate 106B, and also above the boundary portion 103.
In the above, it is desirable to select a region that is above the element region 101.

These areas, first, the control gate 108A
This is because the upper surface 130 and the substrate 100 are presumed to be approximately parallel to each other on the upper surface and the read gate 106B because both have a certain width necessary for the wiring. be. Further, on element region 101, this region is, needless to say, on the main surface of substrate 100, and therefore, upper surface 130 and the main surface of substrate 100 are substantially parallel to each other.

In this embodiment, since the side surface 152 that is substantially parallel to the stepped region of the wiring layer 150 is disposed above these, an overlapping portion that overlaps each gate and the element region is formed. R is provided. As a result, the wiring layer 15
The above-mentioned width W1 between the control gates 10 and 10
8A and the readout gate 106B, and similarly the width W on the boundary portion 103.
3 also includes an overlapping portion R with respect to the element region.

Next, a method for manufacturing the memory cell according to the above embodiment will be explained with reference to FIGS. 4 to 11.

4 to 8 are views showing cross sections corresponding to the cross section in FIG. 2 in the order of manufacturing steps, and FIGS. 9 to 11 are views corresponding to the cross section in FIG.
FIG. 2 is a diagram showing only important steps in a cross section corresponding to the cross section of FIG.

First, as shown in FIG.
A device isolation region 102 is selectively formed on the main surface of the device 00 using a normal device isolation technique, and then a floating gate 104A, a control gate 108A, and a selection gate are formed by a normal manufacturing method. 106A and read gate 106B are formed. Next, an interlayer insulating film 110 is formed on the entire surface, and then an aluminum layer 112 that will become a wiring layer is formed on the entire surface.

Next, as shown in FIG. 5, a photoresist 200 is applied onto the aluminum layer 112.

Next, as shown in FIGS. 6 and 9, the photoresist 200 is selectively exposed by selectively irradiating ultraviolet rays 204 using a mask 202 having light blocking portions 203 with widths P1 and P3. do.

The light blocking section 203 has a predetermined wiring pattern including the wiring layer 150 shown in FIGS. 1 to 3 described above. This wiring pattern is used for the readout gate 106.
It bends between B and the control gate 108A, bends again at the boundary 103, and extends along the boundary 103.

[0043] Furthermore, the light blocking section 203 shown in FIGS. 6 and 9
The width P1 corresponds to the width W1 of the wiring layer 150 including the overlapping portion R shown in FIGS. 1 to 3, and similarly the width P3 corresponds to the width W3 including the overlapping portion R.

Here, the interlayer insulating film 110 has stepped regions between each gate and on the boundary, as in the prior art. However, in the present invention, as described above, the side surface that is substantially parallel to the stepped region of the wiring layer is parallel to the upper surface 130 of the interlayer insulating film 110 on the gate and the element region and the main surface of the substrate 100. It is formed with a wiring layer pattern extending over an equal area.

Therefore, even if the exposure progresses as shown in FIGS.
Reflections on the surface 132 in contact with the photoresist 200 of No. 12, especially those reflected toward the pattern to be formed, can be suppressed as much as possible. Photoresist 200 can be exposed.

Photoresist 200 thus exposed
When developed, as shown in FIGS. 8 and 11, a photoresist pattern is obtained that faithfully reproduces the pattern of the light blocking portion 203 without narrowing due to reflection of ultraviolet rays 204.
208 is obtained. When the aluminum layer 112 is etched using this pattern 208 as a mask, the patterns shown in FIGS. 1 to 3 are etched.
A wiring layer 150 with no local thinning of wiring as shown in FIG.
can be obtained.

With the semiconductor device having the structure shown in FIGS. 1 to 11 and its manufacturing method, even if the wiring layer 150 is formed over the step region of the interlayer insulating film 110, the wiring layer 150 No thinning occurs. Therefore, for example, when forming a surface protection film (not shown), the wiring layer 15
There is no chance of 0 being cut off, and due to the structure of the device, it can be manufactured at a high yield. In addition, since there is no local thinning of the wiring layer 150, it is less prone to deterioration, preventing problems such as the wiring layer 150 breaking during use of the device, and dramatically improving the lifespan of the device. It is.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the scope of the invention.

[0049]

As explained above, according to the present invention, in a semiconductor device having a wiring layer formed over a stepped region, the wiring layer is not thinned and can be manufactured with high yield. It is possible to provide a semiconductor device that has a flexible structure and is highly reliable, and a method for manufacturing the same.

[Brief explanation of the drawing]

[Fig. 1] EEPROM according to an embodiment of the present invention
FIG. 3 is a diagram showing a part of a planar pattern of a memory cell.

FIG. 2 is a sectional view taken along line 2-2 in FIG. 1.

FIG. 3 is a sectional view taken along line 3-3 in FIG. 1.

[Figure 4] EEPROM according to an embodiment of the present invention
FIG. 3 is a first cross-sectional view corresponding to the cross-section shown in FIG. 2, showing the memory cell in the order of manufacturing steps.

[Figure 5] EEPROM according to an embodiment of the present invention
FIG. 3 is a second cross-sectional view corresponding to the cross-section shown in FIG. 2, showing the memory cell in the order of manufacturing steps.

[Fig. 6] EEPROM according to an embodiment of the present invention
FIG. 3 is a third cross-sectional view corresponding to the cross-section shown in FIG. 2, showing the memory cell in the order of manufacturing steps;

[Figure 7] EEPROM according to an embodiment of the present invention
FIG. 3 is a fourth cross-sectional view corresponding to the cross-section shown in FIG. 2, showing the memory cell in the order of manufacturing steps;

[Fig. 8] EEPROM according to an embodiment of the present invention
FIG. 3 is a fifth cross-sectional view corresponding to the cross-section shown in FIG. 2, showing the memory cell in the order of manufacturing steps;

[Figure 9] EEPROM according to an embodiment of the present invention
FIG. 4 is a first cross-sectional view corresponding to the cross-section shown in FIG. 3, showing the memory cell in the order of manufacturing steps.

FIG. 10: EEPRO according to an embodiment of the present invention
FIG. 4 is a second cross-sectional view corresponding to the cross-section shown in FIG. 3, showing the memory cell of M in the order of manufacturing steps;

[Fig. 11] EEPRO according to an embodiment of the present invention
FIG. 4 is a third cross-sectional view corresponding to the cross-section shown in FIG. 3, showing the memory cell of M in the order of manufacturing steps;

FIG. 12 is a diagram showing a part of a planar pattern of a memory cell of a conventional EEPROM.

FIG. 13 is a cross-sectional view taken along line 13-13 in FIG. 12.

FIG. 14 is a sectional view taken along line 14-14 in FIG. 12.

15 is a diagram showing memory cells of a conventional EEPROM in the order of manufacturing steps, and is a first cross-sectional view corresponding to the cross section shown in FIG. 13. FIG.

16 is a diagram showing memory cells of a conventional EEPROM in the order of manufacturing steps, and is a second cross-sectional view corresponding to the cross-section shown in FIG. 13. FIG.

17 is a diagram showing memory cells of a conventional EEPROM in the order of manufacturing steps, and is a third cross-sectional view corresponding to the cross-section shown in FIG. 13. FIG.

18 is a fourth cross-sectional view corresponding to the cross-section shown in FIG. 13, which is a diagram showing memory cells of a conventional EEPROM in the order of manufacturing steps; FIG.

19 is a diagram showing a memory cell of a conventional EEPROM in the order of manufacturing steps, and is a fifth cross-sectional view corresponding to the cross-section shown in FIG. 13. FIG.

20 is a diagram showing memory cells of a conventional EEPROM in the order of manufacturing steps, and is a first cross-sectional view corresponding to the cross section shown in FIG. 14. FIG.

21 is a diagram showing memory cells of a conventional EEPROM in the order of manufacturing steps, and is a second cross-sectional view corresponding to the cross section shown in FIG. 14. FIG.

22 is a diagram showing memory cells of a conventional EEPROM in the order of manufacturing steps, and is a third cross-sectional view corresponding to the cross section shown in FIG. 14. FIG.

[Explanation of symbols]

100...Silicon substrate, 101...Element region, 102...Element isolation region, 104A...Floating gate, 106A...Selection gate, 106B...Reading gate, 108A...Control gate
110... interlayer insulating film, 112... aluminum layer, 1
50... Wiring layer, 200... Photoresist, 202... Mask, 203... Light blocking section, 204... Ultraviolet rays, 208... Resist pattern.

Claims (4)

[Claims] 1. A semiconductor comprising: a semiconductor substrate having an element isolation region and an element region on a main surface; an insulating film formed on the substrate; and a wiring layer formed on one surface of the insulating film. In the device, one surface of the insulating film has a step region that is inclined with respect to the main surface of the substrate, and the wiring layer formed over the step region is formed so that the wiring layer is formed on a side surface of the step region. A semiconductor device characterized in that a side surface that is substantially parallel to the surface of the semiconductor device is located outside the step region and in a region where the one surface and the main surface are substantially parallel to each other. 2. A second wiring layer different from the wiring layer is present between the insulating film and the substrate near the step region, and a layer of the wiring layer is provided above the second wiring layer. 2. The semiconductor device according to claim 1, further comprising a side surface that is substantially parallel to the step region. 3. A boundary between the element isolation region and the element region on the main surface of the substrate is present under the insulating film near the step region, and a step of the wiring layer is present above the element region. 3. The semiconductor device according to claim 1, further comprising a side surface that is substantially parallel to the region. 4. (a) forming an element isolation region on the main surface of a semiconductor substrate to isolate element regions; (b)
) forming a first wiring layer on the substrate using photolithography; (c) forming an insulating film over the entire surface; (d)
forming a second wiring layer on one surface of the insulating film using a photolithography method; One surface of the insulating film near the boundary and near the first wiring layer has a step region that is inclined with respect to the main surface of the substrate, and a second wiring layer is formed on the step region. In this case, in the step (d), a side surface of the second wiring layer that is substantially parallel to the step region is removed from the step region, and the one surface and the main surface are substantially parallel to each other. A method of manufacturing a semiconductor device, characterized in that the second wiring layer is formed using a mask with a pattern drawn in an area equal to .