JPH04225609A - Mute circuit - Google Patents

Mute circuit

Info

Publication number
JPH04225609A
JPH04225609A JP40811290A JP40811290A JPH04225609A JP H04225609 A JPH04225609 A JP H04225609A JP 40811290 A JP40811290 A JP 40811290A JP 40811290 A JP40811290 A JP 40811290A JP H04225609 A JPH04225609 A JP H04225609A
Authority
JP
Japan
Prior art keywords
resistor
operational amplifier
input terminal
output
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP40811290A
Other languages
Japanese (ja)
Other versions
JP2568755B2 (en
Inventor
Chiyo Fujihira
藤平 千代
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2408112A priority Critical patent/JP2568755B2/en
Publication of JPH04225609A publication Critical patent/JPH04225609A/en
Application granted granted Critical
Publication of JP2568755B2 publication Critical patent/JP2568755B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To offer a means to prevent an input signal from leaking to output because of the internal resistance of a reference voltage source even if muting is given. CONSTITUTION:An input terminal 13 is connected to the reference voltage source 10 through a resistor 1, a middle point A, and the resistor 2, and the input of a voltage follower 7 is connected usually to the input terminal 13 and to the middle point A at the time of the muting by a switch 12. An operational amplifier 8 connects the output of the voltage follower circuit 7 to its forward input terminal, and the resistor R3 from an inverted input terminal to its output terminal, and the resistor R4 to the output terminal of a second operational amplifier 9 respectively, and the second operational amplifier 9 connects its output terminal to an inverted input terminal resistor R5, and this point to the reference voltage source 11 through the resistor R6 respectively, and the forward input terminal of the operational amplifier 9 is connected to the point A, and this mute circuit is constituted so that the relation of R3:R4=R5:R6 is satisfied.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はミュート回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mute circuit.

【0002】0002

【従来の技術】以下、従来のミュート回路の構成と動作
を図2を参照しながら説明する。信号ミュート回路はミ
ュート指令が外部から与えられると、それによってスイ
ッチ29を動作させ、それまで信号入力端子30につな
がっていたボルテイジフォロワ25の入力をスイッチ2
9で基準電源圧27に切り換えて、入力信号を出力端子
31に出さないようにしていた。また、この基準電圧源
27はミュート回路自身のバイアス電圧を与える役目も
兼ねているため、外部からの信号に抵抗21、22を介
してバイアス電圧を与えている。
2. Description of the Related Art The structure and operation of a conventional mute circuit will be explained below with reference to FIG. When the signal mute circuit receives a mute command from the outside, it operates the switch 29 and switches the input of the voltage follower 25, which had been connected to the signal input terminal 30, to the switch 2.
9, the reference power supply voltage is switched to 27 to prevent input signals from being output to the output terminal 31. Furthermore, since this reference voltage source 27 also serves to provide a bias voltage for the mute circuit itself, the bias voltage is applied to external signals via the resistors 21 and 22.

【0003】0003

【発明が解決しようとする課題】しかしながら上記の従
来の構成では、入力バイアス用の抵抗21と基準電圧源
27の間には、必ず抵抗22が存在する。この抵抗22
とは、たとえば、基準電圧源27の出力インピーダンス
であったり、集積回路内の配線抵抗であったりする。そ
して、この入力バイアス用の抵抗21と基準電圧源27
につながる抵抗22の接続点の電位は、ミュートON時
にスイッチ29によって選択され、ボルテイジフォロワ
25を介して、次段の出力用オペアンプ26へ伝達され
るが、この接続点には、入力端子30からはいってくる
信号のレベルをVINとし、抵抗21、22の抵抗値を
それぞれ、R21、R22とすると VIN*R22/(R21+R22) という大きさの信号が乗ることになる。そして、その信
号は、ミュートON時、ボルテイジフォロワ25を経て
反転端子が抵抗24を介して基準電圧源28に接続され
、さらに出力端子との間に抵抗27を接続した出力段オ
ペアンプ26で、適当な大きさに増幅されて出力端子3
1に出てくる。このように、上記従来の構成ではミュー
トをかけたのにもかかわらず、信号出力端子に漏れると
いう問題点があった。
However, in the conventional configuration described above, the resistor 22 is always present between the input bias resistor 21 and the reference voltage source 27. This resistance 22
This may be, for example, the output impedance of the reference voltage source 27 or the wiring resistance within the integrated circuit. This input bias resistor 21 and reference voltage source 27
The potential at the connection point of the resistor 22 connected to Assuming that the level of the signal coming in is VIN, and the resistance values of the resistors 21 and 22 are R21 and R22, respectively, a signal of the magnitude VIN*R22/(R21+R22) will be carried. When the mute is turned on, the signal passes through the voltage follower 25, the inverted terminal is connected to the reference voltage source 28 via the resistor 24, and the output stage operational amplifier 26 has a resistor 27 connected between it and the output terminal. It is amplified to an appropriate size and sent to output terminal 3.
It appears in 1. As described above, in the conventional configuration described above, there is a problem in that the signal leaks to the signal output terminal even though muting is applied.

【0004】本発明は上記従来の問題点を解決するミュ
ート回路を提供するのを目的とする。
An object of the present invention is to provide a mute circuit that solves the above-mentioned conventional problems.

【0005】[0005]

【課題を解決するための手段】この目的を達成するため
に本発明のミュート回路は、入力端子に第1の抵抗の一
方が接続され、同第1の抵抗の他方は第1の基準電圧源
に第2の抵抗を介して接続され、前記第1の抵抗と第2
の抵抗の接続点と入力端子のどちらか一方を選択するス
イッチの出力は、1つまたは複数個のボルテイジフォロ
ワによって第1のオペアンプの正転入力端子に結合され
、同第1のオペアンプの出力には出力端子がつながると
ともに、第1のオペアンプの出力と反転入力端子間には
第3の抵抗があり、同反転入力端子と第2のオペアンプ
の出力間に第4の抵抗があり、前記第2のオペアンプの
正転入力端子には、前記第1の抵抗と第2の抵抗の接続
点を接続し、同第2のオペアンプの反転入力端子と出力
間に第5の抵抗を接続し、さらに、同反転入力端子に第
6の抵抗を介して、第2の基準電圧源を接続し、前記第
3、第4、第5、第6の抵抗の抵抗値をR3、R4、R
5、R6としたとき、R3:R4=R6:R5の関係を
満たす構成を有している。
[Means for Solving the Problem] In order to achieve this object, the mute circuit of the present invention has one of the first resistors connected to the input terminal, and the other of the first resistors is connected to the first reference voltage source. is connected via a second resistor to the first resistor and the second resistor.
The output of the switch that selects either the connection point of the resistor or the input terminal is coupled to the non-inverting input terminal of the first operational amplifier by one or more voltage followers, and the output of the first operational amplifier is coupled to the non-inverting input terminal of the first operational amplifier. The output terminal is connected to the first operational amplifier, and there is a third resistor between the output of the first operational amplifier and the inverting input terminal, and a fourth resistor is located between the inverting input terminal and the output of the second operational amplifier. A connection point between the first resistor and the second resistor is connected to the non-inverting input terminal of the second operational amplifier, a fifth resistor is connected between the inverting input terminal and the output of the second operational amplifier, and , a second reference voltage source is connected to the inverting input terminal via a sixth resistor, and the resistance values of the third, fourth, fifth, and sixth resistors are set as R3, R4, and R4.
5 and R6, it has a configuration that satisfies the relationship R3:R4=R6:R5.

【0006】[0006]

【作用】この構成によって、ミュートオン時に、第1の
抵抗と第2の抵抗によって抵抗分割された信号が、ボル
テイジフォロワを通って第1のオペアンプに伝わっても
第1のオペアンプ、第2のオペアンプによって、伝達さ
れた信号をキャンセルし、出力端子に出てこないように
設定することができる。
[Operation] With this configuration, when mute is turned on, even if the signal resistance-divided by the first resistor and the second resistor is transmitted to the first operational amplifier through the voltage follower, the first operational amplifier and the second operational amplifier The operational amplifier can cancel the transmitted signal and set it so that it does not appear at the output terminal.

【0007】[0007]

【実施例】以下本発明の一実施例のミュート回路につい
て、図面を参照しながらその構成と動作を説明する。図
1に示すようにスイッチには接続点Bに接続されており
、入力端子13より入力された信号は基準電圧源10か
ら抵抗2、抵抗1を通ってバイアス電圧を与えられてボ
ルテイジフォロワ7の正転端子に入力される。外部から
ミュート信号が与えられた場合、スイッチ12は接続点
Aとボルテイジフォロワ7の入力を導通させて、接続点
Aの電位を次段のオペアンプ8に伝えるが、発明が解決
しようとする課題の項で述べたように、接続点Aには入
力端子13より入力され、抵抗1、抵抗2によって抵抗
分割された信号が乗っている。この接続点Aの電位をV
Aとする。オペアンプ8は抵抗3、抵抗4、によってゲ
インがきまる非反転増幅器であり、オペアンプ8の出力
をV0、抵抗3、抵抗4の抵抗値をR3、R4とし、オ
ペアンプ9の出力をVCとすると、次の式が成り立つ。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a mute circuit according to an embodiment of the present invention will be explained below with reference to the drawings. As shown in FIG. 1, the switch is connected to a connection point B, and a signal input from an input terminal 13 is applied with a bias voltage from a reference voltage source 10 through a resistor 2 and a resistor 1, and is applied to a voltage follower 7. is input to the normal rotation terminal of When a mute signal is applied from the outside, the switch 12 conducts the connection point A and the input of the voltage follower 7, and transmits the potential of the connection point A to the next stage operational amplifier 8. However, this problem is solved by the invention. As described in the above section, a signal is input to the connection point A from the input terminal 13 and is resistance-divided by the resistors 1 and 2. The potential of this connection point A is V
Let it be A. The operational amplifier 8 is a non-inverting amplifier whose gain is determined by the resistors 3 and 4. If the output of the operational amplifier 8 is V0, the resistance values of the resistors 3 and 4 are R3 and R4, and the output of the operational amplifier 9 is VC, then The formula holds true.

【0008】   V0=(1+R3/R4)〔VA−VC×R3/(
R4+R3)〕(1)ただし、オペアンプのゲインは無
限大とする。(1)式からわかるように、VA=VC×
R3/(R4+R3)の場合、出力は、信号成分が0と
なる。この式を変形すると、 VC=VA(1+R4/R3)(2) 一方、オペアンプ9は、入力は接続点Aにつながり、抵
抗5、抵抗6によってゲインがきまり、基準電圧源11
によって、DCバイアスされた非反転増幅器である。よ
って、抵抗5、抵抗6の抵抗値をそれぞれ、R5、R6
とすると、 VC=VA(1+R5/R6)(3) となり、また、R3:R4=R6:R5であるので、(
2)式と、(3)式は、等しい。このことは、ミュート
をかけたにもかかわらず、入力段より、漏れてきた信号
を、出力段のアンプでキャンセルして、完全に無信号に
できることをあらわしている。
V0=(1+R3/R4) [VA-VC×R3/(
R4+R3)] (1) However, the gain of the operational amplifier is assumed to be infinite. As can be seen from equation (1), VA=VC×
In the case of R3/(R4+R3), the output has a signal component of 0. Transforming this equation, VC=VA(1+R4/R3)(2) On the other hand, the input of the operational amplifier 9 is connected to the connection point A, the gain is determined by the resistors 5 and 6, and the reference voltage source 11
is a DC biased non-inverting amplifier. Therefore, the resistance values of resistor 5 and resistor 6 are R5 and R6, respectively.
Then, VC=VA(1+R5/R6)(3), and since R3:R4=R6:R5, (
Equation 2) and Equation (3) are equivalent. This means that even though muting is applied, the signal leaking from the input stage can be canceled by the output stage amplifier, making it completely silent.

【0009】つぎに、ミュートオフ時には、スイッチ1
2により、入力端子とボルテイジフォロワを導通させて
基準電圧源10、抵抗2、抵抗1によってバイアス電圧
を与えられた入力信号が、ボルテイジフォロワを経てオ
ペアンプ8へ伝えられ、抵抗3、抵抗4によって、増幅
され、出力端子から信号は出力される。この場合の出力
電圧V0は、入力信号電圧をVINとすると    V
0=(1+R3/R4)〔VIN−VC×R3/(R4
+R3)〕(4)と表される。(4)式に(3)式を代
入するとV0=(1+R3/R4)(VIN−VA)(
5)となり、信号レベルは従来例より接続点Aの電圧に
オペアンプ8のゲインをかけた分だけ小さくなっている
が、通常、抵抗1の抵抗値は、抵抗2の抵抗値に比べて
非常に大きいため、VIN》VAとなり、ミュートオフ
時に出力電圧が減少するのはごくわずかである。
Next, when muting off, switch 1 is pressed.
2, the input terminal and the voltage follower are electrically connected and the input signal to which a bias voltage is applied by the reference voltage source 10, the resistor 2, and the resistor 1 is transmitted to the operational amplifier 8 via the voltage follower, and The signal is amplified and output from the output terminal. In this case, the output voltage V0 is VIN, where the input signal voltage is VIN.
0=(1+R3/R4) [VIN-VC×R3/(R4
+R3)] (4). Substituting equation (3) into equation (4), V0=(1+R3/R4)(VIN-VA)(
5), and the signal level is smaller than the conventional example by multiplying the voltage at connection point A by the gain of operational amplifier 8, but normally the resistance value of resistor 1 is much smaller than the resistance value of resistor 2. Since it is large, VIN>VA, and the output voltage decreases only slightly when mute is turned off.

【0010】なおボルテイジフォロワ7として1を用い
て例示したが、必要によって複数個用いてもよいもので
ある。
Although one voltage follower 7 is used in the example, a plurality of voltage followers 7 may be used as necessary.

【0011】[0011]

【発明の効果】本発明は出力段オペアンプのバイアス回
路として、入力段で付加される信号を増幅したオペアン
プを使うことにより、ミュートをかけたにもかかわらず
入力段でもれた信号を、出力段でキャンセルするという
効果を得られる優れたミュート回路を実現できるもので
ある。
Effects of the Invention: By using an operational amplifier that amplifies the signal added at the input stage as a bias circuit for the output stage operational amplifier, the signal leaked at the input stage even when muted is removed from the output stage. This makes it possible to realize an excellent mute circuit that provides the effect of canceling the signal.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例のミュート回路の回路図[Fig. 1] Circuit diagram of a mute circuit according to an embodiment of the present invention.

【図
2】従来例のミュート回路の回路図
[Figure 2] Circuit diagram of conventional mute circuit

【符号の説明】[Explanation of symbols]

1,6  抵抗 7  ボルテイジフォロワ 8,9  オペアンプ 10,11  基準電圧源 12  スイッチ 13  入力端子 14  出力端子 1,6 Resistance 7 Voltage follower 8,9 Operational amplifier 10, 11 Reference voltage source 12 Switch 13 Input terminal 14 Output terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】入力端子に第1の抵抗の一方が接続され、
同第1の抵抗の他方は第1の基準電圧源に第2の抵抗を
介して接続され、前記第1の抵抗と第2の抵抗の接続点
と入力端子とのどちらか一方を選択するスイッチの出力
は、1つまたは複数個のボルテイジフォロワによって、
第1のオペアンプの正転入力端子に結合され、同第1の
オペアンプの出力には出力端子がつながるとともに、第
1のオペアンプの出力と反転入力端子間には第3の抵抗
があり、同反転入力端子と第2のオペンプの出力間に第
4の抵抗があり、前記第2のオペアンプの正転入力端子
には、前記第1の抵抗と第2の抵抗の接続点を接続し、
同第2のオペアンプの反転入力端子と出力間に第5の抵
抗を接続し、さらに、同反転入力端子に第6の抵抗を介
して、第2の基準電圧源を接続し、前記第3、第4、第
5、第6の抵抗の抵抗値をR3、R4、R5、R6とし
たとき、R3:R4=R6:R5の関係を満たすように
構成したミュート回路。
Claim 1: One of the first resistors is connected to the input terminal,
The other of the first resistors is connected to a first reference voltage source via a second resistor, and a switch selects either the connection point between the first resistor and the second resistor or the input terminal. The output of is controlled by one or more voltage followers,
The output terminal is connected to the non-inverting input terminal of the first operational amplifier, and the output terminal is connected to the output of the first operational amplifier. a fourth resistor is provided between the input terminal and the output of the second operational amplifier, and a connection point between the first resistor and the second resistor is connected to the normal input terminal of the second operational amplifier;
A fifth resistor is connected between the inverting input terminal and the output of the second operational amplifier, and a second reference voltage source is connected to the inverting input terminal via a sixth resistor. A mute circuit configured to satisfy the relationship R3:R4=R6:R5, where the resistance values of the fourth, fifth, and sixth resistors are R3, R4, R5, and R6.
JP2408112A 1990-12-27 1990-12-27 Mute circuit Expired - Lifetime JP2568755B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2408112A JP2568755B2 (en) 1990-12-27 1990-12-27 Mute circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2408112A JP2568755B2 (en) 1990-12-27 1990-12-27 Mute circuit

Publications (2)

Publication Number Publication Date
JPH04225609A true JPH04225609A (en) 1992-08-14
JP2568755B2 JP2568755B2 (en) 1997-01-08

Family

ID=18517607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2408112A Expired - Lifetime JP2568755B2 (en) 1990-12-27 1990-12-27 Mute circuit

Country Status (1)

Country Link
JP (1) JP2568755B2 (en)

Also Published As

Publication number Publication date
JP2568755B2 (en) 1997-01-08

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