JPH04225443A - Bus access control system - Google Patents

Abstract

PURPOSE:To prevent the excessive waiting time to a high speed ROM and the short waiting time to a low speed ROM respectively by applying the access drive to the ROM via a bus and in the waiting time proper to the ROM. CONSTITUTION:A waiting time counter 3 measures and decides a waiting time (access time) based on the specific pattern data 41 stored in a ROM 4. A drive control circuit 2 which transmits an access drive signal to a CPU 1 writes the decided waiting time into a waiting time setting part 21 in an initialization state. Then the CPU 1 performs the access drive of the ROM 4 at the time written into the part 21.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention provides a system in which a central processing unit performs RO
The present invention relates to a bus access control system for a processor system that processes access to M (read-only memory), particularly for ROMs with different access times.

0002

2. Description of the Related Art Conventionally, this type of bus access control system has a drive control circuit that drives a central processing unit based on the access time of a mounted ROM.

That is, the central processing unit always accesses the ROM via the bus with a fixed waiting time.

[0004] Therefore, for mounting ROMs with different access times, a drive control circuit has been provided that uses the access time as a waiting time.

[0005]

[Problems to be Solved by the Invention] In the conventional bus access control method described above, the bus drive cycle of the central processing unit during ROM access is kept constant by the drive control circuit.
Even when changing to a ROM with a different access time, the drive cycle does not change, resulting in the phenomenon that, for example, when changing to a high-speed ROM, unnecessary waiting time is required, and when changing to a low-speed ROM, there is not enough waiting time. However, in order to change the drive cycle, it is necessary to change the drive control circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus access control system that eliminates the above-mentioned drawbacks by providing a wait time setting section for writing a wait time into a drive control circuit.

[0007]

A bus access control method according to the present invention provides a bus access control method for a processor system in which a central processing unit processes access to a ROM (read-only memory) for a certain amount of time via an address bus and a data bus. The control method further includes a waiting time setting unit that sets the waiting time that is a cycle for repeating the access process to the bus, and a specific pattern data that is stored in the ROM in advance, and a specific pattern data that is stored from the ROM at the time of initial setting. A drive that extracts pattern data, measures the time for the data to be finalized, writes and sets the determined time as a waiting time in the waiting time setting section, and thereafter drives the central processing unit according to the set waiting time. It has a control circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
2 is a flowchart showing an example of the main operation procedure according to FIG. 1. FIG.

As shown in FIG. 1, a central processing unit 1 is connected to a drive control circuit 2, a waiting time counter 3, and a ROM 4 via an address bus 5 and a data bus 6.

The drive control circuit 2 has a waiting time setting section 21, and a measured value measured by the waiting time counter 3 is written into this waiting time setting section 21 as a waiting time.

The waiting time counter 3 reads specific pattern data 41 stored in advance in the ROM 4, measures the time from start to finalization, and the central processing unit 1 extracts this and writes it into the waiting time setting section 21.

Next, the operating procedure will be explained with reference to FIG. 2 and FIG. 1.

First, at the time of initial operation, the central processing unit 1 instructs the initial setting (101), returns the waiting time count value of the waiting time counter 3 to zero (102), and also sets the waiting time setting section of the drive control circuit 2. 21 is set to a maximum waiting time and activated by the drive signal 7 (103).

[0014] With this activation, the central processing unit 1 loads the ROM 4
extracts the initial setting execution program and calls the area of specific pattern data 41 at a specific address (104);
When the waiting time counter 3 starts counting, the ROM 4
Transfer (105) of the specific pattern data 41 is started.

The waiting time counter 3 has specific pattern data 4.
Measure until 1 matches the correct value of the specific pattern (106
) continue.

The central processing unit 1 stores specific pattern data 41.
After reading, the counted value after the measurement is completed is read from the waiting time counter 3 (107), and written as a waiting time in the waiting time setting section 21 of the drive control circuit 2, and set (108).

Thereafter, the drive control circuit 2 uses the waiting time setting section 21.
The drive signal 7 of the central processing unit 1 is periodically transmitted according to the waiting time of the ROM 4 written in the ROM 4 .

Therefore, the central processing unit 1 can access the ROM 4 due to the waiting time, ie, the access time, of the ROM 4 connected to the address bus 5 and the data bus 6.

In this embodiment, a waiting time counter is used to
Although the waiting time of the ROM was measured using specific pattern data, it is also possible to calculate the waiting time in advance at the time of design, set the waiting time in the ROM instead of the specific pattern, and read it as the access time directly by the central processing unit.

[0020]

Effects of the Invention As explained above, the present invention allows the waiting time (access time) of the ROM (measured by the waiting time counter from the specific pattern data of the ROM) to be transmitted to the central processing unit by an access drive signal. The transmitting drive control circuit writes in the waiting time setting part at the time of initial setting, and thereafter accesses and drives the ROM using the time of this waiting time setting part, so that the ROM can be read from the ROM via the bus using the waiting time of the ROM connected to the bus. This has the effect of preventing excess waiting time for the high-speed ROM and shortage of waiting time for the low-speed ROM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a bus access control method of the present invention.

FIG. 2 is a flowchart showing an example of the main operation procedure according to FIG. 1;

[Explanation of symbols]

1 Central processing unit 2 Drive control circuit 3 Waiting time counter 4 ROM 5, 6 bus 7 Drive signal 21 Waiting time setting section 41 Specific pattern data

Claims (1)

[Claims] 1. In a bus access control method for a processor system in which a central processing unit processes access to a ROM (read-only memory) for a fixed waiting time via an address bus and a data bus, a period in which the access process to the bus is repeated. The apparatus further includes a waiting time setting section for setting the waiting time, which stores specific pattern data in the ROM in advance, and extracts the stored specific pattern data from the ROM at the time of initial setting and measures the time for the data to be finalized. , a bus access control system comprising a drive control circuit that newly writes and sets the determined time as a waiting time in the waiting time setting section and thereafter drives the central processing unit according to the set waiting time. .