JPH04225273A - Semiconductor device - Google Patents

Abstract

PURPOSE:To offer a semiconductor device whose fan-out is higher than that of an I<2>L and which can coexist with a linear IC. CONSTITUTION:A lateral pnp-type transistor 24 which is composed of a P-type semiconductor 3 and n<+> type semiconductors 4, 5 is formed on the upper part of an epitaxial growth layer 2. A P-type semiconductor 6 is formed to be a rectangle on the right side from a position near the n<+> type semiconductor 4. Nearly square P-type semiconductors 7a to 7j are formed respectively in positions near the upper part and the lower part of the P-type semiconductor 6. A multiconnector pnp-type transistor which uses the n<+> type semiconductor 4 as a base, the P-type semiconductor 6 as an emitter and the P-type semiconductors 7a to 7j as a collector is constituted. When the individual transistors are operated normally, it is possible to obtain a semiconductor device whose fan-out is higher than that of an I<2>L.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a logic semiconductor device that coexists with a normal linear IC.

0002

[Prior Art] Conventionally, in bipolar ICs, I2L (In
integrated injection logic)
A semiconductor device called I2L (hereinafter abbreviated as I2L) is generally well known. I2L will be explained below.

FIG. 6 is a two-sided view showing the structure of a conventional I2L. FIG. 6(A) shows a plan view, and FIG. 6(B) shows a cross-sectional view. In FIG. 6(B), 45 is an oxide film, and 39, 40, 41, 42, 43, and 44 are terminals made of aluminum. In FIG. 6A, these terminals are omitted, and the oxide film 45 is shown transparently. In each figure, the same components are denoted by the same reference numerals, and a description of FIG. 6(A) will be omitted.

In FIG. 6(B), a P-type semiconductor substrate 26
A buried layer 16 made of an n+ type impurity semiconductor is formed in the upper center. Furthermore, an epitaxial growth layer (hereinafter abbreviated as epitaxial layer) 27 made of a low concentration n-type impurity semiconductor is formed in the upper center of the buried layer 16.

Outside the epitaxial layer 27, a high concentration n+ type impurity region (represented by deepn+ in the figure, hereinafter referred to as deepn+) is formed on the outer edge of the buried layer 16.
It is written as ) 32 and deepn + the first formed on the top
An n+ type impurity region 33 is provided. Also, d
An epitaxial layer 30 formed on the top of the semiconductor substrate 1 is provided outside the eepn+ 32, and a separation layer 31 made of a P+ type impurity semiconductor formed on the top of the outer edge of the semiconductor substrate 26 is provided further outside the epitaxial layer 30. has been done.

As shown in the figure, the epitaxial layer 27 has a first P-type impurity region 37 made of a low concentration P-type impurity semiconductor, and a second P-type impurity region 37 made of a P-type impurity semiconductor.
A type impurity region 38 is formed. Second, third, and fourth n+ type impurity regions 34, 35, and 36 are formed in the first P type impurity region 37, respectively.

An oxide film 45 is also formed on the upper surface of the I2 L 46 formed as described above. Openings are formed in the oxide film 45 above each of the N + -type impurity regions 33 , 34 , 35 , 36 and the first and second P-type impurity regions 43 , 44 . Terminals 39, 40, 41, 42, 43, and 44 made of aluminum are arranged in each opening.

As is well known, in the I2L having the above configuration,
A lateral pnp transistor 28 and a multi-collector npn transistor 29 shown by broken lines in FIG. 6(B)
is configured.

FIG. 7 is a circuit diagram showing an equivalent circuit of the conventional I2L described above. In the figure, the same components as those in FIG. 6(B) are designated by the same reference numerals, and the explanation thereof will be omitted. In the figure, QP is a lateral pnp transistor, QN
indicates a multi-collector npn type transistor. As shown in the figure, the terminal 44 is connected to the power supply voltage VCC, and the terminal 39 is connected to the ground, and the PN junction consisting of the first P-type impurity region 37 and the epitaxial layer 2 is biased in order to perform the reverse operation of a normal transistor. and input terminal 43,
An inverter having terminals 40, 41, and 42 as output terminals is configured.

Next, FIG. 8 is a circuit diagram showing an example of a conventional circuit that applies a bias to I2L. In the figure, lateral pnp transistors QP1, QP2, QP3...QPN
are connected to each emitter, and each emitter is connected to a resistor R2.
It is connected to power supply voltage VCC via. FIG. 9 is a diagram showing a conventional I2L circuit diagram symbol.

According to the conventional I2L described above, as shown in FIG. 6(B), the collector region of the lateral pnp transistor 28 and the base region of the multi-collector npn transistor 29 are common. Furthermore, since the base region of the lateral pnp transistor 28 and the emitter region of the multi-collector npn transistor 29 are common, the structure is simple and does not include any resistance, and the separation of each transistor and some wiring can be omitted. This has the advantage of increasing the degree of integration compared to normal bipolar integrated circuits.

0012

[Problem to be solved by the invention] However, I2
As mentioned above, L is a normal TTL (Train transistor) in order to use an npn type transistor as a reverse operation type transistor.
Transister Logic)
There was a problem that the current amplification factor was lower than that of the conventional method. For this reason, the fan-out number could normally only be 3 to 4.

The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a semiconductor device that has a higher fan-out than the conventional I2L and can coexist with a linear IC.

[0014]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an epitaxial growth layer having the same conductivity as the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate and having a low concentration. a first impurity region of a type, a second impurity region of a conductivity type opposite to that of the semiconductor substrate, and the semiconductor formed in the first impurity region at substantially the same depth as the second impurity region. In a semiconductor device having a transistor structure including a substrate and a third impurity region of an opposite conductivity type, the semiconductor substrate is provided with a semiconductor substrate having substantially the same depth as the first impurity region at a position near the second impurity region. A fourth impurity region having the same conductivity type as the semiconductor substrate is provided, and at least an impurity region having substantially the same depth as the first impurity region and having the same conductivity type as the semiconductor substrate is provided in the vicinity of the fourth impurity region. One is provided.

[0015]

[Operation] According to the semiconductor device of the present invention having the above configuration,
A transistor structure is configured, which includes the second impurity region having a conductivity type opposite to that of the semiconductor substrate forming the transistor structure, the fourth impurity region having the same conductivity type as the semiconductor substrate, and the impurity region.

[0016]

[Example] Next, an example of the present invention will be described.

FIG. 1 is a two-sided view showing the structure of a semiconductor device according to an embodiment of the present invention. FIG. 1(A) shows a plan view,
FIG. 1(B) shows a cross-sectional view at the position indicated by the broken line BB in FIG. 1(A). Further, FIG. 2 is a vertical cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, and FIG.
A) A longitudinal cross-sectional view at the position indicated by the medium broken line II-II. In each figure, the same components are designated by the same reference numerals. Each figure will be explained below.

In FIGS. 1B and 2, a buried layer 16 made of an n+ type impurity semiconductor is formed in the upper center of the P type semiconductor substrate 1. Furthermore, an epitaxial layer 2 is formed above the buried layer 16. On the outside of the epitaxial layer 2, there is a P+ layer formed on the upper outer edge of the semiconductor substrate 1.
A separation layer 14 made of a type impurity semiconductor is provided. As shown in the figure, the epitaxial layer 2 includes a first impurity region 3, a fourth impurity region 6, impurity regions 7a and 7b, each made of a P-type impurity semiconductor and having the same depth.
7c, 7d, 7e, 7f, 7g, 7h, 7i, 7j and second impurity regions 4 made of an n+ type impurity semiconductor are formed. A third impurity region 5 is formed in the first impurity region 3 and is made of an n + -type impurity semiconductor and has the same depth as the second impurity region 4 .

As shown in FIG. 1A, the epitaxial layer 2 is formed into a rectangle whose longitudinal direction is in the lateral direction in the figure. The first impurity region 3 is formed in a rectangular shape having a longitudinal direction in the direction of the short side of the epitaxial layer 2 near the left short side in the figure of the epitaxial layer 2 . The third impurity region 5 is formed in a rectangular shape having a longitudinal direction in the longitudinal direction of the first impurity region 3 at a position near the left long side of the first impurity region 3 in the figure.

The second impurity region 4 is located to the right of the first impurity region 3 in the figure, near the center of the epitaxial layer 2.
has a longitudinal direction in the longitudinal direction of the first impurity region 3;
The first impurity region 3 has substantially the same length as the first impurity region 3, and is formed into a rectangular shape substantially parallel to the first impurity region 3.

The first, second, and third impurity regions 3, 4, and 5 formed as described above constitute a lateral npn type transistor 24 (indicated by a broken line in FIG. 1B). This configuration is the same as that of a normal linear IC.

As shown in FIG. 1A, the fourth impurity region 6 has a rectangular shape with its longitudinal direction extending in the longitudinal direction of the epitaxial layer 2.
It is formed at approximately the center of the epitaxial layer 2 , on the right side of the vicinity of the second impurity region 4 , and approximately at the center of the epitaxial layer 2 in the short side direction. Impurity regions 7a, 7b, 7c, 7d, and 7e each have a substantially square shape, and are formed at equal intervals near the bottom of fourth impurity region 6 in the figure. Impurity regions 7f, 7g,
7h, 7i, and 7j are also made of similar approximately squares, and the fourth
The impurity regions 6 are formed at equal intervals near the upper side of the impurity region 6 .

The second and fourth impurity regions 4, 6 and impurity regions 7a, 7b, 7c, 7d, formed as described above
7e, 7f, 7g, 7h, 7i, and 7j, the multi-connector pnp type transistor 25 (Fig. 1 (B) and Fig. 2
Indicated by a broken line inside. ) is configured. The second impurity region 4, which becomes the base region of the multi-collector pnp transistor 25, is similar to the lateral npn transistor 2 described above.
It is common to the collector area of No. 4.

An oxide film 15 is formed on the upper surface of each impurity region, epitaxial layer 2, and isolation layer 14 of the above structure, and an opening is provided above each impurity region. Each opening has terminals 8, 9a, 9 made of aluminum.
b, 9c, 9d, 9e, 9f, 10, 11, and 12 are formed, respectively, and are electrically connected to each impurity region. Reference numeral 18 in each figure indicates a semiconductor device constituted by each of the above-mentioned transistors.

FIG. 3 is a circuit diagram showing an equivalent circuit of a semiconductor device according to an embodiment of the present invention having the above configuration. In the figure, the same components as those in FIG. 1(B) and FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted.

Reference numeral 23 in the figure is an equivalent circuit of a semiconductor device having the same configuration as the semiconductor device 18. Q1 and Q2 are each n
Each of the pn type transistors QM1 and QM2 represents a multi-collector pnp type transistor. Terminals 17, 19, 22
Each shows the collector terminal, base terminal, and emitter terminal of the transistor QM2. Terminal 17 is a common terminal with the collector terminal of transistor Q2, and terminal 20,
21 indicate the base terminal and emitter terminal of the transistor Q2, respectively.

In FIG. 3, the terminals 12 and 21 indicated by IG1 and IG2 are connected to the ground, the terminals 8 and 22 are connected to the power supply voltage VCC, and the terminals 11 and 20 indicated by IB1 and IB2 are connected to a predetermined bias. By giving
The base current due to holes injected from the emitters of transistors QM1 and QM2 flows through transistors Q1 and Q2.
is absorbed by the collector current of

By connecting the terminal 9a and the terminal 19, the semiconductor device 18 and the semiconductor device 23 are connected in cascade, and when the first stage transistor QM1 is on, the second stage transistor QM2 is turned off, as indicated by B. terminal 10 is an input terminal,
An inverter having terminal 17 as an output terminal is constructed.

FIG. 4 is a circuit diagram showing an example of a circuit for applying bias to a semiconductor device according to an embodiment of the present invention. In the figure, Q1, Q2, . The circuit shown in the figure will be explained below.

The emitter of the bias npn transistor Q10 is connected to the ground, the collector is connected to the power supply voltage VCC via a resistor R1, and the base is connected to the emitter of the bias npn transistor Q11. Also,
The collector of the bias transistor Q11 is connected to the power supply terminal V
CC, the base is the collector of the bias transistor Q10, and the emitter is each npn transistor Q1, Q
2...Connected to the base of QN.

FIG. 5 is a diagram showing circuit diagram symbols of a semiconductor device according to an embodiment of the present invention. As explained above, according to the semiconductor device of one embodiment of the present invention, both the npn type transistor and the multi-collector pnp type transistor have their base-collector junctions reverse biased to operate as normal transistors, so current amplification is improved compared to I2L. The ratio is easy to obtain, and the fan-out number can be up to 10, which is the same as normal TTL.

[0032]

[Effects of the Invention] As described above, according to the present invention, the linear IC
It has features such as higher current amplification factor and higher fan-out than conventional I2L.

[Brief explanation of the drawing]

FIG. 1 is a two-sided view showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing an equivalent circuit of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a circuit that applies bias to a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a diagram showing circuit diagram symbols of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a two-sided view showing the structure of a conventional I2L.

FIG. 7 is a circuit diagram showing an equivalent circuit of a conventional I2L.

FIG. 8 is a circuit diagram showing an example of a conventional circuit that applies a bias to I2L.

FIG. 9 is a diagram showing circuit diagram symbols of a conventional I2L.

[Explanation of symbols]

3 First impurity region 4 Second impurity region 5 Third impurity region 6 Fourth impurity region 7a-7j Impurity region 18 Semiconductor device 23 Semiconductor device

Claims (1)

[Claims] 1. A first impurity region having the same conductivity type as the semiconductor substrate, and a first impurity region having the same conductivity type as the semiconductor substrate, in a low concentration epitaxial growth layer formed on the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate. and a third impurity region of a conductivity type opposite to that of the semiconductor substrate, which is formed in the first impurity region at substantially the same depth as the second impurity region. In the semiconductor device, a fourth impurity region having substantially the same depth as the first impurity region and the same conductivity type as the semiconductor substrate is provided in the vicinity of the second impurity region, and the fourth impurity region has the same conductivity type as the semiconductor substrate. At least one impurity region having substantially the same depth as the first impurity region and having the same conductivity type as the semiconductor substrate is provided in the vicinity of the impurity region.