JPH04222988A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize the block writing function without increasing the number input/output buses 5 in the dual port RAM and to enable to freely set the bit number to conduct the block writing. CONSTITUTION:The logic circuit (column selection circuit) 1105 of the column decorder outputting the column decoder outputs 105a-105n has first and second logic circuits (column selection means). The first logic circuits 1100a-1100n input the column address selecting signals A0-An and the second logic circuits 1101a-1101n input the signals excluding a specified low-order bit among prescribed column address selecting signals and block writing signal. The column selecting operation in the normal write/read time at every one bit is performed with the first logic circuit and the column selecting operation in the block writing time is performed with the second logic circuit.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to semiconductor memory devices, and in particular to dual-port RAMs (random access memories), which are often used in recent years as memory for image processing in workstations and personal computers. This is related to the improvement of the block write function that can be loaded.

0002

2. Description of the Related Art FIG. 4 is a block diagram of a conventional dual-port RAM. Reference numeral 100 indicates a dual-port RAM chip, 1 indicates a memory array of the RAM which is a first memory array, and 2 indicates its row selection. row decoder, 3
is a column decoder that performs column selection. The row and column decoders 2 and 3 select any one cell in the RAM memory array 1 based on signals inputted from an external address terminal 20 and converted by an address buffer 7, that is, internal address signals 6a and 6b. It has become.

Regarding data writing, data from the external data input/output terminal 22 is transferred to the RAM input/output buffer 4.
is converted into an internal write signal by RAM write bus 5a.
After column selection by , data is written to the selected cell. Regarding data reading, after column selection, the data is outputted to the external data input/output terminal 22 via the RAM input/output buffer 4 by the RAM read bus 5b. Here, various operations such as address selection, writing, and reading are performed using various signals inputted to the external clock terminal 21, that is, an inverted RAS (row address strobe).
, inverted CAS (column address strobe), inverted WB
(Write Per Bit) / Inverted WE (Write Enable)
, Inverted DT (Data Transfer)/Inverted OE (Output Enable), DSF (D Special Flag)
and is converted into a number of internal signals by the internal signal generator 8.

Reference numeral 11 denotes a SAM (serial access memory) memory array which is a second memory cell array having a number of memory cells equal to one row of RAM memory array 1, that is, the number of memory cells in the column direction. For any row of the first memory array 1, data can be transferred bidirectionally between the RAM and the RAM.
Bidirectional transfer from M to RAM is possible. Transfer is instructed by a signal input to external clock terminal 21, similar to writing and reading of RAM memory array 1.

[0005] Here, the writing and reading addresses to the SAM memory array 11 are specified by the serial selector 12, and the start address is the column address 6c given during the data transfer cycle between the RAM and the SAM. . That is, in a transfer cycle, the row address means the row address of the RAM memory array 1 to be transferred, and the column address means the start address of reading and writing of the SAM memory array 11 after the transfer. Note that 9 is a conversion circuit that converts the column address into a SAM write/read head address designation signal after transfer. The address shift is performed by a serial clock signal SC from an external serial clock terminal 30. That is, after converting the signal into a serial clock internal signal by the SC buffer 17, the signal conversion circuit 16
For example, a counter circuit converts the signal and advances the address one by one, and the serial selector 12 instructs the write and read addresses.

Further, 15a is a SAM write bus, and 15b is an SAM write bus.
In the AM read bus, 14 is a SAM input/output buffer, and 32 is an external serial input/output terminal. 31 is an external serial enable terminal, and the serial enable signal (inverted SE) from this terminal 31 is converted into an internal signal by the inverted SE buffer 18, inputted to the SAM input/output buffer 14 and the transfer circuit 10, and sent to the SAM memory array. When writing to or reading from 11, prohibit the SAM input/output buffer 14,
The data transfer circuit 10 between RAM and SAM is prohibited. 19 is a QSF output buffer that converts a special flag signal indicating whether the address position is upper or lower; 33
is an external QSF terminal that outputs the converted signal.

FIG. 5 shows an example of an image processing system using this dual port RAM, in which information necessary for display is written from the CPU 50 to the RAM memory array 1 at any time, and data written from the RAM memory array 1 is sent to the SA.
M memory array 11, and then from SAM memory array 11 to CRTC (CRT controller) 5.
1 and displayed on the display device 52.

With standard memory, one operation is limited to writing or reading, so drawing and drawing cannot be done at the same time, but with dual-port RAM, the first memory is used for writing and the second memory is used for writing. Since these can be operated independently and asynchronously as read memory,
You can draw and draw at the same time.

[0009] Also, in order to simplify the system, memory IC
The tendency to have various functions inside has been particularly strong in recent years, as shown in Figure 7.
(a) shows a block write as an example of such a function. This is 1Mbit dual port RAM
This is a block write function incorporated in the color register 60.
OR DATA) and write 4 bits at a time in one cycle, compared to conventional methods where writing in one cycle was limited to 1 bit.
The time required for drawing can be significantly reduced. In a 1M bit dual-port RAM, 4 bits were written in one cycle, but considering future complex and diverse applications, the number of block write bits will increase to 8 bits as shown in Figure 7(b), or 8 bits as shown in Figure 7(c). ) Needless to say, there will be demands for 16 bits, and even more bits.

FIG. 6 shows an internal circuit for a conventional 4-bit block write, in which 101 is a memory cell of a RAM memory array, 111 is a memory cell of a SAM memory array, 102 is a bit line arranged in a column direction, and 103 is a memory cell of a SAM memory array. 1 is a word line which is a row selection line, and 104 is a sense amplifier. 105 is a column decoder output for selecting columns, and 4a is a RAM input/output buffer having four input/output buses 5c to 5f and configured so that data can be written by selecting four bit line pairs at the same time. , a block write input buffer 1 having a block input bus 1003 shown in FIG.
The configuration includes 010.

In this circuit, in normal 1-bit writing and reading, one of the four RAM input/output buffers 4a is selected, and in block writing, the input/output bus 5 is selected.
All of c to 5f serve as write buses to realize 4-bit simultaneous writing.

0012

[Problems to be Solved by the Invention] Since the block write circuit in the conventional semiconductor memory device is configured as described above, 8 bits and 8 bits as shown in FIGS.
8 to realize 16-bit block write function
It is necessary to prepare 16 pairs of input/output buses.
There are problems in that the chip area becomes large and switching of input/output buses between block writes and normal 1-bit writes becomes complicated.

[0013] This invention was made to solve the above-mentioned problems, and it is possible to realize a block write function without increasing the number of input/output buses, and moreover, it is possible to freely set the number of bits to be block written. The purpose of this invention is to obtain a semiconductor memory device that can be used.

[0014]

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a column selection circuit that selects a column in a memory array of a random access memory (RAM), which selects a single column based on a column address selection signal. a first column selection circuit;
a second column selection circuit that selects a plurality of columns based on a column address selection signal and a block write signal; Batch writing to bit cells is performed based on the block write signal.

[0015]

[Operation] In the present invention, a column selection circuit that selects a column of a memory array of a random access memory (RAM) is divided into a first column selection circuit that selects a single column based on a column address selection signal, and a column selection circuit that selects a single column based on a column address selection signal. It has a second column selection circuit that selects a plurality of columns based on the address selection signal and the block write signal, and has a circuit configuration that can switch between the single column selection operation and the multiple column selection operation. The block write function can be realized without increasing the number of input/output buses of the output buffer. Furthermore, the number of bits to be block written can be freely set by using a logic circuit or the like to cut off the one corresponding to a lower predetermined bit among the plurality of column address selection signals input to the second column selection circuit. can.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a block write circuit configuration for explaining a semiconductor memory device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIGS. 4 and 6 indicate the same or corresponding parts, 101a to 101n are memory cells in a predetermined row of the RAM memory array, 102a to 102n
1 is a bit line for accessing information to each of the memory cells, and 104a to 104n are sense amplifiers connected to each of the bit lines. 1105a to 1105n are logic circuits provided for each column of the RAM memory array and output column decoder outputs 105a to 105n, and these are logic circuits 1100a to 1105n which output the column decoder outputs during normal operation ~1100n, and a second logic circuit 1 that outputs the above column decoder output during block write.
101a to 1101n, and third logic circuits 1102a to 1102n that calculate the logical sum of the first and second logic circuits.

The first logic circuit 1100 is composed of a NAND circuit that receives a plurality of column address selection signals A0 to An, which are signal lines for specifying each column. The second logic circuit 1101 is a NAND circuit that receives the column address selection signals A0 to An and the block write signal ψ, and in this circuit, a predetermined lower bit of the selection signal is controlled by another logic circuit. (not shown), and the other logic circuit allows selection of a predetermined column from the RAM memory array. For example, lower address selection line A
0, A1 are cut off, 4 bits are selected at the same time, and the lower address selection lines A0, A1, A2 are selected simultaneously.
8 bits are selected at the same time. Further, here, the RAM input/output buffer 4 is connected to the second logic circuit 1.
101a to 1101n have block write means for outputting write data to the RAM input/output bus 5 when a write signal φ is input while a plurality of bits are selected.

Next, the operation will be explained. In the case of normal 1-bit writing and reading, when a row is selected, only a predetermined one of the plurality of row address lines, that is, word lines, is activated, and memory cells 101a to 101n connected to the selected word line 103 are activated. The data of bit lines 102a-1
02n. Next, the sense amplifier 104a~
104n starts sensing, after which a column decoder output is output from one of the first logic circuits 1100a to 1100n, and a predetermined bit line is connected to the RAM input/output bus 5. In this state, writing or reading is performed by the RAM input/output buffer 4.

[0019] Also, in the case of block write (batch write),
When a predetermined word line 103 rises, data in memory cells 101a to 101n is transferred to bit lines 102a to 102n.
102n. In the case of block write, the write signal φ is not sensed immediately after the word line 103 rises, and the write signal φ
is input, and the write data is transmitted to the RAM input/output bus 5 by the RAM input/output buffer 4.

Next, the second logic circuits 1101a to 110
When a block write signal ψ and a predetermined address signal are input to 1n, only a predetermined one of the second logic circuits outputs a column decoder output, thereby blocking only the bit line of the bit to be block written. Write write data is transmitted.

In this write operation, when the word line 103 is activated, the data previously written in the memory cell 101 is transmitted to the bit line 102 first, so that the data input from the RAM input/output bus 5 is transmitted to the bit line 102 first. For block write write data, even if a plurality of column decoders 105 are turned on, the write voltage must be made stronger than for the data of memory cell 101. For this reason, after block writing to a plurality of bit lines 102, the sense amplifier 104 is operated to write a complete "H" or "L" level into the memory cell 101.

Next, the control for specifying the bit line to be block written before block writing will be briefly explained. FIG. 2 is a time chart diagram showing the load color cycle, that is, the cycle that loads data to be block written into the color register, and the count cycle, that is, the cycle that counts the bit lines that are block written. This shows the case where the cycle is combined into one. In the figure, inverted RA
S, inverted CAS, and DSF are control signals input to the internal signal generator 8, and A4 and A3 are column address selection signals in normal operation, and these signals set the timing of the block write operation. .

That is, the low level edge of the inverted RAS in the high level state of the inverted CAS and DSF defines the load color cycle and the count cycle, and the next write data is block written at the timing of the low level edge of the inverted CAS. The color and the count, which is the number of bits to be block written, are loaded from the external data input/output terminal 22 in preparation for the next cycle, the block write cycle. FIG. 3 is an example of a time chart of a block write cycle, and the same reference numerals as in FIG. 1 are the same. Block write is started with inverted RAS low level, inverted CAS low level, and DSF high level.

As described above, in this embodiment, during normal write and read operations for each bit, the column address selection signals A0 to
In addition to first logic circuits 1100a to 1100n that output column decoder outputs 105a to 105n based on An, second logic circuits 1101a to 1101n that output predetermined column decoder outputs at the time of block write are provided. In the previous count cycle, the second
Since the number of bits to be block written is specified by the logic circuit, when the block write signal ψ is input, 4
A plurality of column decoders specified in the previous cycle, such as bit, 8 bit, 16 bit, etc., are activated, and data is written to a plurality of bits from the input bus. This allows the block write function to be implemented without increasing the number of input/output buses. Furthermore, among the plurality of column address selection signals input to the second logic circuit, the one corresponding to the lower predetermined bit is cut off by another logic circuit.
This has the effect that the number of bits to be block written can be freely set.

In addition to the RAM, a serial access memory (SAM) is provided in which the number of columns of the memory array is equal to the number of columns of the memory array of the RAM, and the RAM and S
Since each memory constitutes a dual-port memory section that can operate asynchronously except for data transfer operations between AMs, image processing involves drawing, that is, writing image information to memory, and drawing, that is, writing image information to memory. Image information can be read out from the memory at the same time.

[0026] In the above embodiment, in addition to RAM, S
Although a dual-port memory that has an AM and can operate asynchronously in each memory except for data transfer operations between the RAM and SAM has been described, this may also be a single-port memory that does not have the above-mentioned SAM. . in this case,
This embodiment has the same effects as the above embodiment except for the simultaneous operation of drawing and drawing in image processing.

[0027]

As described above, according to the semiconductor memory device of the present invention, the column selection circuit for selecting a column in a memory array of a random access memory (RAM) can be configured to select a single column based on a column address selection signal. a first column selection circuit for selecting;
and a second column selection circuit that selects a plurality of columns based on the column address selection signal and the block write signal, and has a circuit configuration that can switch between the single column selection operation and the multiple column selection operation. , the block write function can be realized without increasing the number of input/output buses of the input/output buffer. Furthermore, the number of bits to be block written can be freely set by using a logic circuit or the like to cut off the one corresponding to a lower predetermined bit among the plurality of column address selection signals input to the second column selection circuit. There is an effect that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a load color cycle and a count cycle in a block write operation of the semiconductor memory device.

FIG. 3 is a diagram showing a block write cycle in the block write operation.

FIG. 4 is a diagram showing a block configuration of a conventional dual port RAM.

FIG. 5 is a diagram showing an example of an image processing system using the conventional dual port RAM.

FIG. 6 is a diagram showing a conventional block write circuit configuration.

FIG. 7 is an explanatory diagram of a general block write operation.

[Explanation of symbols]

1 R.A.
M memory array (main memory array) 2 Row decoder (row selection circuit) 3
Column decoder (column selection circuit) 4 RA
M input/output buffer (data writing/reading means) 11 SAM
Memory array (auxiliary memory array) 12 Serial selector (auxiliary selection circuit) 14 SAM
Input/output buffer (auxiliary access means) 101a to 101n Memory cell 102a to
102n bit line 103
Word lines 104a-10
4n sense amplifier 105a to 105n
Column decoder outputs 1100a to 1100n First logic circuit (first column selection means) 1101a to 1101n Second logic circuit (second column selection means) 1102a to 1102n Third logic circuit 1105a
~1105n logic circuit

Claims (3)

[Claims] Claim 1: A main memory having a main memory array formed by arranging memory cells in row and column directions, and a row and column selection circuit for selecting a row and column of the main memory array; A selection means for selecting a memory cell, and a data write/reader for writing and reading data into and from the selected memory cell.
In the semiconductor memory device, the column selection circuit includes a first column selection means for selecting a single column based on a column address selection signal, and a column address selection signal. and a second column for selecting a plurality of columns to be block written based on the block write signal.
column selection means, and further comprising block write means for collectively writing data to a plurality of bit cells selected by the second column selection means when the block write signal is input. Semiconductor storage device. 2. The semiconductor memory device according to claim 1, further comprising, in addition to the main memory, an auxiliary memory having an auxiliary memory array whose number of columns is equal to the number of columns of the main memory array, and wherein the main memory and the auxiliary memory between memory and
The selection means includes an auxiliary selection circuit for selecting a memory cell from the auxiliary memory array, and the selection means includes an auxiliary selection circuit that selects a memory cell from the auxiliary memory array. The data writing/reading means has auxiliary access means for writing and reading data to and from selected memory cells of the auxiliary memory array, and the main memory and the auxiliary memory perform operations other than data transfer operations between them. A semiconductor memory device comprising a dual-port memory section in which each memory can operate asynchronously. 3. The semiconductor memory device according to claim 1, wherein writing to the memory includes a load color cycle for loading data to be written in a block, a count cycle for setting the number of bits to be written in a block, and the like.
A semiconductor memory device characterized in that writing is performed by a block write cycle in which actual writing is performed.