JPH0422238A - Data discriminating device - Google Patents

Abstract

PURPOSE:To execute the optimal discriminating operation by detecting the jitter quantity by an N level deciding device, and varying a phase of a clock signal from an M frequency divider based on this jitter detecting signal. CONSTITUTION:To a jitter detector 8, a pulse signal C, an original oscillation clock signal D and a clock signal E are inputted, and based on the signal E as a reference, a phase of the signal E is divided equally into M by the signal D, at which phase timing the signal C is inputted is detected, and information of the phase in which the signal C is small or does not exist is outputted to a variable phase shifter 9 as a jitter detecting signal F. In the phase shifter 9, the phase of the signal E is shifted in accordance with the information of the signal F, and outputted to a discriminating circuit 7 as a discriminating clock signal G. In the circuit 7, data is discriminated from a detecting output signal A by the signal G. In such a way, the discriminating operation of optimal data can be executed automatically even in the case of multi-value modulation and even in the case of deterioration of C/N by a simple initial phase adjustment.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data identification device that optimally identifies digital data from a detection output signal in digital transmission.

2. Description of the Related Art Various modulation methods such as ASK, PSK, FSK, and partial response modulation have been put into practical use when transmitting digital signals using carrier wave radio waves. In such a situation, transmission data is identified by regenerating a clock from the transmission data including a clock component, and identifying the data from the regenerated clock signal.

A conventional example will be described below with reference to the drawings. The fourth time is made up of blocks of a conventional data identification device, and (N-1) comparison outputs B are input to the identification circuit 7. On the other hand, the logical sum output of the change points of each comparator is also output from the N level determiner 1 to the pseudo clock generator 2ζ. The pseudo clock generator 2 outputs a one-difference signal at a timing corresponding to the change point of each comparator. The phase error signal is smoothed by a low pass filter 4 and controls a voltage controlled oscillator 5. A voltage control oscillator 5 generates an original oscillation clock signal, which is frequency-divided by M by an M frequency divider 6 and outputted as a clock signal E. With the above configuration, the clock signal E works in synchronization with the data in the detection output signal A, and the identification circuit 7 uses the clock signal E.
Obtain data from comparison output B.

The operation of the data identification device configured as described above will be explained below. The fifth diagram is a diagram showing the eye pattern of the detection output signal A in BPS modulation, the state of the comparison output B, and the phase relationship with the reproduced clock signal E. In FIG. 5, the optimum identification phase is near T, where the eye opening is maximum, and data may be misidentified near To and Tz depending on the signal condition.

Problems to be Solved by the Invention However, with the configuration shown in Fig. 4, there is almost no problem when the C/N is good and stable as shown in Fig. 5, but the C/N is poor and the eye pattern deteriorates, causing problems. The phase of clock output E is optimal when the eye is not open, or when using multilevel modulation, which is used to increase the transmission rate without changing the transmission band, or to narrow the transmission band without changing the transmission rate. Otherwise, the possibility of error is very high.

FIG. 6(a) shows the eye opening state of the eye pattern of the BPSK detection output signal when the C/N is low and the comparison output B. During the period α of the comparison output B, the phase of the clock signal E is Figure 6 (b) shows a valid period in which no error will occur if the identification operation is performed during the period α, and an invalid period in which an error will occur if the identification operation is performed in the period β. As an example, a case of 5-level ASK modulation is shown. From FIGS. 6(a) and (1)), the effective period α becomes significantly narrower due to deterioration of C/N and multilevel modulation. Therefore, although the phase of the clock signal for identification operation is adjusted to the desired phase during initial adjustment, it is vulnerable to subsequent changes over time and temperature drift, and when C/N deteriorates or multilevel modulation is performed, the clock signal A slight phase shift will cause major deterioration.

! Means for Solving Problem i In order to solve problem iu above, the present invention provides an N-level signal by inputting a pulse signal of a pseudo clock generator, an original oscillation clock signal of a voltage controlled oscillator, and a clock signal of an M frequency divider. It consists of a jitter detector that detects the amount of jitter in the determiner, and a variable phase shifter that varies the phase of the clock signal from the M frequency divider based on the jitter detection signal from the jitter detector.

According to the above-described configuration, the present invention detects the amount of jitter by dividing the phase of the clock signal into M equal parts based on the regenerated clock signal, and detecting in which phase there are many changing points, and in which phase there are many changing points. The information on the phase that does not exist is output as a jitter detection signal to the variable phase shifter, and the variable phase shifter shifts the phase of the clock signal to a phase with fewer or no changing points in the N level determiner, thereby achieving the optimal identification operation. It is intended to realize the following.

Embodiment Hereinafter, a data identification device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data identification device that is an embodiment of the present invention. Common numbers and symbols used in FIGS. 1 and 4 indicate the same thing. In FIG. 1, a detection output signal A having an amplitude level of N values is
The amplitude level is determined by the N level determiner 1. The comparison output B of the determination result is input to the identification circuit 7. On the other hand, the OR output of the change point of the comparison output B is output to the pseudo clock generator 2. The pseudo clock generator 2 generates a pulse signal C of a constant width at the timing of the change point.

The phase comparator 3 compares the phases of the clock signal E, which is the output of the M-minute Ji 16, and the pulse signal C, and outputs a phase error signal according to the phase difference. The phase error signal is smoothed by a low pass filter 4 and controls a voltage controlled oscillator 5. A voltage controlled oscillator 5 generates an original oscillation clock signal, which is frequency-divided by M by an M frequency divider 6 and outputted as a clock signal E. With the above configuration, the clock signal E is synchronized with the data in the detection output signal A.

In addition, the jitter detector 8 that detects the amount of jitter in data includes:
Pulse signal C, original oscillation clock signal, and clock signal E
is input, the phase of the clock signal E is divided into M equal parts by the original oscillation clock signal using the clock signal E as a reference, and the phase timing at which the pulse signal C is input is detected. Alternatively, information about an absent phase is output as a jitter detection signal F to the variable phase shifter 9. The variable shifter 9 shifts the phase of the clock signal E according to the information of the jitter detection signal F, and outputs it as an identification clock signal G to the identification circuit 7. The identification circuit 7 uses the identification clock signal G to identify data from the detection output signal A.

As a specific example of the jitter detector 8, a bronch diagram thereof is shown in FIG. The pulse signal C is input to the M-stage shift register 10 and shifted in accordance with the original oscillation clock signal. At this time, the pulse width of the pulse signal C is preferably one clock width of the original oscillation clock signal.The M-stage shift register 10 functions similarly to dividing the phase of the clock signal E into M equal parts by the original oscillation clock signal. do. Therefore, the phase in which the pulse signal C is present is counted using M advance counters to determine how much the pulse signal C is input to the M-stage shift register 10. M number of advance counters 11, -11
．． The smallest counter value or zero counter value is detected by the minimum value detector 12 and outputted as a jitter detection signal F. On the other hand, the counter value (L-1)
When detected, the L-adic counter IL~11. Outputs a reset signal to Moreover, the same effect can be achieved even if the jitter detector 8 is replaced with a microcomputer.

The operation of the data identification device configured as described above will be described below with reference to FIG.

FIG. 3 shows signals for a certain period of time following the detection output signal A, pulse signal C1, original oscillation clock signal D, clock signal E, and identification clock signal G during BPSK modulation.
Detection output signal A and pulse signal C are shown by overwriting signals 1 to B, and identification clock signal G is shown in (1).
(2) and (3) show the changes. When 1.2 of the detection output signal A crosses the threshold, the pulse signal C
1. 2 is output, and the pulse signal C is similarly output for 3.4 and 5.8. 6 to the detection output signal
．． Regarding 7, the pulse signal C is not output because it does not cross the threshold value. Based on the information of 1 and 2 of the pulse signal C, the jitter detector 8 sends the variable phase shifter 9 to the variable phase shifter 9 for two clocks of the original oscillation clock signal. A signal is output so as to delay the clock signal E, and the phase is set to (1) of the identification clock signal G. Next, the phase is changed to (2) of the identification clock signal G using the information of 3, 45.8 of the pulse signal C. Eventually, due to the accumulation of information, the identification clock signal G is set to the phase (3). Also, ■Septinal counter 11. ~11. If the counter value exceeds (L-'1), the jitter detector 8 outputs a counter reset7) signal, and the -adc counter 11.
.about.111 are set to all zeros, but the subsequent operation of the sick detector 8 maintains the previous phase unless the previous phase deteriorates or an even better phase is found.

Effects of the Invention As described above, the present invention detects the amount of jitter in the N level determiner by inputting the pulse signal of the pseudo clock generator, the original oscillation clock signal of the voltage controlled oscillator, and the clock signal of the M frequency divider. By providing a jitter detector that changes the phase of the clock signal from the M frequency divider and a variable phase shifter that changes the phase of the clock signal from the M frequency divider using the jitter detection signal from the jitter detector, it is possible to detect a phase where there are few or no changing points in the comparison output. The phase of the clock signal used for the identification operation is shifted to the detected phase to achieve the optimum identification operation.

As a result, the optimal data identification operation is automatically performed by simple initial phase adjustment even in the case of multilevel modulation and even when the C/N is degraded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data identification device according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a jitter detector which is a component of the present invention, and FIG.
The figure is an explanatory diagram showing the phase relationship during operation of each signal of the present invention,
Fig. 4 is a block diagram showing the configuration of a conventional data identification device, Fig. 5 is an explanatory diagram of the data identification operation of the conventional example, and Fig. 6 (
FIG. 6A is a state diagram of a BPSK detection output signal and comparison output when C7M is low, and FIG. 6B is a state diagram of a five-level ASK detection output signal and comparison output, which is an example of multilevel modulation. 1...N level determiner, 2...Pseudo clock generator, 6...M frequency divider, 7...
・Identification circuit, 8... Jitter detector, 9...
...Variable phase shifter, 10...M-stage shift register, 11. ~11.・・・・・・L-base counter, 12...
...Minimum value detector.

Claims (1)

[Scope of Claims] An N-level determiner that determines the amplitude of a detection output signal of an N-level digital modulation signal to be at N level; and a pseudo clock generator that generates a pseudo clock at a change point of the output signal of the N-level determiner. a phase comparator that receives the output signal of the pseudo clock generator as one input; and a low-pass filter that receives the output signal of the phase comparator as input.
a voltage controlled oscillator whose oscillation frequency is controlled by the output voltage of the low-pass filter; and an M frequency divider that divides the oscillation frequency of the output signal of the voltage controlled oscillator by M, the output signal of the M frequency divider. a jitter detector which is supplied as the other input of the phase comparator, receives output signals from the M frequency divider, the pseudo clock generator and the voltage controlled oscillator, and outputs a jitter detection signal; , a variable shifter that shifts the phase of the output signal of the M frequency divider based on the information of the jitter detection signal, and an identification circuit that identifies the output signal of the N level determiner as data using the output signal of the variable phase shifter. Equipped with a data identification device.