JPH04222058A - Method for inspecting test pattern of logical circuit - Google Patents

Abstract

PURPOSE:To report information for effectively evaluating the failure detecting capacity of a test pattern by counting up the number of effective toggles in each net. CONSTITUTION:Logical gates G1 to G5 are formed in a logical circuit 10. A test pattern to be inspected is inputted to respective input terminals A to F, H. The test pattern is executed in each step by means of a logical simulator and the number of changes (the number of toggles) in the logical states of nets n1 to n13 is counted up. Whether changes in the logical states of respective nets can be observed by output terminals X, Y or not is discriminated, and at the time of discriminating the changes can be observed, the number of toggles is counted up as the number of effective toggles in the net. Namely the number of toggles and the number of effective toggles are accumulated in each net. Then an inspection result mainly following the number of toggles and the number of effective toggles in each net is printed out as a report.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides a test pattern of a logic circuit that is input to an input terminal of the logic circuit while observing the output state of the output terminal of the logic circuit in order to detect a failure in a given logic circuit. In particular, the present invention relates to a test pattern testing method for logic circuits for more effective evaluation of the test pattern's ability to detect faults.

0002

[Prior Art] A fault detection method for a logic circuit such as an integrated circuit, which is made up of predetermined logic gates, involves sequentially inputting test patterns prepared in advance to the input terminals of the logic circuit. There is a method of observing the output state of .

In this method, for example, a test pattern to be input to an input terminal and a corresponding expected output pattern are created in advance, and this test pattern is input to an input terminal of a predetermined logic circuit to be tested. Then, the output state of the output terminal at this time is compared with this expected output pattern, thereby detecting a failure in the logic circuit.

[0004] According to such a logic circuit fault detection method, it is possible to detect a fault in an already completed logic circuit, for example, an integrated circuit sealed in a package, from outside the integrated circuit.

[0005] Further, as a method for inspecting a test pattern used for detecting a failure in a predetermined logic circuit, there are a toggle check method and a toggle check tool that automatically performs this toggle check method.

In fault detection of logic circuits using test patterns, as the number of input terminals of the logic circuit to be tested increases, the number of test patterns for testing the logic circuit increases.

Therefore, in fault inspection of logic circuits using test patterns, it is difficult to use test patterns that include all patterns for input terminals.

Furthermore, even if a test pattern covers all patterns for input terminals, it may not be possible to detect all failures in a logic circuit.

[0009] Therefore, the test patterns themselves used to detect failures in such logic circuits are also inspected.

The above-mentioned toggle check is one of the test pattern inspection methods used for fault inspection of logic circuits.

This toggle check is performed by using a logic simulator that can simulate the logic circuit that is the fault detection target of the test pattern to be inspected, while simulating the logic circuit that is the fault detection target of the test pattern. Inspect itself. At this time, changes in the logic state of each net within the logic circuit are detected, and the number of changes in the logic state, ie, the number of toggles, is counted for each net.

According to such a toggle check, it is possible to evaluate the failure detection ability of a test pattern to be inspected according to the inspection result report, which is the number of toggles of each net obtained as an inspection result.

[0013]

[Problem to be achieved by the invention] However, in the test pattern inspection using the above-mentioned toggle check,
The inventor has discovered a problem in that even if a change in the logic state of each net is detected, it is not necessarily possible to detect a failure regarding this net portion from outside the logic circuit.

In other words, the inventor discovered that even if changes in the logic state of each net are counted during test pattern inspection by toggle check, this change in logic state may not be observed at the output terminal of the logic circuit. is heading.

[0015] If the output terminal cannot be observed, there is a problem that even if there is a fault related to this net part, this fault cannot be discovered by fault inspection using this test pattern.

The present invention has been made to solve the above-mentioned conventional problems, and in order to detect a failure in a predetermined logic circuit, the output state of the output terminal of the logic circuit is observed. An object of the present invention is to provide a method for inspecting a logic circuit test pattern that is input to an input terminal, which is capable of reporting information for more effective evaluation of the fault detection ability of this test pattern. purpose.

[0017]

[Means for Accomplishing the Object] In order to detect a failure in a predetermined logic circuit, the present invention detects a failure of a logic circuit input to an input terminal of the logic circuit while observing an output state of an output terminal of the logic circuit. In a test pattern inspection method, a test pattern is executed step by step in logic simulation, and when the logic state of a net inside the logic circuit changes, the change in the logic state can be observed at the output terminal of the logic circuit. If it is determined that it is observable,
The above-mentioned problem is achieved by counting up the number of effective toggles of the net.

[0018] Furthermore, when the logic state of each net changes, a toggle condition is determined in advance so that the change in the logic state can be observed at the output terminal of the logic circuit, and the logic state of the net inside the logic circuit is determined in advance. The above-mentioned problem can also be achieved by making the above-described judgment as to whether a change in the logic state is observable at the output terminal of the logic circuit when the change occurs in accordance with this toggle condition. be.

[0019]

[Operation] The present invention provides a method for testing a test pattern of a logic circuit, in which the logic state of each net of the logic circuit to be tested by the test pattern must change in accordance with the execution of the test pattern. This focuses on the fact that changes in should be observable from outside the logic circuit.

That is, a change in the logic state of a net inside this logic circuit must be observable as a change in the logic state of the output terminal of this logic circuit.

Therefore, in the test pattern inspection method for a logic circuit of the present invention, when the logic state of a net inside the logic circuit changes, it is determined whether the change in the logic state is observable at the output terminal of the logic circuit. If it is determined that the net is observable, the number of effective toggles of the net is counted up. Therefore, after completing this logic circuit test pattern testing method, by obtaining test results mainly based on the number of effective toggles of each net, it is possible to more effectively evaluate the failure detection ability of this test pattern.

Note that the logical state of the present invention refers to the logical value "0".
” or “1” state. Or, logical value “0”.
” or “1” state as well as a high impedance state.

Further, the term "toggle" according to the present invention refers to a mutual change between these logic states. Further, the number of toggles or the effective number of toggles of the present invention may be anything that corresponds to the number of changes. Note that this net is each wiring inside the logic circuit.

FIG. 1 is a flow chart showing the gist of the present invention.

The process shown in the flowchart of FIG. 1 is capable of simulating a logic circuit in which a fault is detected using a test pattern to be inspected in the logic circuit test pattern inspection method. This is done using a logic simulator.

This logic simulator calculates the output of the output terminal of the logic circuit when the test pattern to be inspected by the logic circuit test pattern inspection method is input to the input terminal of the logic circuit for each step. Not only can the state be obtained, but also the logical state of each net within the logic circuit can be grasped.

In FIG. 1, in step 104,
A logic simulator performs a simulation of a logic circuit to be inspected by a test pattern, and also executes one of the corresponding steps of this test pattern.

In step 106, step 104
A change in the logic state of each net inside the logic circuit is detected by simulating the one-step execution of the test pattern.

Note that for the net for which a change in logic state has been detected in step 106, the number of times this change has occurred may be counted and used as the toggle number of the net. That is, the number of toggles may be counted for each net.

[0030] In step 108, the step 106
Regarding the net for which a change in logic state has been detected, it is determined whether this change in logic state is observable at the output terminal of the logic circuit.

In step 110, if it is determined that the change in the logic state of the net whose logic state has changed is observable as a change in the logic state of the output terminal of the logic circuit, the effective number of toggles of the net is calculated. Count up. Therefore, the number of effective toggles for each net includes a change in the logic state for each net, and the number of times this change in logic state was determined to be observable at the output terminal of the logic circuit is accumulated. .

In step 114, it is determined whether the test pattern executed step by step has been completely executed.

When all test patterns have been completed, the execution of this series of logic circuit test pattern inspection methods is completed. On the other hand, if there is a test pattern that has not been executed, the series of processes from step 104 to step 114 is executed again.

As explained above, the effective number of toggles of each net obtained in this way is
This corresponds to the number of changes in the logic state that can be observed at the output terminal of a logic circuit, and also corresponds to the fault detection ability of the logic circuit that is the object of this test pattern using this test pattern. Therefore, according to such a test pattern inspection method for logic circuits, it is possible to report information for more effective evaluation of the fault detection ability of the test pattern.

In the present invention, when the logic state of the net inside the logic circuit changes, the change in the logic state is
The inventor has discovered that determining whether or not the output terminal of the logic circuit is observable is determined according to a predetermined toggle condition.

That is, in order to inspect a test pattern of a logic circuit, before executing the test pattern step by step in a logic simulator, when the logic state of each net of the logic circuit changes, the logic state of the net is checked in advance. A toggle condition, which is a condition for a change to be observable at the output terminal of the logic circuit, is determined in advance. Also, when a test pattern is executed step by step in a logic simulator and the logic state of a net inside the logic circuit changes during this logic simulation, the change in the logic state can be observed at the output terminal of the logic circuit. When determining whether this is the case, this toggle condition is used.

In this way, when such a toggle condition is used in the test pattern inspection method for a logic circuit according to the present invention, a change in the logic state of a net inside the logic circuit can be detected at the output terminal of the logic circuit. It is possible to simplify and shorten the process of determining whether the test pattern of the logic circuit is observable, and it is possible to shorten the overall testing time for testing the test pattern of the logic circuit.

[0038]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a flowchart showing the processing of the embodiment of the present invention.

The automatic test pattern testing device for logic circuits according to the embodiment of the present invention includes a tool for designing an integrated circuit layout, a logic simulator, etc.
It is configured in one computer system.

Step 210 in FIG. 2 is similar to the step 210 in FIG.
This corresponds to the series of processes shown in the flowchart.

In this FIG. 2, in step 204,
For example, input change propagation conditions are determined for each logic gate, and are registered and stored in a readable format in step 206 or step 208, which will be described later.

Note that this input change propagation condition may be determined for each cell in a logic circuit using a cell library. Alternatively, it may be a more complex logic gate unit consisting of a plurality of logic gates. Further, the registration in step 204 may be performed only when there is a change in the logic gate used in the logic circuit, such as when data in the cell library is changed. Note that the registration performed in step 204 will be described in more detail later using FIG. 3.

In step 206, when determining the test pattern to be inspected and the logic circuit to be inspected by this test pattern, all possible paths for signal flow from each input terminal to each output terminal of this logic circuit are determined. demand. Note that the processing performed in step 206 is as follows:
This will be described in more detail later using FIGS. 4 and 5.

In step 208, toggle conditions are determined for all nets of the logic circuit targeted by the test pattern to be inspected, including all paths to the output terminal of the logic circuit.

Note that the toggle condition for each net is a condition that when the logic state of each net changes, the change in the logic state can be observed at the output terminal of the logic circuit. Furthermore, if there is no need to detect a fault with respect to a certain net portion in a logic circuit or a portion related to this net portion (substantially the circuits surrounding this net), there is no need to determine the toggle condition for this net. Note that the process of determining the toggle condition performed in step 208 is as follows:
The input change propagation conditions for each logic gate obtained in step 204 and the paths from each input terminal to each output terminal of the logic circuit obtained in step 206 are used.
This process will be described in more detail later using FIG. 6.

In step 210, as described above with reference to FIG. 1, the test pattern to be inspected by the test pattern is tested using a logic simulator capable of simulating the logic circuit to be detected by the test pattern.
This is executed step by step, and the number of times the logic state of the net inside the logic circuit changes (the number of toggles) is counted.

At this time, when the logic state of the net inside the logic circuit changes, it is determined whether the change in the logic state is observable at the output terminal of the logic circuit, and if it is determined that the change is observable, also counts up the number of valid toggles for the net. That is, the number of toggles and the number of effective toggles are accumulated for each net.

Note that such counting of the number of toggles and the number of effective toggles is generally performed for all nets inside a logic circuit, but for a specific net portion or a portion related to a specific net portion. If there is no need for failure detection regarding (generally the peripheral portion of this net), there is no need to count the number of toggles and the number of effective toggles regarding this net.

In step 212, the inspection results mainly based on the number of toggles and the number of effective toggles for each net of the logic circuit obtained in step 210 are output as a report as a printout using a line printer.

Specifically, the printed test result is a printed list of the number of toggles and the number of effective toggles for each net. Also, print out a list of nets that have a "0" toggle count or a valid toggle count among the nets that are subject to the logic circuit test, in other words, nets that cannot be detected by the test pattern that is the subject of the test. I do. Also, print out the ratio of the number of nets with a toggle number of "0" to the total number of nets, and the ratio of the number of nets with an effective toggle number of "0" to the total number of nets. .

In this way, in step 212, various information that is effective for evaluating the fault detection ability of the test pattern of the logic circuit is obtained according to the number of dockles and the number of effective toggles for each net determined in step 210. Data is printed out.

It goes without saying that the type of printed output that is actually output can be selected.

FIG. 3 is a diagram showing an input change propagation condition table for each type of logic gate used in the embodiment of the present invention described above.

In the automatic test pattern inspection device for logic circuits according to the embodiment of the present invention, which is configured in one computer together with an integrated circuit layout design tool, a logic simulator, etc., the system shown in FIG. The input change propagation condition table for each logic gate type is created in step 204 of the flowchart of FIG. 2 described above, mainly in accordance with the data of the cell library used mainly for designing the integrated circuit layout in the computer system.

This input change propagation condition table for each type of logic gate is created as data of items for each input terminal for each type of logic gate registered in the cell library.

[0057] This data record also includes conditions for, when the logic state of the input terminal of a predetermined logic gate type changes, the logic state of the output of the logic gate changes in accordance with the change in the logic state; That is, the input change propagation conditions are determined and written. Further, as a record of this data, the time from the change in the logic state of the corresponding logic gate until the change in the logic state of the output occurs, that is, the propagation delay time (unit: nS) is also determined and written.

Note that the types of logic gates in the input change propagation condition table for each type of logic gate shown in FIG. However, if the propagation delay time is different, it is considered to be a different logic gate type.

Note that the input change propagation condition table for each logic gate type in FIG. It is used to obtain propagation conditions and propagation delay times.

FIG. 4 is a logic circuit diagram of an example of a logic circuit to be detected for failure in a test pattern to be inspected in the embodiment of the present invention described above.

The logic circuit 10 of FIG. 4 is provided with a total of seven input terminals A to F, H, and a total of two output terminals X, Y.

[0062] Also, inside this logic circuit 10, there are a total of 5
Logic gates G1 to G5 are provided.

The logic gates G1 and G2 are the same as those shown in FIG.
It is an ND gate. Logic gates G3 and G5 are the OR gates of FIG. 3 described above. Logic gate G4 is as shown in FIG.
This is a D-type flip-flop.

These input terminals A to F, H, output terminals
Y, between the logic gates G1 to G5, there are nets n1 to
n 13, respectively.

In such a logic circuit 10, after the logic circuit 10 is manufactured, a change in the logic state of each of the nets n1 to n13 inside the logic circuit 10 is caused by a change in the logic state of the output terminals X, Y of the logic circuit 10. becomes observable only as a change in the logical state of .

However, during simulation by the logic circuit simulator, not only the logic states of the output terminals X and Y of this logic circuit 10 but also the logic states of the output terminals
It is also possible to observe the logic state of each of the internal nets n1 to n13 and changes in the logic state.

Note that the codes D, CK, and the logic gate G4 are
CL is an input terminal, and symbols Q and QN are output terminals.

The test pattern to be inspected for the test pattern of the logic circuit according to the embodiment of the present invention is the pattern of input signals input to each input terminal A to F, H of the logic circuit 10 in FIG. It is.

FIG. 5 is a diagram showing a path list in a logic circuit used in the embodiment of the present invention described above.

The path list in the logic circuit shown in FIG. 5 is created in step 206 of the flowchart in FIG. 2 described above.

The path list in the logic circuit shown in FIG. 5 includes all the paths ( In addition to listing the signal flow), the signal flow is determined for each path.

For example, the data entered in the logic circuit path list of FIG. 5 includes all paths from input terminals A to F, H to output terminals X, Y to the logic circuit 10 of FIG. Shows some data.

In FIG. 5, for example, the path number "1"
” is a path that passes through input terminal A, input a and output y of logic gate G5 (logic gate genus number 5), and output terminal Terminal B, input a and output y of logic gate G1
(Logic gate type number 1), input a of logic gate G3
and output y (logic gate genus number 5), input D and output Q of logic gate G4 (logic gate genus number 3), input b and output y of logic gate G5 (logic gate genus number 6), output terminal This is a path that passes through each X in turn.

The data obtained as the data for the path list in the logic circuit shown in FIG. 5 is used when obtaining the toggle condition for each net of the logic circuit in step 208 of the flowchart shown in FIG. 2 described above.

FIG. 6 is a diagram showing an input change propagation condition table for each net in a logic circuit used in the embodiment of the present invention described above.

The input change propagation condition table for each net in the logic circuit shown in FIG. 6 is created in step 208 of the flowchart shown in FIG. It is created mainly using the logic circuit path list.

The creation of the input change propagation condition table for each net in the logic circuit shown in FIG. 6 is performed in order starting from net number "1". This is to determine the conditions under which state changes can be observed at the output terminal of the logic circuit.

Furthermore, the data entered in the input change propagation condition table for each net in the logic circuit in FIG.
This is created using the data of the input change propagation condition table for each logic gate shown in FIG. 3 and the data of the path list in the logic circuit shown in FIG. 5 in the logic circuit 10 shown in FIG.

That is, first, the path (path number) passing through the net of the corresponding net number is searched for by using the path list in the logic circuit shown in FIG. while calculating the path number that includes the corresponding net number.

[0080] The change in the logical state of the corresponding net number is
When the path number of the path transmitting to the output terminal of the logic circuit is obtained, for each logic gate in the logic gate type item of the corresponding path number in the path list in the logic circuit shown in FIG. Using the input change propagation condition table for each type, find the input change propagation conditions and propagation delay time of the logic gate, and enter them in the input change propagation condition item column in the input change propagation condition table for each net in the logic circuit in FIG. and the column for the propagation delay time item.

If there are multiple paths passing through the net with the corresponding net number, a series of input change propagation conditions for each of these paths are sequentially created in the input change propagation condition table for each net in the logic circuit shown in FIG. I will write it in.

In the data of the input change propagation condition table for each net in the logic circuit in FIG.
”, the path with the path number “1” passing through the net with the net number “1” from the path list in the logic circuit in FIG. 5 is selected according to the data of the input terminal a of the OR gate of the logic gate G5. The input change propagation conditions and propagation delay times are obtained from the input change propagation condition table for each logic gate type (item number 6) in FIG. written.

Similarly, for net number "2", a total of two paths with path numbers "2" and "3" are obtained from the path list in the logic circuit shown in FIG. From the type of logic gate and input,
Using the input change propagation condition table for each type of logic gate shown in FIG. 3, the corresponding input change propagation conditions and propagation delay time are determined.

The data in the input change propagation condition table for each net in the logic circuit shown in FIG. It is used as a toggle condition when determining whether it is observable at the output terminal of a circuit.

That is, for a net with a predetermined net number, the conditions in the input change propagation condition table for each net in the logic circuit in FIG. If all of the conditions are met, the toggle condition is met.

Note that if there is a plurality of series of data in the input change propagation condition table for each net in the logic circuit for the same predetermined net number, all of the series of input change propagation conditions must be satisfied. The toggle condition is met. For example, the toggle condition for net number “2” is a condition under which either “toggle condition ■ for net number “2”” or “toggle condition ■ for net number “2”” in FIG. 6 is satisfied. .

That is, in such a case, there are multiple paths from a net with a predetermined net number to the output terminal of the logic circuit.

FIG. 7 is a diagram showing a toggle number table for each net in a logic circuit created according to the embodiment of the present invention described above.

The toggle number table for each net in the logic circuit shown in FIG. 7 is written with the number of toggles and the number of effective toggles for each net in the logic circuit that is the target of failure detection in the test pattern inspected in this embodiment. It is a table that can be used.

The toggle number table for each net in the logic circuit shown in FIG. 7 is created by the process of step 210 in the flowchart shown in FIG. 2 described above. That is, the number of toggles and the number of effective toggles in the toggle number table for each net in the logic circuit in FIG. 7 are the same as the number of toggles and the number of effective toggles in FIG. 2 described above.

FIG. 8 is a diagram showing a test pattern inspection report printed out in the above-described embodiment of the present invention.

[0092] In FIG. 8, the underlined printed portions of each item are the portions on which the respective determined numerical values or character strings of names are printed.

In FIG. 8, item 1 is printed with the name of the test pattern inspected in this embodiment of the present invention.

[0094] In item 2, the total number of steps of the test pattern having the test pattern name in item 1 is printed.

Items 3 to 7 are the total number of logic gates, total number of inputs, total number of outputs, total number of paths, and The total number of nets is printed.

Items 8 and 9 also include the number of nets with toggle count "0" after execution of all steps of this test pattern, and the number of toggles relative to the total number of nets in item 7.
The ratio of the number of nets with "0", the number of effective toggles, the number of nets with "0", and the number of effective toggles to the total number of nets in item 7 "
The ratio of the number of nets of 0'' is printed respectively.

In item 10, the names (net numbers) of nets for which the number of effective toggles is "0" are printed in order.

As explained above, according to the embodiment of the present invention, a test pattern inspection report as shown in FIG. 8 is obtained which also includes information according to the data of the effective number of toggles of each net in the logic circuit. Therefore, it is possible to more effectively evaluate the fault detection ability of the test pattern.

The tables and lists shown in FIGS. 3 and 5 to 7 are stored in the memory of the computer system in which the process shown in the flowchart of FIG. 2 is executed. Writing and updating of each item and reading are performed as necessary. Further, the logic circuit shown in FIG. 4 is also stored in this computer system by a predetermined means.

[0100]

[Effects of the Invention] As explained above, according to the present invention, in order to detect a failure in a predetermined logic circuit, input is made to the input terminal of the logic circuit while observing the output state of the output terminal of the logic circuit. The present invention has the excellent effect of providing a logic circuit test pattern inspection method that can report information for more effective evaluation of the fault detection ability of this test pattern. have

[Brief explanation of the drawing]

FIG. 1 is a flowchart illustrating the gist of the present invention.

FIG. 2 is a flowchart showing processing of an embodiment of the present invention.

FIG. 3 is a diagram showing an input change propagation condition table for each logic gate type used in the embodiment.

FIG. 4 is a logic circuit diagram of an example of a logic circuit targeted for failure detection in a test pattern to be inspected in the embodiment.

FIG. 5 is a diagram showing a path list in a logic circuit used in the embodiment.

FIG. 6 is a diagram showing an input change propagation condition table for each net in a logic circuit used in the embodiment.

FIG. 7 is a diagram showing a toggle number table for each net in a logic circuit used in the embodiment.

FIG. 8 is a diagram showing a test pattern inspection report printed out from the embodiment.

[Explanation of symbols]

10...Logic circuit, A to F, H...Logic circuit input, X, Y...
Logic circuit output, G1 to G5...Logic gate, a, b
, D, CK, CL...Logic gate input, y, Q, QN
...Logic gate output, n1-n13...net.

Claims (2)

[Claims] 1. A method for inspecting a test pattern of a logic circuit input to an input terminal of the logic circuit while observing an output state of an output terminal of the logic circuit in order to detect a failure in a predetermined logic circuit. Execute the test pattern step by step in simulation, and when the logic state of the net inside the logic circuit changes, determine whether the change in the logic state can be observed at the output terminal of the logic circuit, and make it observable. 1. A method for inspecting a test pattern of a logic circuit, which comprises counting up the number of effective toggles of the net when it is determined that the net is the same. 2. In claim 1, a toggle condition is determined in advance so that when the logic state of each net changes, the change in the logic state can be observed at the output terminal of the logic circuit,
When the logic state of a net inside the logic circuit changes, the determination as to whether the change in the logic state is observable at the output terminal of the logic circuit is a determination in accordance with this toggle condition. A test pattern inspection method for logic circuits.