JPH04218958A - Semiconductor memory and its manufacture - Google Patents

Abstract

PURPOSE:To provide a capacitor with high charge storage and its manufacture by making irregularity on the surface of a charge storage electrode. CONSTITUTION:Irregular parts are formed on a surface (first surface 605) facing to the layer insulation film 607 of a charge storage electrode and other surface (second surface 609) and a plate electrode 613 is formed on the first surface 605 and second surface 609 so that a capacitor with high charge storage is obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor (charge storage section) used in a semiconductor memory element, etc., and a structure of the capacitor.

0002

2. Description of the Related Art One of the memory cell structures of a dynamic random access memory (DRAM), which is a type of semiconductor memory device, is a stacked capacitor cell as shown in FIG. 901 in the figure is a Si substrate, 903
905 is the field oxide film, 905 is the first polysilicon (word line), 907 is the interlayer insulating film, 909 is the second polysilicon (charge storage electrode of the capacitor), 911 is the capacitor dielectric film, 913 is the third polysilicon (the capacitor) (plate electrode), 915 is a switching transistor. This memory cell stores "1" and "0" information depending on the presence or absence of charge accumulated in the capacitor dielectric film 911, and performs operations such as reading, writing, and memory retention by turning on and off the switching transistor 915. There is.

[0003] In the capacitor section of this memory cell, ■ To maintain the memory state for a certain period of time against charge leakage caused by various factors, ■ To obtain a signal higher than the sense-up sensitivity, To prevent soft errors, it is necessary to secure a charge storage amount above a certain value. The charge storage amount C3 of this stacked capacitor cell is determined by the charge storage electrode (second polysilicon 909) and the plate electrode (
The area S of the capacitor dielectric film 911 sandwiched between the third polysilicon 913), its dielectric constant ε, its film thickness d, and “
Due to the write voltage difference V between “1” and “0”, Cs=ε・S
- Expressed as V/2d.

[0004] Due to the reduction in memory cell dimensions due to the recent increase in the degree of integration of semiconductor memory elements, the area S of the capacitor dielectric film 811 has decreased, and it has become difficult to secure Cs above the above-mentioned certain value. .

[0005] As an example of a method for solving this problem, the document ``Extended Abstracts of the 2
0S Conference on Solid States Devices and Materials, Tokyo (Ext.
Ended Abstracts of the 20
th Conference on Solid St
ateDevices and Materials
, Tokyo), 1988, PP. 581-58
There is something disclosed in 4. This method increases the surface area of the charge storage electrodes by stacking the charge storage electrodes in two stages and creating concave side walls.
This is an increase in

The formation procedure is shown in FIG.

First, as shown in FIG. 10(a), a MOS
After forming the first charge storage electrode 1001 on the transistor, as shown in FIG. 10(b), a silicon nitride film Si3 is formed.
After forming N4 1003 and silicon oxide film SiO2 1005 and opening via holes, the second charge storage electrode 1 is formed.
007 is formed.

Next, by removing 1003 and 1005 by wet etching, a recessed side wall is formed as shown in FIG. 10(c). Thereafter, when the capacitor dielectric film 1009 and the plate electrode 1011 are formed, the area S of the capacitor dielectric film 1009 increases as shown in FIG. 10(d). As a result, Cs also increases.

The above method is effective in securing Cs even as the memory cell size decreases.

0010

[Problems to be Solved by the Invention] However, as mentioned above, in the conventional capacitor structure, the area of the capacitor dielectric film decreases due to the reduction in memory cell size due to higher integration, making it difficult to secure the amount of charge storage. It is.

[0011] Furthermore, in the method described above in which charge storage electrodes are stacked in two stages to solve this problem, the difference in level between the capacitor part and other parts becomes large, making pattern formation in subsequent steps difficult. There is a problem.

The present invention solves the above-mentioned problems and provides a method for forming a capacitor that can form a capacitor with a large charge storage capacity, and a capacitor with a large charge capacity.

[0013]

[Means for Solving the Problems] The first invention forms an oxide film on a polysilicon layer serving as a charge storage electrode, and etches the oxide film to form countless minute oxide film masks. By etching the surface of the polysilicon layer by anisotropic etching using a film mask, the surface of the polysilicon layer (charge storage electrode) is made into a surface with countless minute irregularities.

[0014] The second invention is to form a silicon nitride film and a silicon oxide film on an interlayer insulating film, and then: (1) gas plasma etching the silicon oxide film, or (2) changing the silicon from an amorphous state to a polyamide film on the oxide film. After forming a silicon film at a transition temperature that changes to silicon, the silicon film is etched to form irregularities on the surface of the silicon oxide film, and a polysilicon layer is formed according to the shape, forming an interlayer insulating film. Opposing surface (first
A polysilicon layer having irregularities on the surface of the polysilicon layer (the second surface) and the other surface of the polysilicon layer (the second surface) is obtained.

[0015] The third invention is to form a polysilicon layer as a charge storage electrode on an oxide film having an uneven surface and in an opening using silane gas SiH4 at a transition temperature at which silicon changes from an amorphous state to polysilicon. By doing this, the first layer of the polysilicon layer (charge storage electrode)
A polysilicon layer having unevenness on the first surface and the second surface is obtained.

[0016] The fourth invention provides a surface of the charge storage electrode facing the interlayer insulating film (first surface) and the other surface (second surface).
A capacitor with a large amount of charge storage can be obtained by providing an uneven portion on the first surface and forming plate electrodes on the first surface and the second surface.

[0017]

[Operation] Specifically, the oxide film deposited on the polysilicon layer is made of fluorohydrocarbon (CHF3, etc.)
Etching is performed using a mixed gas plasma of fluorocarbon and fluorocarbon (CF4, C2F6, etc.). At this time, if the ratio R of fluoro-hydrocarbon to the total gas amount is set to 65%, fluorocarbon will be formed on the surface of the oxide film 803 while the plasma is unstable (several seconds after the start of discharge), as shown in FIG. 8(a).・Carbon-based polymer 805 is attached, and this is shown in Figure 8.
As shown in (b), this serves as a mask for the oxide film etching that starts after the plasma stabilizes. Therefore, the oxide film 80
3, due to the masking effect of the polymer, it ultimately remains partially on the polysilicon layer 801 (as countless minute oxide film masks), as shown in FIG. 8(c).
etched. Thereafter, by etching the surface of the polysilicon layer 801 by anisotropic etching using the partially remaining oxide film 805 as a mask, the surface of the polysilicon layer 801 can be made into a surface with countless minute irregularities. In addition,
Although R was set to 65%, similar oxide film etching occurs in the range of 65≦R≦100 (%). R=100(%
) means that a gas plasma of fluoro-hydro-carbon alone is sufficient. According to such a method, an etching mask is formed in which the surface of the polysilicon layer (charge storage electrode) is made uneven by the two steps of depositing the oxide film and etching the oxide film.

Furthermore, the thin oxide film on the polysilicon layer is C
400℃ in O3 and organic silane atmosphere by VD method.
, under the condition of O3:organosilane flow rate ratio = 10:1,
A cluster of silicon oxide film SiO2 is formed. Thereafter, by etching the surface of the polysilicon layer using the SiO2 clusters as a mask, the surface of the polysilicon layer can be made into a surface with countless minute irregularities.

Further, the silicon oxide film on the silicon nitride film is etched using a mixed gas plasma of fluorohydrocarbon (CHF3, etc.) and fluorocarbon (CF4, C2F6, etc.). At this time, if the ratio R of fluorohydrocarbon to the total gas amount is set to 65% as described above, fluorocarbon polymer will adhere to the oxide film surface while the plasma is unstable (several seconds after the start of discharge). This serves as a mask for the oxide film etching that begins after the plasma stabilizes. (65≦R≦100) Therefore, the surface of the oxide film finally has an uneven surface shape due to the masking effect of the polymer. By forming a polysilicon layer on this uneven oxide film, the surface of the polysilicon layer can be made uneven.

Furthermore, silane gas (SiH4) is applied onto the silicon oxide film on the silicon nitride film by the LPCVD method.
When a silicon film is formed at 570° C. (the transition temperature at which silicon changes from an amorphous state to polysilicon) using the above method, a silicon film having irregularities on the surface is formed. Thereafter, when the silicon film is removed under the condition that the etching ratio of the silicon film to the silicon oxide film is 1:1, a silicon oxide film having an uneven surface is formed. By forming a polysilicon layer on this uneven oxide film, the surface of the polysilicon layer can be made uneven.

[0021]

【Example】

[0022]

[Embodiment 1] A first embodiment of the present invention will be described below with reference to FIG.

In FIG. 1A, 1.01 is a Si substrate, 103 is a field oxide film, 105 is a first polysilicon (word line), 107 is an interlayer insulating film, and 109 is a switching transistor. On such a base structure, an electrode storage electrode of a capacitor is formed using a polysilicon layer 111 (second polysilicon) having a film thickness of 1500 Å. Furthermore, an oxide film 113 with a thickness of 2000 Å is formed thereon by the CVD method.

Next, the oxide film 113 is etched using a parallel plate type plasma processing apparatus. The plasma generation conditions at this time were: pressure 133 Pa, CF4: 40 sc
cm, CHF3 = 80 sccm, high frequency of 750 W, and etching time of 30 seconds. When the oxide film 113 is etched under these conditions, the oxide film 113 partially remains on the polysilicon layer 111 as shown in FIG. (forming countless minute oxide film masks).

After that, this partially remaining oxide film 113
Using this as a mask, the surface of the polysilicon layer 111 is etched as shown in FIG. 1(c). This polysilicon layer is etched using a parallel plate plasma processing device.
Pressure 20pa, SF6: 20sccm, C2 ClF
5 = 20 sccm, under the conditions of high frequency power 90 W, 1
Do this for 5 seconds. By this etching, the polysilicon portion of the oxide film 113 not covered by the mask is removed by about 500 Å. As a result, the surface of the polysilicon layer 111 becomes a surface with countless minute irregularities. Note that the etching conditions for polysilicon are not necessarily limited to the above conditions as long as the conditions allow polysilicon to be etched anisotropically.

Next, the structure shown in FIG. 1(c) after polysilicon etching was soaked in a hydrofluoric acid aqueous solution (concentration 5%) for 60 minutes.
By dipping for a second, the mask oxide film 113 is removed as shown in FIG. 2(d). Note that this hydrochloric acid aqueous solution treatment also serves to remove a damaged layer formed on the surface of the polysilicon layer 111 during plasma etching.

Next, as shown in FIG. 1E, a capacitor dielectric film 321 is formed on the uneven surface of the polysilicon layer 111, and a plate electrode of the capacitor is further formed using third polysilicon 323 on top of the capacitor dielectric film 321. , complete the capacitor.

[0028]

[Embodiment 2] A second embodiment of the present invention will be described below with reference to FIG.

FIG. 2(a) is a cross-sectional view of a DRAM having an LDD transistor structure in which an insulating film is formed on the gate wiring and a contact hole for forming a capacitor is opened. Here, 201 is a silicon substrate,
203 is a field oxide film of 6000 Å, 205 is a gate oxide film of 200 Å, 207 is a gate electrode (first polysilicon) in which phosphorus is diffused in polysilicon, 4000 Å, and 209 is a side wall (PSG: Phospho Silic).
ate glass) 3000 Å, 211 is an interlayer insulating film (NSG: non-doped-silicate
lass) 2000 Å.

Next, as shown in FIG. 2(b), the second polysilicon 213 is heated at about 600° C. for 2000° C. using the LPCVD method.
After forming Å and performing phosphorus diffusion, this polysilicon 2
The surface of 13 was heated in a furnace, RTO (rapid th
The material is oxidized to a thickness of several tens of angstroms by the oxidation method or by immersion in a mixed solution of hydrochloric acid and hydrogen peroxide.

Next, on the second polysilicon 213 whose surface has been thinly oxidized, TEOS (tetraethylorthosilicon) of O3 and organic silane is applied by CVD.
cate) at about 400° C. to form SiO2 clusters 215 as shown in FIG. 2(c). Here, in order to form the cluster 215, O3 gas needs to be sufficiently supplied to TEOS, and in this case, the O3 gas has a flow rate ratio of about 10 to TEOS.
It's double.

Next, as shown in FIG. 2(d), hydrofluoric acid (
The size of the cluster 215 is adjusted by immersing it in a solution (concentration 1%) for about 10 seconds to optimize the area of the second polysilicon 213 exposed on the surface.

Next, as shown in FIG. 2(e), SiO2
After etching the second polysilicon 213 by about 500 Å by wet etching or dry etching with high selectivity, the clusters 215 are removed using a hydrofluoric acid aqueous solution (1% concentration).

Next, as shown in FIG. 2F, a dielectric film 217 is formed on the uneven surface of the polysilicon 213, and a plate electrode of the capacitor is formed on the dielectric film 217 using a third polysilicon 219, thereby forming a capacitor. form.

In this example, TEOS was used, but
OMCTS (octomethyl
Cyclo tetrasiloxane: Si4
C8H24O4) was used in the same process and showed similar characteristics.

[0036]

[Embodiment 3] A third embodiment of the present invention will be described below with reference to FIG.

In FIG. 3(a), 301 is a Si substrate;
303 is a field oxide film, 305 is a first polysilicon (word line), and 307 is an interlayer insulating film. On such a lower structure, a silicon nitride film Si3 with a film thickness of 300 Å is deposited.
N4309 is formed by CVD method, and a film thickness of 2 is applied on top of it.
A silicon oxide film SiO2 311 with a thickness of 000 Å is formed by the CVD method.

Next, etching is performed using a parallel plate type plasma processing apparatus. The plasma generation conditions at this time were: pressure 133 Pa, CF4: 40 sccm, CHF3 = 8
The etching time was 0 sccm, the high frequency power was 750 W, and the etching time was 15 seconds. When the silicon oxide film 311 is etched under these conditions, due to the masking effect of the attached polymer explained with reference to FIG. is formed.

Next, a photoresist of about 1000 Å is applied, cell contacts are patterned using a reduction projection exposure device, and using this as a mask, the silicon oxide film 311 and the silicon nitride film 309 are dry etched. This etching was carried out using a parallel plate type plasma processing apparatus at a pressure of 133 Pa, CF4: 70 sccm, CHF3:
It is carried out for 1 minute under the conditions of 50 sccm and high frequency of 650 W. After etching the cell contact, the photoresist is removed with oxygen plasma, and then polysilicon is deposited to a thickness of 1500 Å using the CVD method, thereby forming a second polysilicon 315 with an uneven surface as shown in FIG. 3(c). is formed.

Next, apply photoresist to a thickness of approximately 10,000 Å.
A charge storage electrode is patterned using a reduction projection exposure device, and the second polysilicon 315 is etched using this as a mask. This etching was performed using a magnetic field microwave etcher at a pressure of 1.3 Pa and Cl2
: 100sccm, microwave power: 200mA, R
F power: Perform for 1 minute under the condition of 20W. After etching, the resist was removed with oxygen plasma, and SiO2
After removing the film 311, it was further soaked in phosphoric acid heated to 170°C.
By dipping for 0 minutes, the Si3 N4 film 309 is removed and a structure as shown in FIG. 3(d) is formed.

Next, as shown in FIG. 3E, a capacitor is completed by forming a capacitor dielectric film 317 and a third polysilicon (cell plate electrode) 319 by CVD.

[0042]

[Embodiment 4] A fourth embodiment of the present invention will be described below with reference to FIG.

After selectively forming a field oxide film 403 on a P-type silicon substrate 401 by the LOCOS method,
A gate oxide film 405 is formed with a thickness of 300 Å, and a polysilicon film of 2500 Å is formed on it to form a gate electrode 407.
Form. Thereafter, phosphorus is doped using POCl3 as a diffusion source, and gate photolithography and etching are performed to form a gate electrode (first polysilicon) 407.

Next, using the gate electrode 407 as a mask,
By ion-implanting arsenic 75As+ at an acceleration energy of 40 KeV and a dose of 5 x 1015 inos/cm2, the source 409 and drain 41
1, a silicon oxide film 413 with a film thickness of 3000 Å,
A silicon nitride film 415 and a silicon oxide film 417 having a film thickness of 100 Å are sequentially formed by CVD. After that, L.P.C.
When a silicon film with a thickness of 1000 Å is formed using silane (SiH4) gas by the VD method at approximately 570°C (the transition temperature at which silicon changes from an amorphous state to polysilicon), the surface becomes uneven as shown in Figure 4(a). A silicon film 419 is formed.

Next, when the silicon film 419 is removed by etching under the condition that the etching ratio of the silicon film to the silicon oxide film is 1:1, the silicon film 419 is removed on the surface of the silicon oxide film 417, as shown in FIG. The unevenness is transferred.

Next, after photolithography and etching are performed to form a cell contact 421, the LPCVD method is used to form a cell contact 421.
Using silane (SiH4) gas, the second polysilicon 423, which will become the charge storage electrode, is heated to a thickness of 1500 Å at approximately 570°C.
After forming a thick layer and doping with phosphorus using POCl3 as a diffusion source, photolithography and etching were performed to form the structure shown in FIG.
A structure as shown in c) is formed.

Next, the silicon oxide film 417 was removed by immersing it in a hydrofluoric acid aqueous solution (concentration 5%) for 10 minutes.
A second polysilicon 423 as shown in FIG. 4(d) is formed.

Next, as shown in FIG. 4(e), a dielectric film 425 is formed on the surface of the second polysilicon 423, and a plate electrode is formed on the third polysilicon 427 to form a capacitor. Finalize.

[0049]

[Embodiment 5] A fifth embodiment of the present invention will be described below with reference to FIG.

In FIG. 5(a), 501 is a Si substrate;
503 is a field oxide film, 505 is an impurity diffusion layer, 5
07 is a first polysilicon (word line), 509 is an interlayer insulating film, 511 is a silicon nitride film, and 513 is a switching transistor. The thickness of the stripper silicon nitride film is about 500 Å.

A polysilicon film 515 for a charge storage electrode of a capacitor is deposited to a thickness of about 1500 Å on the base structure. Next, as shown in FIG. 5B, a charge accumulation electrode pattern 517 is formed using photoresist, and using this as a mask, the polysilicon film 515 is etched using a magnetic field microwave etching apparatus. The plasma generation conditions at this time were: pressure 0.7 Pa, SF6: 7 sccm
, C2 Cl2 F4 : 63 sccm, microwave power: 190 mA, high frequency power: 70 W, and etching time is about 30 seconds. After etching, the photoresist 517 is removed using oxygen plasma, etc., as shown in FIG. 1(c).
A second polysilicon 519 as a charge storage electrode is formed as shown in FIG. Next, as shown in FIG. 1(d), an oxide film 521 is formed to a thickness of about 1000 Å using the CVD method. Then, the oxide film 521 is etched using a parallel plate plasma processing apparatus. The plasma generation conditions at this time are pressure 133
Pa, CF4: 40sccm, CHF3: 80sc
cm, the high frequency power was 750 W, and the etching time was about 15 seconds. When the oxide film 521 is etched under these conditions, the oxide film 521 partially remains on the second polysilicon 519 and the silicon nitride film 511 (as shown in FIG. etched).

Thereafter, using this partially remaining oxide film as a mask, a second polysilicon layer 5 is formed as shown in FIG. 1(f).
Etch the surface of No. 19. This second polysilicon 5
19 Etching was performed using a parallel plate plasma processing apparatus.
Pressure 20PaSF6: 20sccm, C2 ClF5
:20sccm, high frequency power: 15 under the conditions of 90W
Do it for seconds. By this etching, a portion of the second polysilicon 519 not covered by the mask of the oxide film 521 is removed by about 500 Å. As a result, the second polysilicon 521
The surface has countless minute irregularities. Note that the etching conditions for polysilicon are not necessarily limited to the above conditions as long as polysilicon can be etched anisotropically and the etch rate ratio of polysilicon to silicon nitride film is 2 or more. do not have. Next, the mask oxide film 521 is removed as shown in FIG. 1(g) by immersing the structure shown in FIG. 1(f) on which the polysilicon etching has been completed in a hydrochloric acid aqueous solution (5% concentration) for 30 seconds. Next 170
Figure 1 by immersion in phosphoric acid heated to ℃ for 20 minutes.
As shown in (h), the silicon nitride film 511 is removed.

Next, although not shown, the second polysilicon 51
A capacitor is completed by forming a capacitor dielectric film on the surface of the capacitor 9, and further forming a capacitor plate electrode using third polysilicon thereon.

[0054]

[Embodiment 6] A sixth embodiment of the present invention will be described below with reference to FIG.

In FIG. 6, 601 is a Si substrate, 603
605 is a field oxide film, 605 is a first polysilicon (word line), 607 is an interlayer insulating film, 609 is a second polysilicon which is a charge storage electrode, 611 is a dielectric film, and 613 is a third polysilicon which is a plate electrode. be.

The capacitor shown in FIG. 6 can be formed according to the third embodiment described above.

In this case, by providing an uneven portion on the surface of the charge storage electrode 609, a capacitor with a large charge storage amount Cs can be obtained.

[0058]

[Embodiment 7] A seventh embodiment of the present invention will be described below with reference to FIG.

In FIG. 7, 701 is a Si substrate, 703
is a field oxide film, 705 is a first polysilicon (word line), 707 is an interlayer insulating film, 709 is a second polysilicon that is a charge storage electrode, 711 is a dielectric film, and 713 is a third polysilicon that is a plate electrode. be.

The capacitor shown in FIG. 7 can be formed according to the fourth embodiment described above.

In this case, the charge storage electrode 7 inside the opening
Since the uneven portion is also formed on the surface of 09, a capacitor having a larger charge storage amount Cs is obtained.

[0062]

Effects of the Invention As described in detail above, according to the present invention, despite the reduction in memory cell dimensions due to higher integration, the surface of the charge storage electrode is made uneven. Then, by forming an uneven shape also on the surface of the charge storage electrode facing the interlayer insulating film, a semiconductor memory device having a capacitor with a large amount of charge storage can be obtained.

Furthermore, the present invention not only makes it possible to effectively form a capacitor having an uneven shape on the surface of the charge storage electrode, but also reduces the difference in level between the capacitor part and other parts, making it easier to form patterns in subsequent steps. It also has the effect of not having any effect.

Furthermore, by forming an uneven shape on the surface of the charge storage electrode after patterning the charge storage electrode, a capacitor with good pattern characteristics can be formed.

[Brief explanation of the drawing]

FIG. 1: Process diagram of the first embodiment of the present invention

[Fig. 2] Process diagram of the second embodiment of the present invention

[Fig. 3] Process diagram of the third embodiment of the present invention

[Fig. 4] Process diagram of the fourth embodiment of the present invention

[Figure 5
] Process diagram of the fifth embodiment of the present invention

FIG. 6: Sixth aspect of the present invention
Configuration diagram of an example of

FIG. 7 is a configuration diagram of a seventh embodiment of the present invention

FIG. 8 is a process diagram illustrating the principle of forming an oxide film mask according to the first embodiment of the present invention and the third embodiment of the present invention;

[
Figure 9: Configuration diagram of conventional stacked capacitor cell

[
Figure 10: Process diagram showing a conventional capacitor manufacturing method

[Explanation of symbols]

101 Si substrate 103 Field oxide film 105 First polysilicon 107 Interlayer insulating film 109 Switching transistor 111
Second polysilicon 113 oxide film

Claims (6)

[Claims] 1. A method for manufacturing a semiconductor memory device having a charge storage electrode, comprising: forming an oxide film on the charge storage electrode; selectively etching the oxide film to form an oxide mask; A method for manufacturing a semiconductor memory device, comprising the step of etching the surface of the charge storage electrode using the oxide mask to form an uneven portion. 2. In the step of selectively etching the oxide film to form an oxide mask, the oxide mask is formed by selectively etching using a fluoro-hydro polymer formed on the surface of the oxide film as a mask. 2. The method of manufacturing a semiconductor memory device according to claim 1. 3. The step of selectively etching the oxide film to form an oxide mask is performed by selectively etching the silicon oxide film clusters formed on the surface of the oxide film as a mask in an O3 and organic silane atmosphere. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the oxidation mask is formed by etching. 4. A method for manufacturing a semiconductor memory device in which an interlayer insulating film is formed on a substrate, comprising: forming an oxide film on the interlayer insulating film; and forming a first uneven portion on the surface of the oxide film. and forming a charge storage electrode having a second uneven portion on its surface according to the shape of the first uneven portion. 5. A method for manufacturing a semiconductor memory device in which an interlayer insulating film is formed on a substrate, comprising: forming an oxide film on the interlayer insulating film; and forming a first uneven portion on the surface of the oxide film. forming an exposed portion on a portion of the substrate; and forming a second surface on the exposed portion and the first uneven portion.
1. A method of manufacturing a semiconductor memory device, comprising: forming a charge storage electrode having an uneven portion. 6. A substrate having an exposed portion formation region and an interlayer insulating film formation region, an interlayer insulation film formed in the interlayer insulation film formation region, and an exposed portion formed on the exposed portion formation region. a first electrode having an uneven surface connected to the interlayer insulating film and extending over the interlayer insulating film; a dielectric film formed on the surface of the first electrode; and a dielectric film formed on the dielectric film and the interlayer insulating film. A semiconductor memory device characterized by having a second electrode formed to extend.