JPH04218920A - Semiconductor device provided with multilayer wiring structure and its manufacture - Google Patents

Abstract

PURPOSE:To improve initial characteristics and reliability of multilayer wiring structure by electrically connecting wiring layers which are laminated with a layer insulating film interposed at a connection part which is formed by plating. CONSTITUTION:A conductive foundation layer 12 is deposited on a surface side of a semiconductor substrate 11a and a first Au wiring layer 13 is formed by plating on a surface thereof. Then, an Au layer 15 for connection is formed by plating on a surface of the first Au wiring layer 13 and superposed. After the conductive foundation layer 12 is dry-etched using the first Au wiring layer 13 as a mask, an insulating film is deposited flat on an upper surface and a surface thereof is etched back to expose an upper part of the connection Au layer 15. A second Au wiring layer 17 is formed by plating on a surface thereof by a similar method as a formation process of the first Au wiring layer 13. Thereby, the second Au wiring layer 17 is electrically connected to the first wiring layer 13 through the connection Au layer 15.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same, and more particularly to connection technology between wiring layers.

0002

[Prior Art] Generally, in wiring technology for semiconductor devices, a number of wiring layers are stacked with an interlayer insulating film interposed between the wiring layers, and these wiring layers are formed on the interlayer insulating film. A structure is adopted in which electrical connection is made to a lower wiring layer through a contact hole, and the wiring structure is an important element that determines the characteristics and reliability of a semiconductor device.

[0003] Such a multilayer wiring structure will be explained with reference to FIG. 9, which is a process cutaway diagram of a conventional semiconductor device.

In FIG. 9A, a semiconductor region 71a and an insulating layer 71b are formed on the surface side of a semiconductor substrate 71, and the surface of the semiconductor region 71a is deposited by sputtering and then patterned. The first wiring layer 7
2 is formed. In order to form multilayer wiring on the semiconductor substrate 71 having this structure, first, as shown in FIG. 9(b),
An interlayer insulating film 73 is deposited above the first wiring layer 72,
Next, as shown in FIG. 9C, a connection hole 74 for connecting the first wiring layer 72 and the wiring layer to be formed on the surface side of the interlayer insulating film 73 is opened. A metal material is deposited on the surface side of the semiconductor substrate 71 in this state by sputtering to form a metal layer on the surface of the interlayer insulating film 73 and fill the connection hole 74. After that, Figure 9
As shown in (d), the metal layer is patterned,
A second wiring layer 75 is formed.

[0005] Thereby, the first wiring layer 72 and the second wiring layer 75 are electrically connected through the connection hole 74 of the interlayer insulating film 73.

[0006]

As described above, in the conventional semiconductor device manufacturing method, the connection hole 74 of the interlayer insulating film 73 is filled from above the semiconductor substrate 71 by the sputtering method. Layer 75 and first wiring layer 7
The coverage with 2 is greatly influenced by the shape of the lower layer. For example, metal material attached around the opening of the connection hole 74 prevents the metal material from being deposited on the lower side.
If a void occurs in the corner 74a of the bottom surface of the connection hole 74, or because metal material is difficult to deposit on the inner peripheral side of the connection hole 74, a thin portion will occur in the second wiring layer 75 inside the connection hole 74. There are cases. Such poor coverage is undesirable because it may cause initial disconnection or disconnection over time due to electromigration or the like.

[0007] As a method to solve such problems,
A method using the plated wiring layer shown in FIG. 10 is devised. In FIG. 10, on the surface side of a semiconductor substrate 81, a conductive base layer 83 is deposited on the surface of an interlayer insulating film 82 and the inner surface of its connection hole 82a. Here, a plating process is performed using the conductive base layer 83 as a plating electrode to deposit the second wiring layer 84 and fill the inside of the connection hole 82a. Therefore, since the metal layer can be reliably grown from the surface of the conductive underlayer 83, the above-mentioned coverage is improved. However, in this method, since the conductive base layer 83 is also present on the side surface of the connection hole 82a, if the aspect ratio of the connection hole 82a is high, the second layer grown near the opening 82b of the connection hole 82a may wiring layer 8
4, the opening is closed, leaving a void 84b inside. This causes problems such as increased wiring resistance inside the connection hole 82a and disconnection due to electromigration, so there is a limit to the range to which a wiring structure using plating can be applied. In particular, as elements become smaller and the lateral size of semiconductor devices is further reduced, the aspect ratio of contact holes becomes even higher.
The above problems become even more noticeable.

[0008] In view of the above problems, an object of the present invention is to improve the initial characteristics and reliability by forming the connection part for electrically connecting the wiring layers only from the surface of the lower wiring layer. An object of the present invention is to provide a semiconductor device including multilayer wiring layers.

[0009]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the measures taken in a semiconductor device having a multilayer wiring structure according to the present invention are as follows: a base layer, a first wiring layer deposited on the surface of the base layer and electrically connected to the lower layer via the conductive base layer, a connection metal layer stacked and formed on the surface of the first wiring layer, An interlayer insulating film is deposited on the surface side of the first wiring layer and buries the connection metal layer with its upper surface exposed; It is characterized by having at least a second wiring layer for electrical connection.

A method for manufacturing a semiconductor device having this structure includes a base layer forming step of depositing a conductive base layer on the surface side of the semiconductor substrate, and a first step of depositing a conductive base layer on the surface of the conductive base layer in a wiring pattern area.
a first wiring layer forming step in which a wiring layer is deposited;
a connecting metal layer forming step of plating a connecting metal layer on the surface of the first wiring layer in the window opening of this mask; and a mask removing step of removing this mask. and a base layer removal step of removing the conductive base layer in the inverted region of the wiring pattern of the first wiring layer;
an insulating film forming step of depositing an interlayer insulating film on the surface side of the first wiring layer to bury the connection metal layer so that at least the upper surface thereof is exposed; and then a step of forming a second wiring layer above them. The method is characterized in that it has two wiring layer forming steps.

In the present invention, when using a layer formed by plating on the surface of a conductive base layer as the first wiring layer, the first wiring layer to be formed is A process of covering the surface of the conductive base layer with a mask having a window opening in the wiring pattern area of the layer, and a plating process of plating a first wiring layer on the surface of the conductive base layer in the window opening, and forming the mask. In the removal process, this mask is also removed. In this case, the first wiring layer is formed so that its side surfaces are tapered so that its bottom surface has a larger area than its top surface, and the interlayer insulating film is deposited in close contact with the side surfaces. Therefore, it is preferable to use a negative photoresist as a mask for forming the first wiring layer.

[0012] Further, as an insulating film forming step, for example,
After an insulating film is deposited above the first wiring layer to cover the top surface of the connection metal layer, an etch-back process is performed until at least the surface of the connection metal layer is exposed. In order to ensure a wide contact area between the metal layer and the second wiring layer, it is preferable to perform the etch-back process to the extent that the upper part of the connection metal layer protrudes from the surface of the interlayer insulating film.

Further, as the base layer removal step, for example, dry etching is performed using the first wiring layer as a mask without forming a new mask. Here, in order to deposit the interlayer insulating film in close contact with the first wiring layer, it is desirable that the outer peripheral side of the upper surface of the connecting metal layer and the outer peripheral side of the upper surface of the first wiring layer be curved. Preferably, the etching also shallowly etches the upper surface of the connection metal layer and the upper surface of the first wiring layer.

In the present invention, for example, Au, Ag or Cu can be used for the first wiring layer, the connection metal layer and the second wiring layer.

Then, Ti or Mo is deposited as the bottom layer so that the conductive underlayer is in close contact with both the lower layer side and the upper layer side, and the same type of metal as the first wiring layer or Pt is deposited.
is preferably deposited as the top layer.

[0016]

[Function] In the present invention having the above structure, a conductive base layer is previously deposited on the surface side of the semiconductor substrate in the base layer forming step, and a conductive base layer is coated on the surface of the conductive base layer by plating or the like. 1 wiring layer is formed. Here, the conductive base layer is left in place, and after covering the surface of the first wiring layer with a mask with an opening in the region where the connection metal layer is to be formed, the semiconductor substrate is plated using the conductive base layer. Then, a connection metal layer is formed in the window opening. After forming the connection metal layer, the conductive base layer in the inverted region of the wiring pattern of the first wiring layer is removed. In this state, the connection metal layer is filled with an interlayer insulating film with the top surface of the connection metal layer exposed. After that, when a second wiring layer is formed by repeating the above steps or using a sputtering method, the second wiring layer is connected to the connection metal layer exposed from the interlayer insulating film, and this connection metal layer is connected to the connection metal layer exposed from the interlayer insulating film. It is electrically connected to the first wiring layer through the layer. In this way, since the connection metal layer is formed by plating from the surface of the first wiring layer before forming the interlayer insulating film, there is no need to fill the connection holes in the interlayer insulating film as in the conventional method. Therefore, the adhesion between the connection metal layer and the first wiring layer is high,
Even when a thick connection metal layer is applied, no voids remain inside. Therefore, it is possible to realize a wiring structure that has low wiring resistance and can prevent electromigration, and improves the initial characteristics and reliability of the semiconductor device.

[0017]

Embodiment Next, a wiring structure of a semiconductor device according to an embodiment of the present invention will be explained with reference to FIG.

FIG. 1 is a cutaway view of a semiconductor device according to this example. In a semiconductor device 11, a semiconductor region 11b is formed on the surface side of a silicon substrate 11a;
In the region where b is not formed, a silicon oxide film 11c is formed.
is covered. A conductive base layer 12 consisting of a lower Ti layer 12a with a thickness of approximately 10 nm and an upper Au layer 12b with a thickness of approximately 100 nm is deposited on the surface side of the silicon substrate 11a having this configuration, and its conductivity A first Au wiring layer 13 having a thickness of approximately 700 nm is plated on the surface of the base layer 12, and the first Au wiring layer 13 is electrically connected to the semiconductor region 11b via the conductive base layer 12. Connected. An interlayer insulating film 14 is deposited above the interlayer insulating film 14, and a first Au wiring layer 1 is formed inside the contact hole 14a.
It has a connection Au layer 15 (connection metal layer) formed by plating from the surface of 3. Here, the connection hole 14a is not formed in the interlayer insulating film 14, but is formed by depositing the interlayer insulating film 14 so as to fill the connecting Au layer 15 stacked on the first Au wiring layer 13. It is what was done. The connection Au layer 15 is in a state of protruding from the surface of the interlayer insulating film 14. Above this, like the first wiring layer, a conductive base layer 16 consisting of a lower Ti layer 16a with a thickness of about 10 nm and an upper Au layer 16b with a thickness of about 100 nm is provided for connection. It has a second Au wiring layer 17 electrically connected to the Au layer 15. Thereby, the second Au wiring layer 17 and the first Au wiring layer 13 form a multilayer wiring structure in which they are electrically connected via the interlayer insulating film 14. Furthermore, a surface insulating film 18 is deposited above the second Au wiring layer 17.

Next, a method for manufacturing the semiconductor device 11 having this configuration will be explained with reference to FIGS. 1 to 5.

2 to 5 are process cross-sectional views of the semiconductor device of this example. In FIG. 2(a), the silicon substrate 11a is in a state before the wiring layer is formed, and a semiconductor layer is formed on the surface side of the silicon substrate 11a. A region 11b and a silicon oxide film 11c are formed.

First, as shown in FIG. 2(b), a T layer with a thickness of about 10 nm is applied to the entire surface of the silicon substrate 11 in this state.
The i layer 12a is deposited by sputtering, and the Ti layer 1
An Au layer 12b having a thickness of about 100 nm is deposited on the surface of 2a to form a conductive base layer 12 (base layer forming step).

Next, as a step of forming a mask for the wiring layer, as shown in FIG. 3(a), the surface of the conductive base layer 12 is covered with a positive photoresist layer 19 having a thickness of approximately 1 μm. After that, a window opening 19a corresponding to the wiring pattern area of the first wiring layer is formed. After that, as a process for forming a wiring layer, the silicon substrate 11 is immersed in an Au plating bath, plating is performed using the conductive base layer 12 as a power supply electrode, and a window is opened as shown in FIG. 3(b). An Au film is grown from the surface of the conductive base layer 12 in the portion 19a,
A first Au wiring layer 13 having a thickness of about 700 nm is formed inside the window opening 19a (first wiring layer forming step).

Furthermore, as shown in FIG. 3(c), after covering the upper part of the silicon substrate 11a with a positive photoresist layer 20 having a thickness of about 1 μm, a second photoresist layer 20 is formed above this.
A window opening 20a is formed in a region where a connecting metal layer for connecting the wiring layer and the first Au wiring layer 13 is to be formed. Here, the photoresist material is removed sufficiently so that it does not remain inside the window opening 20a (mask forming step).
.

Next, the silicon substrate 11a is immersed in the Au plating bath again, and plating is performed using the conductive base layer 12 as a power supply electrode, so that the window opening 20 is formed as shown in FIG. 4(a).
On the surface of the first Au wiring layer 13 of
forming a connection Au layer 15 (connection metal layer forming process)
.

Next, as shown in FIG. 4(b), the photoresist layers 19 and 20 formed on the silicon substrate 11a are removed. As a result, the connection Au layer 15 is stacked on the first Au wiring layer 13 (mask removal step).

Next, as shown in FIG. 4(c), the silicon substrate 11a is dry etched in a mixed gas of CF4 and O2. Here, the first Au wiring layer 13 is used as a mask for dry etching, and the first Au wiring layer 13 is used as a mask for dry etching.
Conductive base layer 12 in areas where wiring layer 13 is not deposited
Then, the surface layer of the silicon oxide film 11c is removed. (Underlying layer removal step) After that, as shown in FIG. 5(a), a silicon oxide film 14b with a thickness of approximately 1.5 μm is deposited above the silicon substrate 11 by plasma CVD, and a resist is further applied to the surface of the silicon oxide film 14b. A layer 21 is applied to planarize the surface. In this state, the silicon oxide film 14b and the resist layer 21 are etched from the surface by plasma etching. Here, by setting the plasma etching conditions so that the etching rates for the silicon oxide film 14b and the resist layer 21 are the same (etchback method), the silicon oxide film 14b is etched as shown in FIG. 5(b). , are left as a flat interlayer insulating film 14. Here, in the plasma etching, the upper part 15a of the connection Au layer 15 is
This process is continued until it protrudes from the surface of the interlayer insulating film 14 (insulating film forming step).

Thereafter, as a second wiring layer forming step, the same steps as those from the base layer forming step to the first Au wiring layer forming step described above are repeated to form a second wiring layer.

First, a Ti layer 16a having a thickness of about 10 nm is deposited on the surface side of the interlayer insulating film 14 by sputtering.
Further, an Au layer 16b having a thickness of about 100 nm is deposited on the surface of the Ti layer 16a to form a conductive underlayer 16. Furthermore, after covering this surface with a positive photoresist layer 22 having a thickness of about 1 μm, as shown in FIG. 5(c),
Window opening 2 corresponding to the wiring pattern area of the second wiring layer
Form 2a. Next, the silicon substrate 11a is immersed in an Au plating bath, and plating is performed using the second conductive base layer 16 as a power supply electrode. is grown to form a second Au wiring layer 17 with a thickness of 700 nm inside the window opening 22a. Next, the photoresist layer 22 is removed, and the silicon substrate 11 is dry etched in a mixed gas of CF4 and O2. Here, the second Au wiring layer 17 serves as a mask for dry etching, and the second
The surface of the second conductive base layer 16 and the interlayer insulating film 14 in the area where the Au wiring layer 17 is not deposited is removed.

Thereafter, a surface insulating film 18 is deposited to form the multilayer wiring of the semiconductor device 11 shown in FIG. 1 (second wiring layer forming step).

As described above, in this example, the conductive base layer 12 formed in advance is left after the first Au wiring layer 13 is formed, and this is used as a power supply electrode for plating. , the connection Au layer 15 is grown only from the surface of the first Au wiring layer 13 , and then the connection Au layer 15 is filled with the interlayer insulating film 14 . Therefore, connection A
Even if the u layer 15 is thick, the connection Au layer 15 is
It has high adhesion to the first Au wiring layer 14 and has no voids inside. Moreover, since the connecting Au layer 16 protrudes from the surface of the interlayer insulating film 17a toward the second Au wiring layer 18, the contact area with the second Au wiring layer 17 is wide and the connection can be made in close contact with the second Au wiring layer 17. There is. Therefore, in the wiring structure of this example, the wiring resistance is initially low and electromigration does not occur over time. Therefore, initial characteristics and reliability are good, and restrictions on the thickness of the interlayer insulating film can be relaxed in designing and manufacturing a semiconductor device.

[0031] Furthermore, the first Au wiring layer 13, the second Au
The wiring layer 17 includes a Ti layer 12a with high adhesion to the oxide film between the lower silicon oxide film 11b and the surface insulating film 18.
and an upper layer made of the same Au as the wiring layer, the adhesion between them is also high. Furthermore, the first Au wiring layer 13, the connection Au layer 15, the second
Since the Au wiring layer 17 is made of Au, the wiring resistance is low and corrosion and disconnection due to impurities are less likely to occur.

[0032] Before the second wiring layer forming step, by repeating the base layer forming step to the insulating film forming step,
It is also possible to form a wiring structure of three or more layers with good initial characteristics and reliability.

In this example, a multilayer wiring structure was formed using a plated wiring layer, but instead of the second Au wiring layer 17, an Au layer deposited by sputtering was used to form the second Au wiring layer 17.
A wiring layer may be formed. A cutaway view of a semiconductor device manufactured by this method is shown in FIG. In the figure, the second Au wiring layer 32 of the semiconductor device 31 is connected to the connecting Au layer 3.
3, and is directly connected to the upper part 33a of the connecting Au layer 3.
It is electrically connected to the first Au interconnection layer 34 via 3.

Also in the semiconductor device 31 having this structure, the interlayer insulating film 35 is formed in such a state that the upper part 33a of the connection Au layer 33 protrudes, and in this state, the second Au wiring layer 32
is deposited by sputtering. Therefore, unlike the conventional manufacturing method, there is no need to fill the inside of the contact hole 35a, so if the interlayer insulating film 35 is thick, even if the second wiring layer is deposited by sputtering, the wiring structure will be Good initial characteristics and reliability.

In this example, the conductive underlayer is removed by
Although dry etching in a mixed gas of CF4 and O2 gas is used, it may also be performed in a single gas of CF4, or an ion milling method in an inert gas such as Ar gas may be used. Here, together with the conductive underlayer,
Also for the top surface of the Au wiring layer and the top surface of the connection Au layer,
Conditions may be set to allow shallow etching. In this case, as shown in FIG. 7, corner portions 41a and 42a on the outer circumferential side of the upper surface of the first Au wiring layer 41 and the connecting Au layer 42 are etched to form curved surfaces. Therefore, silicon substrate 1
Even if the silicon oxide film 43 is deposited from above 1a, the corner portions 41 of the first Au wiring layer 41 and the connection Au layer 42
a, 42a, and can be deposited on side surfaces 41b, 42b without gaps.

Furthermore, a negative photoresist may be used instead of a positive photoresist for the photoresist layer for forming the plating wiring layer. In the positive photoresist after opening the window, as shown in FIG.
The bottom surface 52a of the resist layer 52 becomes wider perpendicular to the angle a or as shown in FIG. 8(b). On the contrary,
When using a negative photoresist, when exposed to light,
The surface side of the resist is exposed more strongly than the inside, so
As shown in FIG. 8(c), the side surfaces 53 are arranged such that the upper surface 53a of the resist layer 53 has a larger area than the bottom surface 53b.
A taper occurs at 3c. In this state, when the window opening portion 53d is embedded from above, the window opening portion 53d
The corner 53e of the bottom surface of d is in the shadow of the top surface 53a of the resist 53, resulting in a portion that is not embedded. However, when forming the wiring layer by plating, the wiring layer is grown upward from the bottom layer. Therefore, Fig. 8(c)
Even if the resist 53 is formed in the shape of
The corner 53e of can also be embedded. For this reason,
As shown in FIG. 8D, the formed wiring layer 54 has a tapered side surface 54c such that the top surface 54a has a smaller area than the bottom surface 54b. In this case, when the interlayer insulating film is deposited from above, the upper surface 54a
Since the lower part is not obstructed because the side surface 5 of the wiring layer 54 is narrow,
Since the interlayer insulating film can be reliably applied to 4c, a more reliable wiring structure can be realized.

In this example, T is used as the conductive underlayer.
Although a two-layer structure consisting of an i-layer and an Au layer was adopted, the present invention is not limited to this, and any conductive material that can be used as a power supply electrode in a plating process may be used. Here, in order to improve the adhesion between the conductive underlayer and the lower and upper layers, a Ti layer is used as a material with high adhesion to the oxide film for the lower layer that is directly deposited on the surface of the oxide film. In addition, a Mo layer may be used as the upper layer on which the plated wiring layer is deposited, and a Pt layer may be used in addition to the metal layer of the same type as the wiring layer as a material with high adhesion to the plated wiring layer. is made of Ti or Mo, and the middle layer is made of Pt.
The upper layer may be formed of the same type of metal as the wiring layer. Note that, in addition to Au, Ag or Cu can also be used as the wiring layer.

[0038] To form the interlayer insulating film, a silicon oxide film and a resist layer were deposited and an etch-back process was performed, but any material that can flatten the substrate surface may be used.
For example, a phosphorus glass layer or a boron-phosphorus glass layer may be used as a single layer, or in combination with silicon oxide, silicon nitride, silicon oxynitride, or a multilayer film thereof as an insulating film.

Furthermore, the formation of the plating layer is not limited to electroplating using current waveforms such as DC, pulse, and PR, but may also utilize electroless plating or a combination of electroplating and electroless plating.

Note that in this example, the first
Although a plating-formed connection Au layer (connection metal layer) was used to connect the first layer and the second wiring layer, the present invention is not limited to this.
The connection metal layer should be placed in an optimal position depending on the function of the semiconductor device to be manufactured, and should be combined with a conventional wiring structure to form a multilayer wiring structure. Good too.

[0041]

As described above, in the present invention, a conductive base layer is deposited on the surface side of a semiconductor substrate, a first wiring layer is formed on the surface of this conductive base layer, and a conductive base layer is formed on the surface of the conductive base layer. The method is characterized in that the interlayer insulating film is formed after plating and stacking the connection metal layer on the surface of the first wiring layer using a base layer, so that the following effects are achieved. .

(2) Since the connection metal layer is formed by plating, it grows only from the surface of the first wiring layer. Moreover, since the connection metal layer is formed before forming the interlayer insulating film,
The thickness of the interlayer insulating film does not affect the formation of the connection metal layer. Therefore, the connection metal layer has high adhesion to the first wiring layer and does not have voids or the like inside. Therefore, even in the case of having a thick interlayer insulating film, it is possible to realize a multilayer wiring structure with low wiring resistance in terms of initial characteristics and high reliability over time.

■ If the upper part of the connection metal layer protrudes from the surface of the interlayer insulating film, a large contact area between the connection metal layer and the second wiring layer can be ensured, resulting in low connection resistance and stable connection. can be realized.

■ When the mask for forming the wiring layer is formed of negative photoresist, the first
The wiring layer is formed so that the bottom surface is wide. In this case, since the upper surface of the first wiring layer does not prevent the interlayer insulating film from being deposited on the side surface of the first wiring layer, the adhesion between the first wiring layer and the interlayer insulating film can also be improved. I can do it.

■ When the conductive base layer has a lower layer made of Ti or Mo and an upper layer made of the same metal as the second wiring layer or Pt, the oxide film on the lower layer side and the upper layer side High adhesion to wiring layers.

[0046] When the base layer removal process is a process of removing the conductive base layer by dry etching using the first wiring layer as a mask, a process of forming a mask for removing the conductive base layer is performed. Can be omitted.

[Brief explanation of the drawing]

FIG. 1 is a cutaway diagram showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process cutaway diagram showing a part of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a process cutaway diagram showing a part of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a process cutaway diagram showing a part of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a process cutaway diagram showing a part of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

6 is a cutaway diagram showing the structure of a semiconductor device in which the second Au wiring layer in the semiconductor device of FIG. 1 is replaced with another wiring layer; FIG.

FIG. 7 is a process cutaway diagram showing part of a method for manufacturing a semiconductor device using conditions different from the conditions of the base layer removal step according to the present example.

FIG. 8 is a process cutaway diagram showing the structure of a photoresist layer in a wiring layer forming process.

FIG. 9 is a process cutaway diagram showing a conventional method for manufacturing a semiconductor device.

FIG. 10 is a process cutaway diagram showing another conventional method for manufacturing a semiconductor device.

[Description of symbols] 11, 31... Semiconductor device 11a... Silicon substrate 12, 16... Conductive base layer 13, 34, 41... First wiring layer 15, 42... For connection Au layer (connection metal layer) 17, 3
2... Second Au wiring layer 14, 35, 43... Interlayer insulating film

Claims (16)

[Claims] 1. A conductive base layer deposited in a wiring pattern area on the front surface side of a semiconductor substrate, and a first wiring layer deposited on the surface of the conductive base layer and electrically connected to the lower layer via the conductive base layer. a connection metal layer stacked on the surface of the first wiring layer by plating; an interlayer insulating film deposited on the surface side of the first wiring layer and filling the connection metal layer with its upper surface exposed; A semiconductor having a multilayer wiring structure, comprising at least a second wiring layer deposited above the interlayer insulating film and electrically connected to the first wiring layer via the connection metal layer. Device. 2. A semiconductor device having a multilayer wiring structure according to claim 1, wherein the first wiring layer is formed by plating on the surface of the conductive base layer. 3. A multilayer wiring structure according to claim 2, wherein the first wiring layer has a tapered side surface so that its bottom surface has a wider area than its top surface. Semiconductor device equipped with 4. A semiconductor device having a multilayer wiring structure according to claim 1, wherein the connection metal layer protrudes from a surface of the interlayer insulating film. 5. The multilayer device according to any one of claims 1 to 4, wherein an outer peripheral side of the upper surface of the connection metal layer and an outer peripheral side of the upper surface of the first wiring layer are curved surfaces. A semiconductor device with a wiring structure. 6. In any one of claims 1 to 5, the first wiring layer, the connection metal layer, and the second wiring layer are selected from the group consisting of Au, Ag, and Cu. 1
A semiconductor device having a multilayer wiring structure characterized by being made of a certain metal. 7. In any one of claims 1 to 6, the conductive base layer includes a lower layer made of one of the metals Ti and Mo, and a metal of the same type as the second wiring layer. and an upper layer made of any one of the following metals: 8. A base layer forming step of depositing a conductive base layer on the surface side of a semiconductor substrate; and a first wiring step of depositing a first wiring layer on a wiring pattern area on the surface of the conductive base layer. a layer forming step, a mask forming step of covering the surface of the first wiring layer with a mask in which a region where a connecting metal layer is to be formed is opened; and a mask forming step of covering the surface of the first wiring layer in the opening of the mask; a connection metal layer forming step of forming the connection metal layer by plating;
a mask removal step of removing this mask; a base layer removal step of removing the conductive base layer in the inverted region of the wiring pattern of the first wiring layer; and a state in which at least the top surface of the connection metal layer is exposed. An insulating film forming step of depositing an interlayer insulating film on the surface side of the first wiring layer to fill the periphery of the connection metal layer, and then a second wiring layer forming step of forming a second wiring layer above it. A method for manufacturing a semiconductor device having a multilayer wiring structure, comprising: 9. In claim 8, the first wiring layer forming step includes the step of covering the surface of the conductive base layer with a mask having a window opening for a wiring pattern area of the first wiring layer to be formed;
a plating step of plating a first wiring layer on the surface of the conductive base layer in the window opening portion, and in the mask removal step, this mask is also removed. A method for manufacturing a semiconductor device comprising: 10. The method of manufacturing a semiconductor device having a multilayer wiring structure according to claim 9, wherein a negative photoresist is used as a mask for forming the first wiring layer. 11. The multilayer wiring structure according to claim 8, wherein the step of removing the base layer is performed by dry etching using the first wiring layer as a mask. A method for manufacturing a semiconductor device. 12. The method of manufacturing a semiconductor device having a multilayer wiring structure according to claim 11, wherein the dry etching also shallowly etches the upper surface of the connection metal layer and the upper surface of the first wiring layer. 13. In any one of claims 8 to 12, the insulating film forming step includes depositing an insulating film above the first wiring layer to cover the top surface of the connection metal layer. A method for manufacturing a semiconductor device having a multilayer wiring structure, characterized in that an etch-back process is subsequently performed until at least the surface of the connection metal layer is exposed. 14. Manufacturing a semiconductor device having a multilayer wiring structure according to claim 13, wherein the etch-back process is performed until an upper part of the connection metal layer protrudes from a surface of the interlayer insulating film. Method. 15. In any one of claims 8 to 14, the first wiring layer, the connection metal layer, and the second wiring layer are selected from the group consisting of Au, Ag, and Cu. A method for manufacturing a semiconductor device having a multilayer wiring structure characterized by being made of one type of metal. 16. In any one of claims 8 to 15, the base layer forming step includes depositing any one of Ti and Mo as the bottom layer;
1. A method for manufacturing a semiconductor device having a multilayer wiring structure, comprising the step of depositing a metal of the same type as the second wiring layer and one of Pt as an uppermost layer.