JPH04215191A - Display apparatus - Google Patents

Abstract

PURPOSE: To make it possible to read texel (texture element) values out of two different levels of a pyramid array of different resolution level by an easy method at the same time in parallel. CONSTITUTION: A texture memory 41 is provided with different texture memory banks which can be addressed in parallel. Further, display devices 30, 32, 34, and 36 are provided with a texel value storage means which can alternately store two-dimensional arrays of values forming sequential levels of pyramid arrays that are already stored in the respective two texture memory banks. Consequently, values supplied to an interpolating means can be read out of the two different levels of the pyramid arrays at the same time without parallelizing the storage space or employing a double structure.

Description

[Detailed description of the invention]

0001

FIELD OF THE INVENTION The present invention relates to a texture element ("texel") representing a two-dimensional (2-D) modulation pattern at at least two distinct resolution levels, distinguishable by each value of a level coordinate, and an associated display memory. a display processor having a texture memory for storing at least one pyramid or partially pyramidal array of values ``);
It further comprises interleaving interpolation means responsive to the fractional portion of the received level coordinates for combining together corresponding texel values from two levels of the stored pyramid array to generate interpolated texel values. The present invention relates to display devices.

[0002] A device of the above-mentioned type is disclosed in International Publication No. WO 85/00913, which synthesizes and displays objects in real time for three-dimensional cases and flight simulations.

[0003] This device implements a technique known as "texture mapping" in which a 2-D pattern ("texture") is pre-generated, stored in a texture memory, and then ,
By having a single elementary element presented (translated from "object space" to "screen space" and scanned into display memory),
Map basic elements to textures. This technique allows a large amount of surface detail to be displayed without appreciably increasing the number of primitives required to generate the image. In the simple case, in order to define the color of the object surface by a stored pattern, the texel values can establish color values that can be written directly into the display memory. In a more general case, the texel values may be further processed or controlled so that, for example, complex lighting effects can be computed quickly. Although texture mapping can be performed entirely in software, the present invention allows the mapping to be performed in hardware in the field of real-time image synthesis. The texel values need to be filtered during mapping to avoid aliasing effects. To simplify the calculation of filter values, a series of
It is customary to store textures in so-called pyramid arrays consisting of 2-D arrays. Regarding the generation and storage of pyramid texture arrays, see “COMP
UTER Graphics, Vol. 17. N
o. 3 (Proc. SIGGRAPH 1983), pages 1 to 11 of Lance Williams' paper ``Pyra
midal parameters”.

0004

Since the object moves away from or towards the viewpoint, interpolation means are provided to prevent the display resolution from changing sharply. However, because the texel values must be read from a two-level array, such an improvement requires twice the number of memory read cycles, unless parallel reading from both arrays is possible. Although the Williams reference suggests a method for making all levels of a given texture pyramid accessible simultaneously, this would require a large number of connections and the equipment would be extremely expensive, thus requiring large quantities for commercial use. It is unsuitable for production. Additionally, conventional methods place arrays in 2-D memory as fixed "MIP maps." There are other solutions to provide a full duplex ported textured memory, but this is not feasible due to the small capacity of the dual ported memory device.

It is an object of the invention to enable parallel readout from two levels of a pyramid array by a simpler and more economical technique than previously considered.

[0006]

The present invention provides a display device as mentioned in the introduction, wherein the texture memory comprises separate first and second parallel addressable texture memory banks; further comprising texel value storage means for storing alternating 2-D arrays of texel values forming successive levels of the stored pyramid array in each of the first and second texture memory banks. do.

In this way, the texel values supplied to the interpolation means can be read out simultaneously from two different levels of the pyramid array without the need for excessive parallelization or dual structure of the storage space. .

The present invention is based on the recognition that it is possible to limit the degree of parallelization and still provide parallel reading by simply dividing the texture memory into two separate single-port banks, regardless of the number of levels in the pyramid array. It is something. All that is required is that adjacent levels of any given pyramid are always stored in different banks.

In a preferred embodiment of the invention, each texture memory bank is divided into at least three parallelly addressed memories, wherein the texel values are stored in an interleaved manner such that the values for a 2-D patch of texels are first and a second texture memory bank, the texel value storage means configured to read in parallel from each of the second texture memory banks, and the interpolation means configured to perform a single 3-D interpolation from a set of eight or more stored texel values. The interleaved interpolation is configured to combine with the 2-D interpolation within each patch to generate the values. Therefore, a complete 3-D interpolation can be performed with only one read cycle per pixel.

[0010] Furthermore, in another preferred embodiment of the invention, the interpolation means performs a 2-
first and second 2-D interpolators for performing D interpolation;
and a 1-D interpolator for interpolating between two adjacent levels of the array by combining the interpolated values generated by these first and second 2-D interpolators. do.
The 2-D interpolation may be a simple bilinear interpolation, and the 1-D interpolation means may be an overall three-wire trilinear interpolator.

[0011] In another advantageous aspect of the invention, the display processor comprises feedback means by which the first 2-D array is read from the 2-D array stored in one texture memory bank. The interpolator allows the interpolated texel values to be written to a smaller corresponding array in the other texture memory bank, said smaller array representing the same modulation pattern as the first mentioned array, but with a lower level of resolution. Let it be expressed. Such feedback means enable the display processor to generate and store all or part of the texel values of the pyramid array from a single externally generated 2-D array. Therefore, a fast 2-D interpolator can be provided for a second purpose without requiring separate hardware or software filters to generate each pyramid, yet allowing texture pyramids to be generated in real time. I can do it.

In a further embodiment of the invention, the display device receives pyramid texture coordinates and associated level coordinates in the form of 2-D coordinate pairs and generates from these coordinates a physical address for providing to the texture memory. the physical address generating means for generating another physical address corresponding to the same 2-D texture coordinate pair but having level coordinates offset from the received level coordinates; and selection signal means, and the selection means selects the physical address and the other physical address from the first and second physical addresses.
A respective separate bank of texture memory banks is provided for simultaneous reading of the texel values from two adjacent levels of the pyramid array. In yet another embodiment of the invention, each physical address consists of two physical address coordinates, each of which is generated from a respective coordinate of the received texture. It is conventional in texture mapping hardware to use 2-D addressable memory. In particular, as described in the Williams reference,
“Multum in parvo” to memorize
Alternatively, the "MIP map" method can be used to make the storage of pyramid texture maps compact and to make retrieval of these maps very efficient.

In yet another preferred embodiment of the invention, each physical address is constituted by a linear address generated by combining the coordinates of both of the received 2-D texture coordinate pair. In this manner, each 2-D array is free to be stored in any suitable space in memory, providing greater memory utilization than is possible with 2-D memory.

The present invention will be explained below with reference to the drawings.
1 is a block diagram of a display device including texture mapping hardware of a known type. A keyboard 10 and trackerball type input device 12 provide input from the user to a central processing unit (CPU) 14 . The trackerball can be used to draw three-dimensional objects to be manipulated by the system in a known manner. Of course, other devices such as a joystick, a digitizing tablet or a "mouse" can be used as the input device 12. Such devices can also be used to manipulate images created by rotation or zooming or the like. Generally, such devices are more intuitive and effective to use than a conventional keyboard alone. Object images and photographic images to be applied to the object surface by texture mapping can also be input from a video source such as camera 16.

The CPU 14 is connected to the bus 18 (for example, VME
It is connected to a disk store 20, ROM 22, and main memory (MRAM) 24 via a bus). Disk store 20 may include a magnetic floppy disk, a hard disk, and/or an optical memory disk for storing data (e.g., image or three-dimensional model data) and then recalling this data. It can be used to enable manipulation to produce desired new images. Such data may include user work from previous input sessions and/or commercially generated data for interactive computer-aided design simulations or computer simulations, for example for educational or entertainment purposes. In order to be able to model three-dimensional objects, such data is typically stored as polygonal model data rather than in the form of two-dimensional images. The data in this case corresponds, for example, to a three-dimensional model containing an object that is decomposed into groups of polygonal surfaces (basic elements) in a three-dimensional "object" space (eg triangular or quadrilateral surfaces). The data for each object in this model comprises a list giving the location and properties of each polygon that makes up the object, as well as the relative position of each polygon's vertices and the color or transmittance of the polygon's surface. In other systems, the primitives can be curved surface patches, as is known. Specify the “texture” to map it onto the surface and create a scene.
It is known that details can be expressed without increasing the number of primitives that make up the . A texture map is a stored two-dimensional array of texture elements ("texels") that defines a two-dimensional modulation pattern that may define, for example, color in the manner described in detail below. The texture may also modulate other quantities, such as reflectance normal to the surface, in known manner. These textures
Maps can also be stored in a disk store and recalled as needed.

The display device's CPU 14 and other components construct a three-dimensional model in object space by geometric transformations that perform translations, rotations, and perspective projections, typically by matrix multiplication of vertex coordinates, no matter what viewpoint the user chooses. world” into a two-dimensional view (in “viewer” space) for the user. CPU 14 may also perform clipping and lighting calculations on a per-element or per-vertex basis.

[0017] ROM22 and MRAM24 are CPU1
4, which may be a microprocessor such as the Motorola MC68020. Specialized processing hardware 26 can be provided to assist CPU 14 in performing the numerous arithmetic operations required to transform almost any simplest model into a two-dimensional scene. Hardware 26 may consist of standard arithmetic circuitry or may include more powerful custom or programmable digital signal processing (DS).
P) can be an integrated circuit, e.g. VME
Connects to CPU 14 via bus. The nature of the hardware 26 depends on the requirements of the display device, such as speed, resolution, number of primitives, etc. per scene.

The display processing unit (DPU) 28 is
Output of U14 (bus 18) and display memory (VRAM
)30 input. Display memory 30 stores pixel data COL in raster-scan format. The pixel data COL includes, for example, for each pixel an 8-bit value (24 bits in total) corresponding to the red (R), green (G) and blue (B) components of the desired image. It is clear that this number of bits can be increased or decreased and that different color components can be defined by these bits.

[0019] In the DPU 28, the basic element is "scan conversion".
These elements can then be pulled into display memory 30. Scan conversion is a process in which the pixels covered by each primitive are written in the same way, row by row and pixel by pixel, so that the complete image is scanned and output to the display.

A timing unit (video controller) 32 generates read address signals XD and YD to address pixel data in VRAM 30 in synchronization with the raster scan of display screen 34. In response to these address signals, storage locations in VRAM 30 are scanned row by row and column by column and color component values COLD are read and provided to a digital-to-analog converter (DAC) 36. If non-RGB color codes are used, a matrix circuit or color look-up table is provided,
This allows the pixel data COLD to be converted into equivalent RGB signals and provided to a display screen 34, which may be, for example, a cathode ray tube (CRT) display screen. The display screen 34 receives a timing signal (SYNC) from the timing unit 32.
directly or indirectly.

To draw or "represent" the basic elements, the CPU 14 (or special hardware 26)
causes registers in the DPU 28 to be loaded via bus 18 with values defining a single component (eg, regarding vertex coordinates, edge slope, etc.) and its various attributes, ie, color, reflectance, etc. The DPU 28 then determines the pixel coordinates (X and Y) to systematically scan the entire area covered by the primitive.
generate. These pixel coordinates X and Y are supplied to the VRAM 30 as a write address to write the pixel value COL for each pixel.
can be written to the VRAM 30.

The pixel value COL modulates the basic surface color of the basic element to adjust the properties of the object surface (eg, color, transmittance, diffuse reflectance, spectral reflectance) and the attributes of the 3-D environment (eg, the light source). position, color and shape, remote stray light) can be generated to be realistically taken into account. This modulation can be generated arithmetically from parameters loaded with basic data to produce smoothly varying shading, for example to simulate a curved surface. However, in order to achieve a more fine-grained modulation, it is known to use mapping hardware as shown at 40 to provide the modulation values MOD according to a predetermined pattern previously stored in the texture memory 41.

To this end, DPU 28 generates a pair of texture coordinates U and V simultaneously with each pair of pixel (display) coordinates X and Y to map the modulation pattern onto the surface of the elementary element, (i) texture space; from object space and (
ii) Make a geometric transformation from object space to viewer (display) space. FIG. 2 shows the relationship between the texture space defined by the horizontal and vertical axes designated U and V and the screen space defined by the tilt axes X and Y. The texel values actually stored correspond to integer values of U and V, and these values are represented by an array of filled squares. The positions of pixels in screen space are marked by diagonal crosses ('X'), and these positions lie along scan lines S1, S2, S3, etc. parallel to the X axis.

In order to define the coordinates U and V necessary to address the texel values corresponding to successive pixel values in scan lines S1, S2, S3, etc., the CPU 14 (
or by drawing hardware 26), e.g.
U28 is the coordinate pair (
U0, V0) and the partial derivative (
dU/dV and dV/dX) and partial derivatives dU/dY and dV/dY that define the gradient for each pixel in texture space are also given. In the illustrated example, the transformation from texture space to screen space is linear. In the more general case, the scan line S1 etc. and the pixel column may diverge, converge, or curve, in which case the partial derivatives vary from point to point across the elementary element.

Since the texture coordinates U and V are processed in the mapping hardware 40 in the manner described below and then supplied to the texture memory 41, a modulation value MOD for each addressed pixel position X, Y is obtained. It will be done. This modulation value MOD generally contains a color value, which in principle directly forms the pixel value COL, which can also be supplied directly to the display memory (VRAM) 30, as indicated by the dashed data path 42. can. More generally, however, even if the modulation values MOD are color values, these need to be changed within the DPU 28 to provide realistic illumination. In most cases, the modulation value MOD is used in conjunction with other parameters within the DPU 28 to make it less direct to change the pixel value COL. For example, in so-called "bump mapping", the surface normal direction of the elementary element is modulated by the modulation value MOD to influence the subsequent illumination calculation and indirectly change the pixel value COL. Other techniques known as "environmental mapping" e.g.
TR is also used to store the image of the environment as spherical coordinates.
AM can be used to simulate the spectral reflection of complex environments (including light sources, windows, other objects, etc.). This and various other uses of mapping hardware are discussed in the ``IEEE
Computer Graphics and App
The paper by Paul S. Heckbert published on pages 56-67 of ``Su
rvey of Texture Mapping”
as outlined in. It will be clear to those skilled in the art that the invention is applicable to all applications of such mapping hardware.

The texels represented in the texture memory 41 generally do not have a one-to-one correspondence with the pixels of the display, especially when the primitives are shown far away and the texture is therefore mapped to a very small number of pixels. Dimensional space filtering is needed to eliminate aliasing effects that would disturb the viewer when simple subsampling is used.

It is also known that general-purpose filters cannot be economically applied to devices for synthesizing real-time video images, and the aforementioned Williams document provides a conventional solution for this purpose by using several filters for a given pattern. -D
A method is described in which arrays (hereinafter referred to as "maps") are stored and each of these arrays is successively smaller and pre-filtered to progressively lower resolution. In this case, the DPU 28 only needs to generate the level coordinate L and determine the appropriate map to use. In order to compact the storage capacity and increase the speed of access to texel values, the map is selected so that its area is a cumulation of 2, so that it can be used as a "multum in parvo" (
can be stored in a rectangular texture memory according to a "MIP map").

The texture memory 41 in FIG.
The color components R, G and B of the texture pyramid are shown stored as a P map. Maximum (highest resolution)
For example, a map (L = 0) is composed of 512 × 512 texels, an L = 1 map is composed of 256 × 256 texels, and then each map is a single texel, forming L = 9 maps. can do. For example, assuming that each texel value consists of 8 bits for each color component of R, G, and B, the total size of the texture memory 41 is 1 Mbyte.

The texel values are stored in memory 41 via bus 18 and write port 43 of memory 41 prior to rendering. For each texel value to be read, the DPU 28
coordinate pairs, each of these coordinates (U and V) containing at least an integer part 9 bits long. At the same time, a level coordinate L is generated by the DPU 28, which level coordinate is changed from the "virtual" coordinates U and V to the physical coordinate U.
' and V' and store them in the texture memory 4.
1 read address ports 44 and 45, respectively. The memory 41 stores each physical coordinate pair U', V
' in response to R, G and B of the addressed texel
The components are output via a (24-bit) read port 46.

Since the MIP map in the memory 41 is a two-dimensional binary tree arrangement, the necessary physical coordinates U' and V' can be easily generated by a pair of binary shift circuits 47 and 48, respectively. The shift circuit shifts each coordinate to the right to a number of positions defined by the level coordinate L. In particular, where L=0 represents the highest level, the address corresponding to a given texel in the level 0 map shifts the U and V coordinates to the right L positions, effectively scaling each coordinate by 2L. can be translated into the physical address of the corresponding texel in the level L map, which can be found by downgrading. The level coordinate L can be supplied to the DPU 28 as part of the basic data, but if perspective painting should be considered for mapping, the level coordinate L, which depends on the partial derivatives with respect to X and Y, can be supplied for each pixel. DPU28
It is more reliable to generate it internally.

It is known to apply 3-D (for example trilinear) interpolation between texel values to completely eliminate aliasing, in which case the coordinate L
, U' and V' are decimal parts (Lf, Uf' and Vf')
and an integer part (Li, Ui', Vi'). The non-integer parts of the U' and V' coordinates are the 2-D (
The fractional part of the level coordinates LF can be used to interpolate between (2-D interpolated) texel values from two adjacent levels of the pyramidal array. be able to. For this, level Li
Four texel values (Ui', Vi'), (Ui'+1,
Vi′) , (Ui′, Vi′+1) and (Ui
'+1, Vi'+1). These 8
It is clear that there is a penalty in operating speed when reading out multiple texel values serially. Fortunately, the four texel values for each level are stored in texture memory as four parallel memories interleaved to allow 2x2 patch addressing and allow eight values to be read in a few memory read cycles, as detailed below. When configured, they can be read in parallel via read port 46. but,
It is desirable to be able to read the four (Li and Li+1) texel values of both sets in parallel, and the Williams reference allows all levels of a given MIP map to be accessed in parallel by hardwired addressing. It suggests that. Although this is theoretically possible, the method proposed by Williams requires far too many connections to be an economical solution for commercial mass production. For example, with 10 levels, 2x2 patch addressing (excluding the lowest level), and each R, G and B per texel.
8 bits for each supplied coordinate pair U
, V to read port 46 of texture memory 41
It is necessary to output 888 bits of data.

Generally, it is desirable to store various texture pyramids in the texture memory 41. For example, three texture pyramids will define shapes '0', '+' and 'X' that map onto the faces of the cube shown on the screen of display 34 in FIG. To this end, it is known to divide the rectangular array at each level of the MIP map to store a mosaic of corresponding 2-D arrays defining each 2-D pattern. In this case, the coordinate pair U, V generated by the DPU 28 has a 2-D offset merged with it to create a 2-D
Make sure the correct part of the array is addressed. However, this known method always leaves some space in the texture unused, making it practically wasteful. In most cases, it is impossible to eliminate unused space from a 2-D shape mosaic. For example, texture problem '0',
Arranging the three rectangular arrays representing '+' and 'X' into rectangular arrays at each level in conventional hardware texture memory 41 wastes at least 1/4 of the available memory. Finding an optimal solution to a typical 2-D "jigsaw puzzle" is also difficult and must be done in real time when the array can take on various shapes such as squares, squares, and triangles. is completely impossible.

Another disadvantage of the MIP mapping method is that in situations where the basic elements are only visible at a distance, only one or two smaller maps (L=5, L=6, etc.) are actually used. Each texture pyramid occupies a full level of space (1MB in the example above) even if it is not used for
That's what I mean. It would be extremely advantageous to store only the levels that are likely to be needed at any given time in the texture memory, leaving free space available for other texture maps. For example, even though the largest map of the pyramid (L=0) is actually never read during the depiction of the image, this map will occupy 3/4 of the total texture memory capacity.

Unfortunately, it is extremely difficult to provide flexibility in conventional hardware to overcome any of the drawbacks mentioned above.

[0035]

[Example] The present invention will be explained below with reference to an example.
1 illustrates new mapping hardware according to the present invention that may be used in place of that shown at 40 in FIG. By providing a linearly addressed texture memory 41', the problem of eliminating wasted space can be easily solved. Texture management circuit 49 keeps track of the various arrays in linear texture memory 41', and circuit 49 serves to convert pyramid coordinates L, U and V into linear physical texel addresses. Instead of using 2-D offsets to identify all the different textures stored as a mosaic in a large map, the new CPU 14 uses texture identification values T, separate from coordinates U and V, as basic data. supply together. Therefore, the 2-
Both D maps can be identified as maps T, Li, where Li is the integer part of the level coordinate L. Although circuit 49 is more complex than simple 2-D MIP addressing hardware, the improvements in memory utilization and flexibility are significant.

The DPU 28' in FIG. 3 is the related DPU 28.
(FIG. 1), which is slightly modified, has an output terminal T for sending the received identification value to the texture management circuit 49. The modified DPU 28' also has an output terminal that carries a logic signal FB that activates the return path as described below.

The new hardware shown in FIG. 3 incorporates not only 2×2 patch addressing (allowing fast bilinear interpolation), but also new parallel circuitry to overcome the solution proposed by Williams, supra. This allows eight texel values to be used simultaneously for trilinear interpolation without requiring extreme parallelization of the strategy. For this purpose, the texture memory 41' is divided into two memory banks TRAM1 and TRAM2, with arrays T/A for two adjacent levels of a given texture pyramid.
Li and T.Li+1 are always stored in separate banks TRAM1 and TRAM2.

The texture management circuit 49 is the DPU 28
' has input terminals for receiving signals T, L, U and V from '. The texture management circuit 49 comprises a page position and logic circuit (PLLC) 50 which receives the texture identification output T provided by the DPU and at least the integer part Li of the level coordinates.

The PLLC 50 stores information defining each map T and Li, and stores the information in the bank TRAM1 or TRAM2.
(1) Map T・Li, (2) Map width W (T・Li) in the U direction and reference address B (T・Li) that determines the starting position for linearly storing the array in the appropriate bank TRAM1 or TRAM2. ) to be memorized.

In general, PLLC 50 provides stored data for maps T.Li and T.Li+1 to the remainder of circuit 49, thereby providing memory bank TRAM1 with stored data for maps T.Li and T.Li+1.
and linear address A given to TRAM2 respectively.
1 and A2 to address the texel data for the coordinate pair (U, V) of levels Li and Li+1 in the texture pyramid T. The general formula for these linear addresses is: In other words, address A=A(T・Li) or A(T・Li
+1) in memory bank TRAM1 and address A2=A(T・Li+1) or A(T・Li) in memory bank TRAM2, U
VA(T.Li
)=──────+w (T・Li) ──────+
B(T・Li)su
(T・Li) sv(T
・Li) and U
VA(T.Li
+1) =──────+w (T・Li+1) ──
────+B (T・Li+1)
su(T・Li+1)
sv(T·Li+1). su(T・Li) and sv(T
·Li) represents the generalized scale factor related to the dimensions of the map T·Li with respect to the dimensions of the maximum map (T·O) in the U and V directions of the pyramid T.

As in the conventional method, scaling factors su(T·Li) and sv(T·Li) are limited to powers of 2 defined by, for example, su=sv=2Li for all values of L and T. The addressing hardware according to the invention can then be extremely simplified. Even simpler hardware can be used, as in the MIP map method, to set the width value w of the map to, for example, the width index W(T·Li) and the formula w(T·Li) = 2W(
T. Li) can be obtained by limiting to the power of two texels defined by . These 2
The texture management circuit 49 shown in Figure 3 simplifies the process.
Incorporate into. These limitations apply not only to rectangular maps but also to rectangular maps, but if desired, hardware can be constructed using formulas more general than those described above. This general formula can be further generalized to store other shapes effectively, such as triangular or trapezoidal textures, by varying the width w in the U direction linearly or non-linearly across the map in the V direction. .

Taking into account the above-mentioned limitations associated with hardware simplification, a new formula can be derived for migrating to simpler hardware. These formulas are as shown below, and the symbols “→” and “←” used here represent binary right left (division) and left shift (multiplication), respectively. Therefore, for example, the expression "(U→L1)i" is the integer part of the value U after shifting to the right by L1 bit positions, in other words, U
Indicates the quotient of ÷2L1.

A1=(U→L1)i+((V→L1)
i ←W1)+B1 where L1=Li or Li+1, w(T・L1) =2W1, and
A2=(U→L2)i+((V→L2)i←W2)+B
2Here, L2=Li+1 or Li, and w(T・L2
) =2W2.

Returning to FIG. 3, which shows the hardware that executes these formulas for A1 and A2, P in FIG.
LLC50 is a value W that defines the width and base position of the map to be addressed in TRAM1 and TRAM2.
1, B1, W2 and B2, respectively. The PLLC50 has a texture memory bank TRAM1 mapped to T. It generates a binary signal SWI 1 which takes the value 1 or 0 depending on whether it contains the map T.

[Outside 1] occurs.

An adder 51 is provided within the remainder of the texture management circuit 49 to generate a value Li+1 from the value Li generated by DOU 28'. logic signal SW
The multiplexer 52 responsive to I 1 is Li or Li
+1 is selected to generate level coordinates L1 for the map stored in bank TRAM1. Another multiplexer 53 selects the other of Li and Li+1 in response to the complementary logic signal SWI 2 to select the other of the bank TRAM2.
generate level coordinates L2 for the map stored in the map. The first right shifter 54 responsive to the level coordinate L1 is
It receives the U coordinates of the coordinates U and V generated by the DPU 28' and generates a first scaled U coordinate U1=U→L1. The second right shifter 55 responding to the same level coordinate L1 is V
The coordinates are received and a first scaled V coordinate V1=V→L1 is generated. The third and fourth right shifters 56 and 57 also receive the U and V coordinates, respectively, and are responsive to the level coordinate L2 to provide a second scaled U and V coordinate for the map stored in the second bank TRAM2 of the texture memory 41'. V coordinates, U2=U→L2 and V2=V→L2 are generated, respectively.

Scaled coordinates U1, V1, U2 and V2 are their integer part U1i etc. and their decimal part U1
Separate into f etc. First and second left shifters 58 and 59 receive the integer parts V1i and V2i of the scaled V coordinates V1 and V2, respectively, and generate values 2W1·V1i and 2W2·V2i, respectively, in response to width indices W1 and W2, respectively. do. Here, 2W1 and 2W2 are respectively bank T
It is the width of the map stored in RAM1 and TRAM2.

An adder 60 converts the integer part U1i of the first scaled U coordinate U1 to the value 2 generated by the first left shifter 58.
A first linear offset address I1 is generated by adding it to W1·V1i. Another adder 61 adds the first offset address I1 to the first map base address B1 generated by the PLLC 50 to generate a first linear texel address A1 for supply to the first bank of texture memory 41'. Similarly, the other adder 62 has the value U2
i and 2W2·V2i to generate a second linear offset address I2, and another adder 63 adds the second linear offset address I2 to the second map base address B2 generated by the PLLC 50 to generate the second linear offset address I2. A linear texel address A2 is generated and supplied to the second bank TRAM2 of the texture memory 41'. Since the bits of the value V1i (or V2i) once shifted do not overlap with the bits of the value U1i (U2i),
Adders 60 and 62 can actually be implemented with simple OR gates.

Each texture memory bank TRAM1
and TRAM2 are divided into four parts A, B, C and D which can be addressed in parallel as shown in the figure. The texel values defining a given map are stored in the appropriate memory bank (TRA
A 2×2 texel patch is distributed between the four portions A to D of M1 or TRAM2) according to a predetermined pattern as shown in FIG. Enable parallel addressing. In the pattern shown, the texel values of even numbered texel lines (V is even) are stored alternately in portions A and B. The texel values of odd numbered lines (V is odd) are stored alternately in portions C and D.

To enable this patch addressing, a special address port 64 receives the linear texel address A1 from the adder 61 and divides the four addresses A1
A to A1D are generated and four memories TRAM1A to T
In response to these addresses, patches (U, V), (U+1, V), (U,
V+1) and (U+1, V+1) texel values can be obtained from the four corresponding read ports 65A-65D.

[0050] Four correct addresses A1A to A1D
Address port 64 is connected to the first
The least significant bits U1ilsb and V1ilsb of the integer part of the scaled coordinate pair U1, V1 (these bits are U1
and specify whether V1 is odd or even). Patch addressing hardware 64, 65A ~6
Regarding the detailed design of 5D, it can be similar to that used to convert digital video images, an example of which is
system Design Magazine” 19
August 1987, pp. 81-85 Joel H. Derrick’s paper “Transforming Digit
One difference from this known hardware is that the system shown in FIG. 3 requires a texel array of linear storage. 2-D In Derrick's circuit, which uses addressable frame store memory, the unit value 0001 is added to the ordinate (Y') to address the texel value of the next row (Y'+1) of the image. However,
In the circuit of Fig. 3, the array width W (T・Li) = 2W1
is added to the linear address A1 to correctly address the texel value of the next row V1+1 of the linearly stored texture map. For this purpose, address port 64
is the PL for the map stored in bank TRAM1.
A width index W1 generated by LC 50 is also received.

A similar patch address port 66 is provided for the second bank TRAM2 of the texture memory 41', with a second linear address A2, odd/even index U2.
ilsb and V2 ilsb and second width index W2
receive. Port 66 is patch address A2A ~
A2D and supplies these addresses to respective portions A-D of the second texture memory bank TRAM2 having four corresponding read ports 67A-67D.

[0052] Patch addresses A1A to A1D and
Many configurations suitable for generating A2A-A2D are possible. For example, instead of generating a single linear address A1 and stretching it to form addresses A1A-A1D, patch addressing functionality may be merged with linear address generation functionality to generate addresses A1A-A1D from coordinates L1, U1, and V1. can be generated directly. In such an embodiment, some elements may be 4
It is necessary to overlap the other elements with addresses A1A~
At least two occurrences of A1D can be contributed to. Also, larger patches can be addressed by using more parallel memory and ports.

Bank TRAM1 read port 65A
The four texel values from ~65D are the first bilinear (
2-D) is applied to the input terminal of an interpolator BIL1, which interpolator calculates the fractional part U of the first scaled coordinate pair U1, V1.
1f and V1f are also received. Bilinear interpolator BI
L1 is (obtained from the integer parts U1i and V1i)
The four texel values in the patch addressed by addresses A1A-A1D are combined to generate a first bilinear interpolated texel value MOD1. Bank TRAM2
The texel values from the read ports 67A to 67D are likewise fed to a second bilinear interpolator BIL2, which interpolates the fractional part U2 of the second scaled coordinate pair U2, V2.
f and V2f are also received and generate a second bilinear interpolated texel value MOD2.

Two bilinear interpolated values MOD1 and MO
D2 (one from map T.Li, the other from map T.
(obtained from Li+1) is then linear interpolator LINT
supplied to This interpolator LINT has values MOD1 and M
OD2 are combined at a rate determined by the fractional part Lf of the level coordinate L received from the DPU 28' to generate trilinear interpolated modulation values MOD for the pyramid coordinates L, U, and V. As in the known device (Fig. 1), the value MOD directly modulates the pixel color value COL (dashed path 42).
or can be used to execute indirectly via other processing within the DPU 28'.

Texel Values If the MOD specifies a color, each texel value preferably contains three color component values, such as R, G, B, in which case the interpolators BIL1, BIL2 and Each LINT may actually include three interpolators or be otherwise configured to perform a three-component interpolation.

The hardware shown in FIG. 3 also includes first and second return paths 70 and 72, and includes a first memory bank TRAM1.
can be supplied to the write port 71 of the second bank TRAM2 of the texture memory 41', and
can be applied to the write port 73 of the first bank TRAM1. A logic signal FB provided by the DPU 28' indicates that the feedback path should be driven.
1" state. AND gates 74 and 75 connect signal FB to logic signal S generated by PLLC50.
In combination with WI 1 and SWI 2 , a pair of logic signals FB1 and FB2 are generated. Multiplexers 76 and 78 output signals FB1=1 and FB2, respectively.
= 1, when FB and SW1 = 1 or F
When B and SWI2=1, the first or second return path 70 or 72 is closed. During other times each multiplexer 7
6 or 78 connects the corresponding write port 71 or 73 to the CPU 14 via the bus 18. The purpose of return paths 70 and 72 will be explained in due course, but for the time being it will be assumed that these return paths are inactive (FB=0).

FIG. 4 illustrates three partial pyramid texture maps (T=1, 2, 3) stored in linear memory banks TRAM1 and TRAM2 to access in parallel all texel values required for trilinear interpolation. It shows what you can get. Each memory bank constitutes a linear physical address space A1 or A2, respectively. The 2-D array (map) of texel values for levels Ti of map T is stored linearly as data pages denoted PT.Li. Texture 1 may have four pages P1.0, P1.1, P1.2 and P1.3, each page being 1/4 the linear size of the previous page. When P1.0 is stored in bank TRAM1, page P1.1 is stored in bank TRAM2, and page P1.2 is stored in bank TRAM1.
, and the following are stored alternately in the same way.

The second texture (T=2) has three pages P2.1 to P2.3 in banks TRAM1 and TRAM1.
The entries corresponding to each page are stored alternately in the RAM2, and the entries corresponding to each page are stored in the page table memory P described below with reference to FIG.
Exists in TAB. Highest level page P2.0
is present, but since it is not needed at the time shown, this page is not stored in the texture memory, making more free space available for receiving other maps if required. In practice, the memory map shown in FIG. (or low) resolution can represent the time at which it is erased when it is no longer needed. texture memory 4
Even if more texel data than the space in banks TRAM1 and TRAM2 of TRAM1' is required, at least a low resolution map can be loaded and interpolated to the required size until space becomes available. This "graceful degeneration" property of linear texture memories is an advantage over known 2-D map memories, where texture pyramids generally occupy either space at all levels or none at all.

The third texture (T=3) is also loaded alternately into TRAM1 and TRAM2 with three pages, but page P3.0 is the L of the first two textures.
i = smaller than 0 pages. This is because the third texture only needs to be defined with low detail. This also contributes to more efficient use of texture memory capacity compared to conventional MIP maps.

FIG. 5 shows the page position and logic circuit of FIG.
Page table memory PT indicated by a broken line inside LLC50
The contents of AB are shown, and this circuit allows finding a given array T·Li in memory. In the page table, there is an entry for each page PT/Li of each texture. The first item in each entry is whether the page is stored in bank TRAM1 or not.
A single bit value outside 2 that takes the value 1 or 0 depending on whether it is stored in M2

[Outside 2]. This bit value therefore drives the logic circuit PLLC to generate the signals SWI 1 and SWI2 to control the generation of addresses A1 and A2 as described with respect to FIG.

The second item of each entry in the table is the width index of the map T.Li. Page P1
．． 0 contains map 2W = 29 = 512 texels wide, P1.1 contains map 28 = 256 texels wide, P3.1 contains 27 = 128 texels width, and so on. The third attem of each entry is the memory (TR
AM1 or TRAM2).

Returning to FIG. 3, the array of texel values forming page P1.0 etc. is connected to bus 1 as shown in the figure.
8 and write ports 71 and 73 by the CPU 14 into the memory banks TRAM1 and TRAM2. This is a straight forward method of “housekeeping” for the CPU14, and (
i) storing any new page of texel data in an unused portion of the texture memory; (ii) storing each successive level of a given pyramid in a different bank TRAM1;
or alternately storing in TRAM2, (iii)
At the same time, the page table PTAB in PLLC50 has three external

[Example 3] Appropriate values for W and B can be loaded. If not enough space is available in a single block for a new texture (for example, if P2.0 needs to be loaded), in this case a "garbage collection" operation is performed to collect the unused parts. It can be made into a large enough space.

The entire pyramid texture array can be stored in a database in disk store 20 or main memory 24, and the various 2-D level arrays (maps) can be transferred to spare locations in the appropriate texture memory as needed. can do. However, return paths 70 and 7
2, the bilinear interpolator BIL1 or B
Using IL2 as a filter as described below,
Sequential levels of maps can be generated from a single high resolution map loaded via bus 18. This is advantageous because patch addressing and interpolation can achieve faster filtering than software routines conventionally executed by the CPU 14.

FIG. 6 shows that the filtered map T·Li+1 is generated from the map T·Li previously stored in one bank of the texture memory 41' using the value feedback generated by the existing bilinear interpolation. 12 is a flowchart showing a series of operations performed to generate the information. In the first step 80, the CPU 14 performs P
4 outside the appropriate value for an entry in page table TRAB in LLC50

Allocate texture memory space for page PT.Li+1 by loading B(T.Li+1) and B(T.Li+1).

Next, in step 82, the DPU 28
' sets the logic signal FB=1 and the feedback path 70 or 7
Activate 2. In step 84, the DPU 28
' is a linear interpolator during filtering process LINT
Any value MOD generated by MOD will be ignored. In step 86, DPU 28' is set up with the values of UO, VO and partial derivatives selected to draw the polygon, resulting in the generation of the desired filter values. Returning to the figure, it is assumed that the appropriate texel position of the filter map T·Li+1 is the position indicated by a circled cross. To generate values to be interpolated at these texel positions, the starting values are (Uo, Vo) = (1/2,
1/2), and the partial derivative is dU dV
dU dV ──
──=2;────=0;────=0;────=2
dX dX
dY dY.

In step 88, the DPU 28'"draws" a virtual polygon and draws the bilinear interpolator BIL1 or BIL2 depending on whether the source mass T.Li is stored in bank TRAM1 or TRAM2.
A desired filter value MOD1 or MOD2 is automatically generated at the output terminal of the filter. At the same time, logic signals FB=1 and S
Since WI 1 = 1 or SWI 2 = 1, FB
1 =1 or FB2 =1, thus driving one of multiplexers 76 and 78 to close the appropriate return path 70 or 72. The interpolated value is then automatically written in step 80 to the location in the other memory bank (TRAM2 or TRAM1) allocated for map T.Li+1.

The process of FIG. 6 may be repeated as necessary (each time incrementing the level coordinate L as shown in step 90), using return paths 70 and 72 alternately to display the entire pyramid array in a single display processor. can be generated from an externally generated high resolution array. that different scale factors are possible for those skilled in the art;
It will be appreciated that a rectangular map can be generated from a rectangular map, for example, by asymmetric filtering and considering asymmetric maps. As a specific example,
dU
dV dU
dV (Uo, Vo) = (0, 0)
, ───=1;────=0;───=0;───=
1 dX
dX dY
By using dY, a texel-by-texel transfer of the map from one bank of texture memory to another is obtained. Such transfers are useful for the "garbage collection" operations described above.

The use of texture mapping hardware for map filtering and/or transfer has advantages over conventional methods using software running on a host computer. This is because the display processor hardware is pre-adapted for fast addressing of texture arrays and includes 2x2 patch addressing hardware, interpolation hardware that receives R, G and B in parallel, etc. It is. This advantage is easily understood when one considers that filtering or forwarding a 2-D array in this device takes approximately the same amount of time as it takes to draw a single polygon of the same size. This is overhead that can generally be consumed in real time without significant performance degradation. This is because typical systems can pre-draw hundreds or thousands of polygons within each image frame. Implementing a hardware texture filter using feedback does not depend on the linearity of the map storage, nor does it depend on the structure of the dual bank memory. By generating a filtered map using dedicated addressing and interpolation hardware, even with a conventional 2-D mapping device as shown in FIG. A large speedup is obtained over conventional software approaches, and the overhead is still equivalent to one polygon.

The numerical limitations such as the map size used in the embodiments described above, for example, simplify the configuration of the PLLC 50 and allow the use of bit shifters 54-59 in place of complex multipliers. These numerical limits simplify the allocation of space for new pages in texture memory. However, it is clear that there is no need to limit the design in this way; many variations are possible and are listed below. For example, the width index W is such that the map width is always 2N-Li
(where 2N is the maximum allowable map), there is no need to store it separately. In this case, texture T
In the example of FIGS. 4 and 5 where the highest level of =3 is only 256 texels, the width index can be removed by renaming page P3.0 to P3.1. The reason is that in this case all maps with Li=1 have W=8 (width=256), regardless of whether there are large maps with Li=0 or not. To provide an asymmetrically filtered map, first 2N-L
Two level values Lu and Lv can be provided that identify the map of 2N-Lui texels stored by the Vi rows. The changes in the structure of the texture management circuitry required to implement these changes will be readily apparent to those skilled in the art.

It will also be clear to those skilled in the art that the principles of using dual bank texture memories to enable parallel access for interlevel interpolation are not only applicable to the linear texture memory configurations described above. FIG. 7 shows two two-dimensional texture memory banks 170.
and 172 shows one possible example of storing two pyramid texture arrays (R1/G1/B1 and R2/G2/B2). The assignment is the conventional MI in Figure 2.
It is similar to the P map device, but allows parallel reading from adjacent levels of any one texture. Additionally, those skilled in the art will be able to modify the mapping hardware 40 of FIG. 1 to take advantage of such dual-texture memory to achieve the parallel addressing of two-level maps required for inter-level interpolation. is easy. It is also possible to obtain hardware that generates pyramid maps from a single high resolution by providing return paths such as return paths 70 and 72 (FIG. 3).

Those skilled in the art will be able to make other modifications after reading the above description, and it goes without saying that the present invention includes these modifications.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display device including texture mapping hardware of a known type.

FIG. 2 shows a 2-D array of texel values stored in texture memory.

FIG. 3 is a block diagram of novel texture mapping hardware embodying the invention.

FIG. 4 is a diagram showing how three pyramid texture maps are stored in two linear texture memories in the hardware of FIG. 3;

FIG. 5 is a diagram showing the contents of a page table memory in the hardware of FIG. 3;

FIG. 6 is a flowchart illustrating a process for generating a filtered 2-D array using a feedback path in accordance with the present invention in the hardware of FIGS. 3-5.

FIG. 7 shows the storage of two pyramid texture maps in two two-dimensional texture memories similar to those of known hardware;

[Explanation of symbols]

10 Keyboard 12 Input device 14 Central processing unit 16 Video camera 18 Bus 20 Disk store 22 ROM 24 Main memory (MRAM) 26 Special processing hardware 28, 28' Display processing unit 30 Display memory 32 Timing unit (video controller) 3
4 Display screen 36 Digital-to-analog converter 40 Mapping hardware 41, 41' Texture memory TRAM1,
TRAM2 Memory bank 43 Write ports 44, 45 Read address port 46 Read ports 47, 48 Binary shift circuit 49 Texture management circuit 50 Page position/logic circuit 51, 60, 61, 62, 63 Adder 52
, 53 Multiplexer 54, 55, 56, 57, 58, 59 Shifter 64, 66 Address port 65A-65D, 67A-67D Read port BIL
1, BIL2 Bilinear interpolator LINT Linear interpolator 70, 72 Feedback path 74, 75 AND Gate 76, 78 Multiplexer

Claims (7)

[Claims] 1. An associated display memory for the values of texture elements ("texels") representing two-dimensional (2-D) modulation patterns at at least two distinct resolution levels distinguishable by each value of the level coordinates. a display processor having a texture memory for storing at least one pyramid or partially pyramidal array; and a display processor having a texture memory for storing at least one pyramid or partially pyramidal array; In a display device also comprising interleaving interpolation means responsive to the fractional part of the received level coordinates for combining together corresponding texel values from two levels, said texture memory comprises separate first and second texture memory banks addressable in parallel, and the display device alternates 2-D arrays of texel values forming successive levels of the stored pyramid array in each of the first and second texture memory banks. A display device characterized in that it also comprises means for storing texel values. 2. dividing each texture memory bank into at least three parallelly addressed memories;
the texel value storage means are configured such that the texel values are stored in an interleaved manner such that values for a 2-D patch of texels can be read in parallel from each of the first and second texture memory banks; is configured to combine interleaved interpolation with 2-D interpolation within each patch to generate a single 3-D interpolated value from a set of eight or more stored texel values. The display device according to claim 1, characterized in that: 3. The interpolation means includes first and second texture memory banks for performing 2-D interpolation between values in 2-D patches stored in first and second texture memory banks, respectively. 2-D interpolator and these first and second 2
- a 1-D interpolator for interpolating between two adjacent levels of the array by combining the interpolated values generated by the D interpolators. Device. 4. The display processor comprises feedback means for reading from a 2-D array stored in one of the texture memory banks;
allows the texel values interpolated by the 2-D interpolator of the 2-D interpolator to be written to a smaller corresponding array in the other texture memory bank, said smaller array representing the same modulation pattern as the first mentioned array but with a lower 4. The display device according to claim 3, wherein the display device displays level resolution. 5. Physical address generation means for the display device to receive pyramid texture coordinates and associated level coordinates in the form of 2-D coordinate pairs, and to generate from these coordinates a physical address for providing to the texture memory. and the physical address generation means are the same. 2
- D texture coordinate pairs, but also comprising means for generating another physical address having level coordinates offset from the received level coordinates and selection signal means, the selecting means causing said physical address and said other physical address to be selected. of the pyramid array by providing physical addresses of
5. A display device according to claim 1, wherein said texel values are simultaneously read out from two adjacent levels. 6. The display device of claim 5, wherein each physical address comprises two physical address coordinates, each of which is generated from each coordinate of the received texture. [Claim 7] Each of the physical addresses is
6. The display device according to claim 5, wherein the display device comprises a linear address generated by combining both coordinates of a 2-D texture coordinate pair.