JPS615287A - Graphic image generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a progressive scanning graphics image generation apparatus using a computer.

More particularly, the present invention relates to a graphics image generator with improved spatial resolution, reduced aliasing, and a digital vector generator for high speed graph ink display.

Prior art image display devices provide an array of discrete points, called pixels, whose intensity of emitted light can be independently controlled. Each pixel represents a single intensity for monochromatic devices, and can represent three different primary color intensities for trichromatic devices.

The display image is generated by effectively sampling the light intensity at each imaginary of the source image corresponding to the display pixel, and brightening each pixel according to its corresponding sampled light intensity value. In the case of computer-generated images, the light intensity value of a pixel is determined by the value of the light intensity of a pixel when the actual image of the selected object is sampled under the selected light conditions.
Generated by a computer as a prediction of what the value will be.

Progressive scan display devices typically have a two-dimensional rectangular array of pixels arranged in rows and columns. A frame buffer stores the intensity value for each pixel in a storage location that is addressably accessible according to the pixel's row and column position within the array. As the controlled beam scans the pixel array row by row, corresponding illumination data is read out from the frame buffer to control the brightness of the scanning beam at each pixel and thus the corresponding illumination intensity of the pixel. used.

Because the display pixels occupy discrete locations within the array (eg, a 512x512 array), the illumination intensity can only be controlled at these discrete locations. It is common for there to be lines or edges that do not exactly match predetermined pixel positions in one image, resulting in the appearance of stepped jagged edges called aliasing. Those that are effective will be displayed.

This aliasing problem is particularly severe for lines or lines that are almost parallel to one of the directional (row or column) axes of the pixel array, but are not perfect. These display devices and their problems were discussed by J.D. Folley.
[Fundamentals of Conversational Computer Graphing] by Vandam, A., Addison-Wesley Publishing Co., Ltd.
blishingCo, ) (1982) PP, +Iul-503.

One solution to the aliasing problem would be to increase the number of pixels and hence the spatial resolution of the display. However, current display devices are approaching the limits of available resolution for economical devices;
Further increasing the resolution requires a significant increase in manufacturing costs. Furthermore, in each dimension,
Each doubling of the number of pixels requires the already expensive frame buffer to be quadrupled in size and the operating speed and device bandwidth to be increased by the same factor.

A commonly used solution to aliasing is the aforementioned Foley and Pandam book, PP, 113.
6-1137, by passing the luminance values through a low-pass filter.

However, this technique requires the lines to be at least two pixels wide and results in blurred or fuzzy edged lines. This technique does not work well for color mapping devices where a high resolution range of continuous values is not available for each color gamut across low resolution monochromatic devices. Even for high dynamic resolution full color devices, averaging the luminance at the intersection boundaries of different colors results in a color that is unrelated to either of the two intersecting colors.

David A. Lie
n) "Efson M.K. Flinter Manual", Compusoft Publishing Co., Ltd.
(1982) PP, 3-1.3-5, q
-g to 1l-11, 7-4 to 7-6, and 15
By overstriking an entire image one or more times and shifting the print hammer by a sub-vixel distance on each different overstriking pass, as described in 9. .

A dot matrix printer device that reduces the number of dots is known. Since the same display pattern is used for each pass,
Display buffer storage requirements are not increased. This device produces wide thick lines and does not truly increase the resolution of the displayed image. It is unsatisfactory, especially when thin, high resolution lines are required. Note that the operating speed is significantly reduced.

U.S. Patent No. 99 by Hogan et al.
No. 6,585 discloses a single-dimensional vector generator in which an integer number of steps are taken in the vertical direction and the generator generates pixel data in the horizontal direction. Unable to adapt to two dimensions, this vector generator is used only for spatial information and not for color or luminance information.

US Patent No. 1 by Pruznick et al.
1, 15 g, No. 858, ``Apparatus for Smoothing Symbols on Rask'' provides an apparatus similar to 'low-pass filter apparatus. In this device, a brightness control code is stored for each pixel location. During refresh, each pixel is displayed sequentially, so that in addition to the data from the current display pixel, the brightness control code is stored for each pixel location. data is used to derive the brightness value for the current display pixel.

U.S. Pat. No. 4,212,009 to Ad, Leman et al., "Smoothing Progressive Scan Displays," teaches an arrangement in which the width of the raster beam is varied according to the data to be displayed.

U.S. Patent No. 11.386.549 to Grandberg et al.
"Smoothing" describes a means of using sub-vixel addressing to reduce aliasing without increasing the resolution of the display device.

(Zabvixel means a pixel smaller than 1 pixel)
This device provides each pixel with one pit of luminance information and five bits of sub-vixel address information. Deflection in both the X and Y directions is achieved with special deflection coils, so
Each pixel is physically moved while maintaining the -i shape. This results in overlaps in some places and gaps that appear as black spots in others. Furthermore, each pixel is modified only in one axis, so
An undesirable deviation occurs at the end of the joining line.

Note that writing one image into memory takes twice as long, since it has to be determined both by the pixel storage location itself and by the directional information present in the preceding pixels.

Video image data is typically provided to a digital vector generator as a list of lines or polygons defined by endpoints and corners or slopes of the lines. Visual characteristic information is provided for each line or polygon as part of the test. The spatial information is generated to generate a spatial address storage location that defines each line of the display as a point of multiple adjacent pixels.
Used to initialize the preceding digital vector generator. Each vector generator generates address information that defines the X, Y, and Z coordinates that locate the line in the five-dimensional display space.

A frame buffer storage device is provided having address storage locations corresponding to the location of each pixel in the displayed image. Visual characteristic information defining the visual display characteristics of each pixel must be stored in the address for that pixel. This visual property information may have different parts that define brightness and hue, or may have different partials that define red, green, and blue (RGB) color brightness, and can be edited to create the desired visual property information. The colormap table may also contain information for addressing the colormap table.

Although the digital vector generator determines the X, Y, and Z coordinates for the next point on a line, the central processing unit must also determine the visual characteristic information for the next point. When both visual characteristic information and spatial address information are available, the spatial address information is used to address the frame buffer and the visual characteristic information is written to the selected address location.

The number of pixels that make up a video display, e.g.

768 x 525 = It 05.2 '00, so the time required to generate all the pixel errors for the displayed image can be significant. Generating an image using sophisticated shading algorithms such as phono shading and Gouraud shading can take several minutes in total. Various shading and texturing techniques are described in the following publications:

Smith Alvy Ra
y) "Tint Fill", Computer Gusify 7
17 (ACM) Vol, 15, NIL 2, PP, 2
76-285 (August 1979) is a territory with boundaries.
The algorithm for t-filling is fully disclosed.

This algorithm is adapted to handle the gradual shading at the bottom of the line that is said to be introduced by all anti-aliasing techniques in a special way.

Langdon, Jr.
, ) and other U.S. Pat. All graphics devices including F(AM) are disclosed.

However, the disclosed device provides a wide range of selectable operating modes available in the present device, as well as the aforementioned U.S. Pat. No. 3,996,585 and U.S. Pat. , 212.009 〇Means for solving the problem of virtual completeness Effective space of the image displayed without increasing the number of pixels used for displaying the image by the graph ink image generation device according to the present invention Total resolution increases.

This device consists of a cathode ray tube (CRT) connected to display an entire image defined by a rectangular array of pixels, frame bassometry, and data stored in a frame buffer.
3, a frame buffer contains a memory location for each pixel in the video image, and defines each pixel in each memory location as the normal representation of one pixel in the array of displayed images. At least one visual characteristic information of a pixel including a spatial displacement from the background or a zero displacement position is stored.

The visual image generator sequentially receives information indicating visual characteristics from the frame buffer for each pixel and accordingly visually manifests the pixel. Each pixel is assigned a normal position within a uniformly spaced rectangular array of pixels and is offset from the normal position according to spatial displacement information indicating the true position of the pixel.

In a progressive scan display, the pixel boundaries' (+-) are determined horizontally (i.e. in the progressive scan direction) by selectively varying the brightness of one pixel at the moment it is transmitted to the display.
Can be moved to the left or right.

When the raster sweeps the displayed image from left to right at a uniform speed, applying the visual luminance signal early will move the pixel to the left, and applying the visual luminance signal slowly will move the pixel all the way to the right. In the vertical direction, sub-vixel displacement is achieved by adding a full sub-vixel vertical deflection mechanism to the normal vertical deflection device for the display.

For example, in the case of cRT, a set of one-turn, low-inductance sub-vixel deflection coils can be placed between the funnel-shaped portion of the entire cathode ray tube and the existing deflection coil. Therefore, both horizontal and vertical sub-vixel addressing can be superimposed on conventional CRT vertical and horizontal deflection circuits without modification of both.

A high-speed graphics display digital vector generator according to the present invention includes a multi-dimensional space digital vector generator and a five-dimensional space digital vector generator connected to operate synchronously therewith.
Includes a dimensional visual signature digital vector generator. A vector processing subsystem responds to the generated visual feature vector information with a wide range of selectable options.

The vector processing device includes a normalization circuit connected to receive the three visual characteristic vectors and responsively generate normalized luminance values suitable for use in phono grading.

The pattern shape multiplexer responds to two of the visual characteristic vectors by generating an output signal representative of the selected resolution of each of the received vectors. A writable pattern RAM is connected in such a way that it is addressed by the output of the pattern shape multiplexer and is conveniently used to represent hues in any selected three-dimensional or textured pattern. Generates an output signal that can

The hue pattern of the visual feature vector generator in the pattern RAM can be easily correlated to the spatial pattern in the displayed video image.

A color/intensity multiplexer receives the output data from the pattern RAM and normalization circuit and combines the output into a selected data pattern for storage in the frame panorama for output to the video display device as required. It is connected to the. This color/luminance multiplexer is particularly useful when used to combine luminance information from the normalization circuit with hue information from the RAM to form a full pixel display data word with a selected resolution for each of the two components. convenient.

Example A straight scan graph ink image generator 10 is shown.

The image generation and storage device 12 may be of a conventional nature, and in a typical arrangement includes a database storing display lists for each image to be displayed, communication interface circuitry, and a keyboard, data tablet, etc. and a peripheral control circuit including a data input device such as a joystick.

A digital vector generator (DvG) xq receives a list of image-specific data from image generation and storage device 12 and converts such data into an array of pixels that define a displayed image. This array of pixels is communicated to frame buffer memory 16 and stored therein. In this embodiment, the frame buffer memory 16 is stored in a rectangular image having its origin at the upper left corner, the positive direction of the Y-axis Q extending in the ] direction, and the positive direction of the X-axis extending to the right. There is storage for a pixel array of dimensions 768x576.

Buffer Memory] For each pixel storage location in 6, 12 bits of video information are stored, along with 2 bits of ZubHiri cell χ AT V address information and 2 bits of ZUB BIXEL Y address information.
Bits are memorized.

Frame buffer memory 16 still has storage locations corresponding to each pixel storage location in the video display buffer memory, and a fifth dimension, or two-axis position, for each pixel location in the display device. Z buffer 1 to remember
6a is included. The Z-axis is considered to be firmly away from the viewer from the origin, which is in the plane of the display screen, perpendicular to the χ-axis and the Y-axis. When moving one pixel of information to frame buffer memory 16, the current 2, i.e.
The value of depth is retrieved from the addressed pixel's storage location in Z buffer 16a and compared with the Z value of the new data. First, the value of Z/<tsu is cented. The value of Z of the new data has a selected functional relationship with respect to the previously existing old data such that the value of Z of the old data is less than or equal to the value of Z of the old data, and the new data , the new data is stored in the frame buffer
The value of the Z coordinate is written to the memory 16 by 2 buffers 16
Write to a and set the brightness of the video display and the X, Y sub-vixels.
Write address data to frame buffer 16.

The Z value of the new data is greater than the previously stored value of 2 at the indicated pixel address (if the new data is far away from the viewer and is obscured by the surface defined by the previously stored data). )
If the new data is stored in frame buffer memory 16
writes are suppressed and new data is discarded. In this way, only the visible surface is actually the frame.
No separate operations are required to complete the proper assembly of the array of pixels for the image that is written to the buffer memory 16 and that distinguishes visible from hidden surfaces. The Z-buffer inhibit feature may be selectively enabled or disabled according to the desired mode of operation.

Within the frame buffer there are three planes of 52 bits forming two display buffers and a Z buffer 16a. Each display buffer contains 12 luminance planes, four sub-vixel address planes and two overlay planes for text or cursors. A single Z-buffer 16a stores depth coordinates. Only the first frame buffer has a digital vector generator DvG
Both buffers can be read by the video output subsystem. In normal operation, the second frame buffer is read continuously to refresh the display system while updating the first buffer. After updating the first buffer, the data is transferred to the second buffer.

During this transfer period, the video output subsystem reads the first buffer from frame buffer memory 16 in raster scan order to convert the data pixels stored by frame buffer memory 16 into a visible image. The 12-pit video display data is transferred to the color map RAM 1g, which performs a conversion operation to convert it into a predetermined color RGB display having a maximum of g bits for each color. Colormap RAM 1g serves as a color lookup table loaded from image generation and storage device 12. This allows a particular brightness and hue to be assigned to the bits of a given pattern at a selected address in frame buffer memory 16.

The brightness adjustment and horizontal sub-pixel deflection circuit 20 receives RGB color brightness change information from the color map RAM 1g and X and Y sub-pixel addressing from the frame buffer memory 16, and is used to generate display control signals. The display control signals include three visual characteristic signals representing RGB color brilliance changes to the cathode ray tube a2 for displaying the stored image on the surface 21I, and a set of vertical displacement signals for commanding the vertical displacement of the displayed pixels. Contains. Braun tube 2
2 is a precision in-line (PIL) that fires three parallel electron beams in a plane parallel to the horizontal raster scan order.
He has a gun. The brightness adjustment and horizontal sub-vixel deflection circuit 20 displaces each pixel in the X or horizontal direction by seven pixel increments according to the two-bit magnitude of the sub-vixel X address data received from the frame buffer memory 16. As the raster beam scans the surface 211 of the cathode ray tube at a uniform speed, the displacement of the subvixel of a given pixel can be changed by varying the time at which the 24 bits of RGB color information are actually added to the color intensity adjustment of the cathode ray tube 22. Can be controlled. To move a pixel to the left of its normal position, the corresponding data is applied to the cathode ray tube 22 somewhat earlier than usual; to move the pixel to the right, data is applied to the cathode ray tube 22 somewhat later than usual. . A raster deflection control circuit 26 is connected to drive the cathode ray tube 22 in a regular raster scan, with X and Y subbixel addressing superimposed on the normal raster scan of the electron beam over the face 211 of the cathode ray tube 22. not affected by

Vertical sub-vixel displacement of the scanning electron beam is achieved by a small horizontal magnetic field. Four pairs of one-turn windings are placed below the normal deflection coil of the cathode ray tube 22. 1st of 6 pairs
The windings (four parallel one-turn windings) are placed on one side of the cathode ray tube 22 in a coaxially wound relationship between the existing deflection yoke and the funnel-shaped portion of the cathode ray tube, and are arranged in six pairs. Second
The windings are similarly placed on opposite pieces of the cathode ray tube 22.

By connecting only two turns in each winding in series, a very low impedance, fast response sub-vixel deflection device is obtained. This configuration also increases sensitivity by allowing the low reluctance magnetic return path of the main vertical deflection device to be used in a sub-vixel deflection device.

The nomenclature for sub-vixel addressing is driven by the need to minimize the bits of storage required to represent each sub-vixel address, the need to avoid representing negative numbers, and unidirectional sub-vixels with small steady-state values. Complicated by the need for vertical displacement currents. To meet the conflicting requirements, different reference axes are used at different points within the image generating device 10.

Within the image generation and storage device 12, a world XYZ coordinate system is used with the origin at the center of the image. An image is stored as a display list in which the image is represented by a list of individual line segments of standard shapes, such as straight lines or circular curves. A line segment is defined with a resolution of several bits for each axis in a three-dimensional Euclidean space.

In many cases, only a portion of the display list, that is, a window, is displayed on the surface 211 of the cathode ray tube 22. When transferring the display list from the image generation and storage device 12 to the digital vector generator ill, the parts of the list outside the selected display window are excluded and the transformation to the display coordinate system is performed by the digital vector generator ill. This is done by i4. The display coordinate system has its origin at the upper left corner of the display image, with the positive X-axis extending to the right and the positive Y-axis extending downward.

This arrangement is the same as the non-interlaced rask scan used to draw the displayed image onto the surface 211 of the cathode ray tube 220.

Using two bits each to define the X and Y sub-vixel addresses results in four discrete sub-vixel address locations in each dimension for each pixel. The four stages are numbered in the binary order 00, Ol, 10.11 from top to bottom in the Y direction and from left to right in the X direction. A value of 10 is assigned to normal or background sub-vixel locations.

This allows a given pixel to be selectively shifted by 1 or 1 pixel increments to the right (or up) or by 7 pixel increments to the left (down).

In the X direction, the sub-vixel address adjusts the starting time (or left edge) of the pixel. This location can be varied by starting pixel display slightly earlier or slightly later. However, in the Y direction, a special sub-vixel deflection coil must be added and driven with a sub-vixel deflection current.

However, realizing a bipolar deflection current with an extremely high frequency response is expensive. For this reason, the sub-vixel deflection coils and currents direct the pixel to binary 00.01.10.1
1, respectively, is implemented to deflect vertically upward by 0, -- or 7 pixel increments from the normal raster scan position.

When there is no negative sub-vixel deflection current, a sub-vixel deflection of 7 is set as the normal background position. The effect of this is to shift the entire displayed image upwards in the vertical plane by Y pixels. This is transparent to the observer and the steady state current required to drive the sub-vixel deflection coils is relatively small. Each given pixel can be shifted i pixels below, above the ground element, or one pixel above the background position. These actual physical locations, in turn, match the sub-vixel address commands, although this requires conversion between addresses and sub-vixel deflection current commands.

These conditions are summarized in Table 1 below.

Table 1 Displacement Sub-vixel address Current command upper 1/2 00 11 upper l/4
01 10 Zero 10 01 lower 1/4 11. o.

As can be seen from Table 1, the conversion from the sub-vixel address to the current command is exactly logical inversion. It will be recalled that point zero in Table 1 actually corresponds to a vertical upward displacement of 7 pixels relative to the pixel's normal deflection coil location.

Vertical sub-vixel deflection circuit 28 receives two bits of Y sub-pixel address information from frame buffer memory 16 via brightness adjustment and horizontal sub-vixel deflection circuit 20, and selectively drives the vertical sub-vixel deflection coils in response to that information. do.

Color map RAMI! ! , brightness adjustment and horizontal sub-pixel deflection circuit 20 and vertical sub-pixel deflection circuit 28 form a display controller 30 that drives cathode ray tube 22 to control the visual characteristics and position of each visual pixel of the displayed video image.

Brightness adjustment and horizontal sub-pixel deflection circuit 20 and vertical sub-pixel deflection circuit 'in the display control unit 0'
52 forms a video output subsystem 52. Video output subsystem 52 includes frame buffer MEMO!
J l 6 and 0 knee h: operates to repeatedly update cathode ray tube 22 with information received from y-mask RAM 1g to maintain a continuous visual display.

For pixels defining lines and edges, the sub-vixel addresses can be changed from the normal 2.2 value as needed to reduce 9 aliasing giving smoother edges. Therefore, by moving the pixel where the sub-vixel address value of 0.0 is displayed vertically higher by half a pixel distance and horizontally to the left by half a pixel distance, the sub-vixel address value of 1.2 is moved. The value of will move the pixel by a distance of 1 pixel to the left without changing the normal vertical displacement. A value of 2.2 is the normal display position, and a value of 5.0 moves the pixel horizontally to the right by a distance of 1 pixel and vertically downward by a distance of 10 pixels to the normal background display position. Move against. The X and Y subpixel addresses independently control horizontal and vertical deflection, allowing each pixel to be selectively deflected either horizontally or vertically, or both, by a selected ten pixel increment. You will find that there is.

The endpoint of the vector is always positioned with a deviation of (2,2). Due to the nature of the digital vector generator, the address between the final and final imaginary is always (n,2) or (2,m) depending on which axis is the major axis. The long axis sub-vixel address is always chosen to be 2.

Referring now to FIG. 2, the brightness adjustment and horizontal sub-vixel deflection circuit 20 is shown in somewhat simplified form. Since frame buffer display architectures are well known, most of the conventional circuitry required to access the frame buffer memory 16 in raster scan order, read out the pixel data, and illuminate the surface 211 of the cathode ray tube 22 with the pixel data. was not clearly indicated. Only the portion of the deflection circuit 20 relating to horizontal and vertical sub-vixel deflection of normal pixel display positions is shown in detail.

A timing control circuit 40 generates mask timing and synchronization signals for the operation of monitor Ill, including cathode ray tube 22. These signals include synchronization signals that are conveyed to deflection control circuit 41I, which controls the mask scanning of the beam across plane 211 of cathode ray tube 22 in a conventional manner.

In this example, a set of magnetic deflection coils +16 generates the usual mask display pattern, but other deflection means could be used, such as electrostatic deflection plates or other display techniques.Timing and Control Circuit IIO is color map RAM1
It generates a pixel clock rate signal of 35 MHz that is used to synchronize the color intensity and sub-vixel address data received from the frame buffer memory 1G and the frame buffer memory 1G. Timing and control circuit IIO also. ! 15M
Generates a signal gcLK that is used to launch luminance and sub-vixel address data after processing in a pipelined configuration at the H2 pixel clock rate. The timing and control circuit IlO also provides a set of four timing signals To-T3 at a 35 MHz pixel rate but with a relative phase relationship displaced by ten time intervals (75 nanoseconds).
to control the time at which the color luminance data is applied to the cathode ray tube 22, ie, the exact one-pixel horizontal position of the corresponding video pixel image.

■Latch lI8 launches 24 bits of video luminance data of five colors in response to a clock signal of 53 MHz, while
, Y latch 50 latches 4 bits of X and X sub-vixel address data;
All 4 bits immediately before the X sub-vixel address data are latched.

The horizontal control ROM 5G receives the sub-vixel address information of the current pixel and the previous pixel as address input and output horizontal displacement control information, and determines an effective sub-vixel address command in response to the information. Horizontal control RO
The X-sub-vixel information output by M56 represents the unaltered passage of the current X-sub-vixel address information. However, the X sub-vixel address information output by the horizontal control RO'M 6 is such that the previous and current X
, represents a selected mixture of X sub-vixel at I/s offsets.

Many existing devices handle the break that occurs when two intersecting lines attempt to share a single pixel by displaying it as a weighted average of the colors of two or more of the pixels; It attempts to divide the pixels in proportion to the portion of the pixel that is theoretically aged by each color. This color mixing tends to degrade the overall dynamic resolution of the display and is aesthetically unsatisfactory for color mapping devices that have a limited continuity of different colors.

When attempting to dynamically blend two intersecting lines or edges with different edges, the horizontal control ROM 56 creates an aesthetically pleasing image while preserving the full dynamic vision sharpness and resolution of the imager. The sub-vixel addresses of adjacent horizontal pixels are used to set the spatial boundaries between pixels. In general, the pixel edges of lines or boundaries are treated as dominant;
The discordant background pixel edges are moved to match the sub-vixel deflection of the line or edge pixels.

Tables 2A-2D show the horizontal control ROM 56's responses to previous and current sub-vixel addresses YI YOXlX0. Xp and Xc are the decimal values of the previous and current sub-vixel address pixels (XiXO). yp and Yc are the decimal values of the previous and current sub-vixel address bits YI YO.

Table 2A yc and yp42 Xc 1 1i22 3223Table 2B Yc=2. Yp42 Xc 1 1122 La 2255 Table 2CYc42. Yp = 2 XC11112 Table 2 D Y c - Y p = 2p I'm sure it will. Such a pixel may therefore be placed in the background or infill, although a two-subpixel address may occur at the boundary of a line or border if the best position of the bounding dot simultaneously happens to be a normal background position. It tends to indicate location. In any case, the current and previous pixel X
2 from sub-vixel address (Yl, YO=1.0・
The absence of a value of .

In Tables 2A-2D, each row corresponds to a current X sub-vixel address value of θ~5 in decimal numbers, respectively, in order from top to bottom, and each column corresponds to a current X sub-vixel address value, respectively, in order from left to right.
Corresponds to the previous pixel X sub-vixel address value of 0 to 3 in decimal notation. Looking at the raw diagonal of the array shown in Table 2A,
It will be noticed that if both the current and previous pixels have the same sub-vixel address, the output address from control ROM 56 will be the same as the input.

If the previous and current pixels do not have the same X sub-vixel address, the effective X address of the current pixel is approximately the average of the is output as

At this point, it should be appreciated that the X sub-vixel address defines the point at which the left edge of the pixel occurs by defining when the corresponding color intensity data is applied to the cathode ray tube display. - Once a pixel is started, it continues until the next pixel is generated by applying color intensity information for the next pixel to the cathode ray tube display. Therefore, there is no gap between adjacent pixels in the horizontal direction. The width of each pixel is essentially changed.

〇 Horizontal control ROM 56 X subpixel address (X
RI, XRO) are decoded by a binary decoder 58 and then E
It is latched by the X launch 60. ``At the same time, the EV clutch 2 latches the corresponding 24 bits of video color brightness information, while the EY clutch! latches the corresponding X sub-vixel address information Y1, YO that has passed through the horizontal control ROM 56 unchanged. A multi-blephr 66 receives the decoded valid X sub-vixel address information and four sequentially out-of-phase timing signals TO-T5 and, in response to these signals, determines the occurrence time 1 . Thus, a pixel start clock signal is generated which effectively defines spatial positioning.

When signal pixel start occurs, latching ■DA06
Three 8 pins in the circuit called g) DA
Converters (one for each of the red, green, and blue color components of the video signal) receive and latch the color intensity signal from EV clutch 2. These latched color luminance signals are immediately converted to corresponding analog voltages and sent to the cathode ray tube 2.
2 color brightness control inputs immediately command the display of all latched video information. At the same time, the signal "pixel start" causes Y deflection latch 70 to receive and latch the X sub-vixel address information from EY latch 6II.

A DA converter 71 generates an analog signal on conductor 7 indicative of sub-vixel displacement in response to the digital Y, YO sub-vixel offset signal output by Y deflection latch 70. The DA converter 71 is essentially an X sub-vixel
Performs the logic conversion necessary to convert the address signal into a deflection current command signal.

An amplifier 72 with four output stages is responsive to the analog deflection signal on conductor 71 to cause a current proportional to the signal to flow through the four coil pairs. A set of low inductance sub-vixel deflection coils 76 having four one-turn coils on each side of the cathode ray tube 22 selectively deflect the scanning electron beam vertically upward from the normal mask scan position by means of the current output of the buffer amplifier 72. Driven. The eight coils generate a uniform horizontal magnetic field across the five electron beams from the PIL gun of the cathode ray tube 22.

This results in equal vertical deflection of the five beams.

As previously mentioned, negative sub-vixel address values are eliminated by using a sub-vixel address value of 2 as the normal horizontal background position and a sub-vixel address value of 2 as the normal vertical background position. This background address value corresponds to a vertical offset of ten upwards. The location of the displayed image can be moved up or down from this normal background position perpendicularly to the image information bias position. In order for the vertical sub-vixel displacement of a given image to match the occurrence of the left border of the image at the time the corresponding video data is latched by the DA converter 6g and available for full control of the display device, amplifier 7
2 and the deflection coil 75 must match the response speed of the color brightness adjustment circuit of the cathode ray tube 22. This response speed is very fast, so one turn of coil 7
6 is used to reduce its inductance so that the response time of the sub-vixel vertical deflection device can match this very fast response of the brightness adjustment device. During the band of the amplifier, sub-vixel vertical deflection can be adjusted at the time of manufacture to synchronize with the brightness adjustment.

As shown in FIGS. 1 and 5, the digital vector generator 111 operates in response to vector restriction information received from the image generation and storage device 12 to generate video images of vectors restricted by the vector restriction information. A multi-bit digital word of pixel data representing a pixel is generated. The digital vector generator 111 has an input data bus RDPIN 90 and an output data bus RDPOUT.
92i raster display processor (RDP) 110, each data bus having 16 parallel data conductors along with a control conductor, raster board buses RBOUT l 5-096 and RBIN15-
These rasterboard buses interconnect most system components of the image generation and storage device 12. RDP input data bus 90 is connected to bus RBOUT 96 through buffer 94, while RDP output bus 92 is connected through buffer 98 to bus RBIN 100. Included within raster data processing unit 110 is a 16KX 16 data memory for storage of object and vector specific data and work operands. 16 data conductors and g
A message bus with book control conductors provides communication between the raster data processing device 110 and the image generation and storage device 12. Via the RDP input and output buses 90, 92 and their extensions RBOUT 96, RBINloo and control lines, the raster data processing device 110 (see FIG. 5) is connected to the visual characteristic pixel data generation portion of the digital vector generator 1. It has communication access to 112 individual registers and memories.

The raster data processing device 110 receives the image restriction list from the image generation and storage device 12 and sends the image data generator 11 to the image data generator 11 .
Processing these lists to obtain the data necessary to perform the initial establishment of 2, image data generator 112 generates the actual pixel data, including dynamic color and intensity visual characterization for each line vector. The image data generator 112 essentially operates between only two endpoints that limit a single line vector at any one time. Raster data processing unit 108 decomposes complex image segments, such as vertex-defined, filled tubes or empty polygons, into line vector representations. Typically, each object is represented by a series of filler vectors that define the interior of an object, coinciding with a series of boundary vectors and raster scan lines that define the perimeter of the object. Pixel data generator 12 is then used to generate the actual pixel data values and their display location addresses for these line vector displays.

The pixel data generator portion 112 of the digital vector generator 11I includes a digital vector generator control circuit j1i31111'i, which circuit 114 moves certain decoding, timing signals and data from one location to another. All control signals are generated to clock and enable the various registers, memories, and other circuit components of pixel data generator 112 for this purpose.

These data transfer techniques are conventional and have not been described in detail for clarity. However, the main control signals and important timing relationships that enable proper operation of vector generator 112 are specifically described.

The digital vector generator 14 is connected to the DVG bus 11.
The frame buffer memory 16 is connected to frame buffer memory 16 by a large bandwidth bus designated 6. DVG bus 116
The set of 79 main conductors that make up the 54 data signals DV
GDAT 55~0.16 address signal DVGAD
Chip selection signal DVGC823~ of DR15~0124
0 and 5 frame buffer memory selection signals FB
MSEL li~ol is configured to communicate. All but the data signals are actually addressing signals. The frame buffer memory select signal allows selection of the color component of frame buffer memory 16, Z buffer 16ai, or color map RAM 1g and two single bit overlay components. The data signal is the Z buffer 16a data DVDGD
AT 35-I 16 bits of Pi, overlay memory data DVGDAT 2 bits of 17 to 16, X
, Y sub-vixel address data DVGDAT 1
5 to 12, and 12 bits of main 7vme buffer memory 16 data D V G D AT 11 to 0. Conventional control and clock signals also pass through the DVG bus conductors.

A raster data processor 110 is connected to the DVG bus 116 to provide complete control of the raster data processor 110 over the contents of functions such as frame buffer 16.16a initialization and diagnostic analysis. During video display generation, image data generator 112 communicates pixel spatial addresses and visual characteristic information to frame buffer 16.16a over DVC bus 116. Bus RBOU
T96 and RBINloo are raster data processing device 1
00 to color map RAM for initialization and diagnostic analysis.
Connect to 1g.

The pixel data generators 112 are each DVGX.

DVG Y, DVG Z, DVG 〒, DVG
J and DVG K include component digital vector generators 118-12. Spatial address generators X, Y and Z 118-120 generate five-dimensional position address information, and visual display characteristic generators, J,' 121-123 generate five-dimensional color and video intensity information. Two sets of generators generate the X, Y, Z space address portion 12
Form a vector generator subsystem 126 with a dynamic color portion 150 at g and J. two parts 128
．． 150 are conceptually similar, but there are differences in their specific implementations.

During shade ink, DVG K1231d interpolates the luminance data between the two end points. Phono
Shading is caused by secondary interpolation occurring between the end points and DV
G I, J and 'i are used. DVGI and J(zD
VG X, Y and 2 dependent on pattern RAM
Generate texture by addressing with i D V G and J.

A dynamic brightness processing circuit 150 connects the generated visual characteristic information to the DVG bus 116 in a number of selectable combinations that provide the device operator with a large collection of selectable operating modes. The pattern shape multiplexer 152 receives the 15 pins T6-0 and J5-0 and selectively outputs 12 out of 1 rabbit to the uniform KX12 pattern RAM 156. This output bit ranges from 15 to 0 when the signal PATTSHPSEL from mode control register 258 is 1;
5 to 0, and the signal PATTSHPSEL is 0.
In this case, ■6-0 and J5-1 are selected. This causes the color selection signals '1 DVG 1121 and DVG J122
DVG 1121 can be balanced or weighted with a full selection of DVG 1121.

The selected 12 bits are pattern RA, M i56
It becomes address focus for. Pattern RAM156
If each task in stores the value of its address, the address input signal is output unchanged to the color/luminance mixer 15g. Alternatively, the address inputs can be cycled at a selected period. If the selected visual pattern is stored in pattern RAM 158 at an address corresponding to a repeating address pattern, pattern R
The AM 156 outputs patterns in a circular manner to provide textured surface effects.

Another degree of freedom for manipulating visual characteristic pixel data is to select either PR7-0 (8 bins from normalization circuit 1511) or 12-bit COL (11-0) from pattern RAM 156 to select the selected combination. 12 pins)'1 DVG bus 116 data conductor DVGDAT 1
It is provided by a color/intensity multiplexer 158 that outputs from 1 to 0.

This makes it possible, for example, to shade or cover the surface with a pattern.

The DVG control circuit 1111 includes a DVG pixel counter 118 having functions such as register selection and generation of enable signals and control signals necessary for the operation of the pixel data sending device 112. The address translation and interleaving circuit 1116 displays the X, Y coordinates [X from pvo xxlg and DVG Yll&;
It takes the Y integer pixel address and converts it to a set of linear addresses that are compatible with all these data memories. A more detailed discussion of the various components of Vector Generator II↓ is provided below.

DV()X11g is shown in greater detail in FIG. DVG XLL8 receives the outputs of the 12-bit Contains 1 to 8 connected 12-bit adders/subtractors. 12-bit amplifier/down x pixel counter 1]
IO is selectively enabled when its count enable input GET is enabled by the carrier output C12 from adder/subtractor 158, which represents the carrier from the most significant bit when adding or borrowing when subtracting. connected to be incremented or decremented. The C12 output of adder/subtractor 158 is XORed with the DELXS I t)N signal to ensure that carries are propagated for additions and borrows are propagated for subtractions. . The counter 1110 is a signal load x counter LDXC
It is connected to be initialized with data from buses RBINII to 0100 under the control of TR, and the signal LDXC
TI() is decoded in the DVG control circuit 1111 from a set of five binary RB destination control signals generated by the raster data processing unit 110.

The 16-bit state
When activated by the signal RDXDVG for reading H, it is connected to place on the 16-bit word '1 RDP output bus 96. This 16-bit word consists of the 12 bits from the X counter 1110 and the 16 bits of the
It consists of the most significant 4 bits XAC0,11~g.

This binding is useful for testing and diagnostic purposes.

The X fraction register can be loaded from the RBINII~0 bus 100 under the control of the signal load X fraction register, LDXFRACl, which is decoded from the RB destination selection signal.
It is made from 1F582 integrated circuit and has three control circuits 5O1S1 and S2 to control its operation. With control power S2 coupled to logic 0, the four available functions controlled by Sl, SO are 00 (output all zeros), 01 (subtraction B-A), 10 (subtraction A-B) and 11 By selectively using these control and transfer data transmitted on the RB I N bus LOO'i (addition), the X fractional registers 1-4 and the It can be initialized with any desired data. For example, the X accumulator register 156 can be cleared by using the all zero output state of the adder/subtractor 15g, then passing any value lx 136. X accumulator register 1
36 After all initial settings, set any desired value to RBIN.
It can be loaded from bus 100 into X fractional register 1311. It can be directly set with data from the pixel counter 11i0i bus RBIN11-0100.

A binary point is considered to be between the most significant bit position of the X accumulator register 156 and the least significant bit position of the X pixel counter 1110.

Thus, during operation, X pixel counter 1110 stores integer X address values, while X accumulator register 136 stores fractional X address values.

X, and X. The two most significant decimal address bits, denoted by
Frame buffer 1 for use in addressing
6 can be conveyed.

-・Logic game) 141 to 1-5 are control signals decoded from the RB control signal, clear accumulator (C11
λACO8) and load X accumulator (LDX, A
CC) and signal, delta X sign (+) ELXS
It controls the operation of the DVG X11g in response to the signals I ON ) and DVG X11g. Signal DE
LXSIGN is generated by raster data processor 110 as the sign of the difference between the end and start points in the X dimension for the vector to be generated.

The sign of this difference is D as the control signal RBDXSIGN is latched to generate the signal DELXSIGN' (5).
It is output to the VG control circuit 1111. This signal is L (logic 0) for a positive sign (addition) and H (logic 1) for a negative sign (subtraction). Data processing device 11
DVG control circuit 11) ↓
The control signal 5TARTDVG continues until the pixel counter 1118 in the vector indicates that all points in the vector have been generated.
is generated by the DVG control circuit 1111 in response to the DVG control circuit 1111.

The so input to adder/subtractor 1-8 is the signal SO=
CLRA, CC3 (LCXACC+DELXSIGN)
Therefore, the signal XSO is input to the X accumulator register 156. Forced low to make an O output to clear by f C1-PACC8. After this, signals LDX, ACC place the adder/subtractor 158 in addition mode so that the contents of the previously loaded fractional register 154 can be added to O and transferred to the X accumulator register 156. It may be determined that Signal DELXS-GN is a direction signal.

When L (positive sign), adder/subtractor 138 is placed in addition mode and counter 11IO counts up.

When H (negative sign), adder/subtractor 1'58 is placed in subtraction mode and counter 140 back-counts.

DVG Y119 is a DVG Y119, except that it is controlled by a Y-dimensional control signal that corresponds to an X-dimensional control signal.
Same as X11g. DVG Z120 has some small changes, but DVG X11g and DVG
Same as Y119. (See Figure 5) Next, to explain Figure 5, the DVG Z120 has a Z decimal register 1511a and a Z integer register 15111.
).

Z12 bit decimal adder/subtractor 13 ga, Z16
It includes a bit integer adder/subtractor 13g, a z12-bit fractional accumulator 136a, and a z16-bit integer accumulator 1112 through ll11G. The operation of DVG Z120 is essentially the same as DVG Xl,18 and DVG Y119, except that the computing power is expanded to 16 integer bits. This reduces the resolution in the Z dimension to 1
The increase to six integer bits allows the digital vector generator to step a large number of integer distances in the Z dimension when operated to create a full video data pixel representation of the vector.

The Z integer register 15IIb receives the decoded control signal LDZ.
It can be loaded for initialization from the bus RBIN under the control of the INT, while the 2-decimal register 131Ia can be loaded from the bus RBIN in response to the decoded control signal LDZFI (AC) to kill 0. DVG shown in Figure 5
The Z circuit 120 is the DVG X circuit 118 in FIG.
It is not configured with an overflow adder counter configuration. To better resolve small angles and distances in the Z dimension, the DVG Z120 was provided with a 12-bit fractional part and a 16-bit integer part. The decimal part is
It includes a Z decimal register 1311a, a Z adder/subtractor 1a, and a 2 decimal accumulator 156at. The 16-bit integer part operates synchronously with the decimal part to process the more significant bit positions and is connected to a Z integer register 13 connected to receive initialization data from bus RBIN15-0.
IIb, II number accumulator 136b and integer adder/subtractor 13gb. All 16 available integer bits can be scaled by the user in a well-known manner to best represent the range of distances in the Z dimension for any given application.

Although the selection of initialization data varies somewhat with the particular mode of operation for vector generator 126, the mechanism of operation of each of digital vector generators 118-123 is as follows:
always remains essentially the same. As a specific example, DV
G X1ll! When using i, each DV0118-125
Save the integer part of the starting vector coordinates to the data memo IJ
Load integer counter or register 1110 from I O6 through bus RJ3IN 10.0. q! r
Fractional register 15II for DvG is loaded in the same manner.

The x7 cumulator register 156 then outputs a signal CLRA to force a zero output from the adder/subtractor 158.
CC8i is cleared by asserting K, and clock signal DVGCLK is asserted. Then, for a digital vector generator where the load accumulator signal (LDXACC) is active to add O to the starting vector coordinates and store the sum in accumulator register 156, it is rounded to -H (binary α001). The value is then loaded into the fractional register and then added to the fractional starting coordinate value for the initial pixel stored by the accumulator. This hundred pixel value creates an offset that automatically rounds the ten pixel resolution represented by the two most significant bits to the nearest ten pixel value. That is, as soon as the incremental value stored in the accumulator passes through the hundreds point, the two most significant accumulator bits will indicate the value of tens, and the value will remain constant until the actual value stored passes through the tonal point. At that point, the two most significant bits indicate the value of wheat. Therefore, rounding is automatically performed to the nearest ten pixels.

The slope of the vector relative to the X or Y axis is then loaded into fractional register 154.

The axes are the FiY axes, which are the X and Y axes, with which the vector to be displayed is closest to parallel.

This is an axis where the angle between the axis and the vector is less than or equal to 45°. If the vector is exactly at the lI5° mark, the X-axis is treated as the x-axis.

Regarding the DVG corresponding to the major axis, all 12
+ and the 1 router value of 1 (1-2) is loaded into the corresponding decimal register. DELSIGN is L (incremental accumulation 1)
- if the carry bit is adder/subtractor 13
can be placed in g. If DELSIGN is H (decrement accumulator), the borrow (L) bit is placed in adder/subtractor 158. This retardation step sets the increment along the light beam axis to 1.

After each DV() is stepped to generate the next value, the resulting value is written to frame buffer 16. The value stored in the decimal register of each DVG is
In this way, the accumulator 13 corresponding to each DVG
6 so that the correct values for each axis can be shown in the DVG output as the device steps in one pixel increments along the line vector. Adder/subtractor 158
When the digits of each DVGIII overflow, the counter 140
For I~119, counter 1110 indicates the integer portion of the image address and X accumulator 156 is incremented (or decremented) to indicate the fractional portion. Each DV0118~
123 includes an adder/subtractor H&A-138b and accumulators 136a, 156b that extend to the integer portion of the resulting vector coordinates.

Next, referring to FIG. 6, the dynamic values DVGI, J,
K121~125i'! :, Space DV011 g~12
0 DVG I, J and 121-12 operate in relatively the same way as 0, but have a somewhat more flexible hardware configuration.
J- and 121-125 are not position vectors but 5
DV, except that it operates with a normal luminance vector of
'Same as GX, Y and Z118-120.

Dynamic value DVG I, J, 121 to 123 are X, Y
, the Z-space DVG l1g ~12 generates all the information defining the visual representation characteristics corresponding to the pixels with the addresses being generated simultaneously. DVG 11 shown in Figure 6
Although the hardware of a dynamic value DVG, as exemplified by No. 21, is more flexible in selecting modes of operation than a spatial DVG, the basic principles of operation are essentially the same.

The 8-bit fractional register 134C58, the 8-bit fractional adder/subtractor 138c, and the 8-bit 1 fractional accumulator 136c are similar to the DVG X118 and DVG Y1, except that the resolution is reduced from 12 to 8 bits.
It operates in much the same way as the decimal part of 19. DVG
For each step 118-12'5, the delta value stored by fractional register 1311cKj is added to the accumulated value stored by fractional accumulator 156c.

However, if the pixel space address is determined by the location of the pixel within a predetermined pixel display array, and at most
The visual properties can change by a value greater than 1 at each step, depending on the object illumination conditions. The integer part of DVG 121 is therefore an 8-bit I integer register 15# (1,8 bit ■ integer adder/
An 8-bit emask that performs all the corresponding accumulator functions of the subtracter 158d and the fractional accumulator 136c.
0D realized by register and accumulator 156d
The VG module 121 can therefore accommodate non-fractional delta increments.

Inside DVG 1121 and DVG J122,
Allows the mask register and accumulator 156d to be effectively frozen or fixed to a value that may be preset to a selected number of the most significant integer vilatra accumulators 136d, while the lower vilatra is executed through a series of pixel-limiting steps. Accumulate and overflow repeatedly. ■Mask register and accumulator1.
The mask register in 56d is connected to the bus RBIN7 in response to the decoded register load signal D S HDMS K.
Receives and stores mask control bytes from ~0100.

Each bit of this mask control byte is
Allows loading of the corresponding bit position in a register. By disabling the loading of a given accumulator register bit, it is frozen and unable to pass a full carry to a higher order bit position. Therefore, the masked bit position and all values above it remain constant, while the lower ranked positions have an integer delta value and carry from the fractional part to it for each DVG. Can be incremented and overflowed when added in steps.

This optional bit freezing feature is available in DVG 1121
and DV() J 122 are particularly useful in conjunction with them when they are connected to address pattern RAM 156 via pattern shape multiplexer 152. In this mode of operation, the pattern stored in a selected number of address locations in pattern RAM 156 can be repeatedly output every 2Q pixels in each dimension, where n is a bit that can be changed in the ■ and J outputs. is the number of DV
C) By setting the same delta values as DVG DVG X and Y (1i
8.119) can be stored in the pattern RAM 156 that is repeatedly recalled in synchronization with performing the increments of 8.119).

For example, if the output corresponds to the Step in the lx direction 2
= Repeat every 8 pixels. Similarly, DVG J
122 generates a Y-dimensional pattern output while allowing 5 pixels to change state, the pattern RA
The Y address input to M156, and therefore the corresponding no-turn output, repeats every 23-g steps in the Y direction.

Therefore, the size and repetition frequency of the pattern stored in the pattern RAM 156 can be controlled by the mask control signal, or alternatively by changing the increment values stored in the 1 and J decimal registers 134c, the -Resistor 156d can control relative pattern size while continuing to control stray frequency. accumulator·
Masking the more significant bits of register 136d,
It can be used as a page address input to pattern RAM 156 to select one of a plurality of pages, each of which stores a different texture pattern in pattern RAM 156.

The absolute value circuit 1117 is the accumulator register 13
6d as well as the most significant fractional bit signal from fractional accumulator 156c.

Sign bit 17 is used as a control bit, while
The seven least significant integer bits and the most significant fractional bit are output as an 8-bit unsigned number. When enabled, the 1 magnitude circuit outputs the received signal if the sign bit is positive (zero) and outputs the 1 of the received bit if the sign bit is negative (1). Print the complement. DVG
and J, the absolute value circuit is permanently enabled. For the DVG K125, the enable input is controlled by the decoded control signal BACKLITE, which selectively enables backlighting effects. During normal operation, either the absolute value of K is selected for backlighting or K is set equal to zero.

Next, referring to FIG.
while the select signal PATTSHPSEL from the mode control register determines which luminance signals can be passed to pattern RAM 156 as address inputs.

If PATTSHPSEL=0, signals 15 to 0 and J5 to JO are selected.0 Otherwise, signals 6 to
0 and J5 to J1 are selected.

FIG. 7 shows the -DVG control circuit 114 in some detail. The DVG control circuit 114 includes a DVG pixel counter 1
48, mode control register 25g, control decoder 252,
Includes execution control flip-flop 2511 and direction control register 256.

In order to start vector generation, the raster data processing device 110 initializes the DVG circuits 118 to 125 as described above, and under the control of the decoded control signal LDDVGCTR, the DVG control circuit 1llI (seventh The start signal S T A RT is loaded with the number of pixel points to be plotted into the pixel counter t11g in the pixel counter t11g (see figure) and decoded from the DvG control signal by the destination decoder 252.
Assert D V ().

The signals STA and RTDVG are the execution signal DVGR at the Q output.
DVG execution execution/holding cleanprop 2 that generates UN
511'i set. Signal DVGRUN, along with the count enable input of 12-bit DVG pixel counter 250, enables operation of each of DVGi1g-12'5. The digital vector generator then automatically steps along the display vector in single pixel increments relative to the clock axis under the control of the clock signal DVGCLK. Then, the current pixel is converted to a digital vector generator LLg~
The position address and dynamic intensity data produced by 125 are used to write to frame buffer memory 16.

As soon as the vector has been plotted, the DVG pixel counter 1118 counts back to zero and resets the execution control flip-flop 254.

R operates to terminate the execution signal DVGRUN.
Activate C output. digital vector generator il
l must then be reinitialized with the data for the next vector, and the signal plate c+vG must be reasserted to begin plotting the next vector.

If the next vector has a first point that matches the previous vector, then that first point will have already been output to the frame buffer 16, and the accumulator register and the , will contain the first coordinate value. Delta value or step value and DVG
Only pixel counter 250 needs to be updated to generate the next vector.

Direction control register 256 outputs six direction control signals RBDKSIGN-RBDXSI in response to signal 5TARTDVG.
GN and the corresponding product signal DELKS I ()N-
0 These signals operate to store the DELXS I GN.
Determine whether the G adder/subtractor operates in addition or subtraction mode. This then determines whether a vector extends in the positive or negative direction for a given dimension.

Mode control register 258 inputs data via bus signal RB.
The three address inputs are connected to bus signal RBI
It is implemented as an addressable latch connected to N2-0. Mode control register 258 is enabled by the decoded control signal L DMODRE G to store data input signals in any addressable register storage location.

Therefore, the eight output control signals can be set to any desired state by register and data processor circuit 10F3.

The DVG/VTC decoder 252 uses the bus RB I N10
It receives six control signals RBDEST O-2, I-6, which are essentially register address signals.

These signals are signaled after the reset signal is not asserted to generate the following 21 active low select signals. The selection signals are LDXYCNTL, S E
TBRDFLT, LDCLT-LIM) 8, L
DPATT, 5TARTDVG, CLRACC8,L
DDVGCTR.

LDSHDMSK, LDKACC, LDDELK,
LDJACC,LDDELJ,LDIACC,LDDE
LI, LDYCTR, LDYACC, LDYFRACl
LDCTRLDXAC'C, LDXFRAC.

The faulty flip-flop 262 decodes the control signal S
gTBRDFLT controls the failure circuit 2011 to generate an alarm signal BROKE'e, and when the digital vector generator 11I is not operating properly, the LED 266
make it brighter.

It will be seen that the contents of the X, DVG integer pixel counter 111O and the X accumulator register 156 can be concatenated at any given time to give the complete The integer part of the address is in the counter 1140,
The 12-bit decimal address part is stored in X accumulator 1.
It's in 56.

Delta value 'lf in X fractional register 1' 511: in addition to the fractional value in x accumulator 136, adder/subtractor 158 whenever the result is a sum greater than 1
The carry output CR goes active high and increments (decrements) the X pixel counter 1110t to point to the next pixel address field P9r. The decimal value stored in the X decimal register 134 continues to be added to (or subtracted from) the decimal value stored in the X accumulator 156.0 for each DVG update -! The integer portions of the X and Y addresses stored in the
and the two most significant fractional bits for Y are DVGDA
It is output to the data bus 116 of the frame buffer memory at T l 5-12. Next, the address
Translate and interleave circuit 1116 (fifth
) converts the integer X and Y values into memory chip addresses for the frame buffer memory 16.

X and Y at 1 indicated by these address values
At the No. 1 location, the dynamic intensity video information derived from the contents of the digital vector generators (DwG) 121-12) along with the X and Y sub-vixel values is stored in the main portion of the frame buffer memory 16. be remembered. Note that the X-dimensional integer and sub-pixel values taken from the Z DVG circuit 120 are stored in the buffer memory 16.
It is stored at the designated pixel address in buffer portion 165a. If hidden surface processing is triggered,
Luminance data is stored only if the two coordinate values of the pixel are considered to be closer to the origin than the data previously written to the pixel X, Y storage location. After storing that data in frame buffer memory 16, vector generator circuits 118-125 are incremented and the next sample intensity and sub-vixel address value is then stored in frame buffer memory 16. It is stored at the next pixel address inside.

To determine when the generation of pixel data for a line vector is complete, raster data processing unit 110 (Figure 1) calculates the number of pixel sample points to be generated and converts this value into DVG Stored in pixel counter 148 (FIG. 7). Each time signal DVGCLK occurs, a pixel data point is sampled and stored in frame buffer memory 16.
and the pixel counter 111g is decremented until it reaches a count of O, at which point the RC output is sent to the execution control flip-flop 25! Reset the signal DV
generates a count complete signal that terminates GRUN and thus terminates processing for the current line vector.Referring now to FIG. 5, the dynamic luminance or visual characteristic processing circuit 150 is connected to the visual characteristic vector generator 1. J, is connected to receive the visual characteristic information from 121-125 and process this information to generate information defining the visual characteristic along the display vector being generated at each spatial pixel point. . The processing circuit 150 is a DVG
7 bits from I circuit 121 and DVC) J circuit 1
pattern shape multiplexer 152 connected to receive 6 bits from DVG 1121 and D
6 pins R from each circuit of VG J122
AM 15 G, and a color/intensity multiplexer 158.

A selected background color pattern, such as a dashed line pattern or a background color window for inserting discrete data, can be generated by initializing frame buffer memory 16 to the background color before vector generation begins. A pattern of zeros is then written to pattern RAM 156 at the pattern storage location where it is desired to display the full background color. Zero detect circuit 166 detects this zero value output data and responds by terminating the active state of signal DVG write enable (DVGWB). During phono shading operation, D
It operates to convert VG I, J and K121-123 into a single Mized value representing them. During this mode, the signal PATT from mode control register 258
Pattern RAM for EN to ensure constant color output
156. Next, referring to FIG.
The raw 4 includes a B ROM 190, an A ROM 192, and an adder 1911. The 0 adder 'l 91+ is
ABSK7~0 from A AR7~A from ROM192
It is summed with the RO output and outputted as PR7 to PRO'i.

The normalization circuit 1511 calculates the formula % formula % (
1) Estimate the size of the phono shedding algorithm while optimally using economically available precision by: N is the modified luminance component parallel to the axis. N is calculated from the values in the interpolator, J.

[] The first term in parentheses is algebraically treated as an unsigned positive decimal value with a decimal point immediately to the left of the interpolated value of K.
1121 and DVG J122 as address inputs, and accordingly I”+
Output J2'i. The outputs BR7-BR2 are limited to a maximum value of 0.999, regardless of the input value, in order to maintain a maximum number of significant figures and a simple hardware combination.

A ROM 192 receives as its six most significant address inputs six data bits D representing BR7-2 (the six most significant pins of the function of B ROM 190).
Receive 5-0. A ROM 12 still has a brightness signal ABSK as its six least significant address bits.
A N D gate 1 receives a single gate signal PH0NGSHD from 7-2 and mode control register 160.
91 output is received. A ROM192 outputs AR
7 ~ As ARO, the correction term [K / (Eng.2-1- J2+
K')! AK] is generated. 8-bit adder 1
911 has output ABSK 7 to 0 and A ROM19
2 output and the sum is the 2nd communication signal PR7~
An output Tqy, represented by PRO, is generated.

Next, referring to FIG. 9, color/luminance multiplexer 1
5F! is the signal COi,' from the pattern RAM 156
11-0 and signals PR7-0 from the normalization circuit 1511
and converts these signals into mode control signal MIXMO.
DE Binary count of 3-0 0-5 [j: Selectively combine in one of the six modes determined. buffer 5
110 receives a selected group of 12 signals among these signals and outputs them as signals DVGDAT 11-0. Buffer 3' lj O also receives four X and Y sub-pixel address signals and assigns them '1
The iDVG data signals DVGDAT 15-12 are outputted to the frame buffer memory 16.16a.

Quad 2:1? Lunaplexa 55
0 receives signals C0L11-g as inputs B, and receives signals PR7-1I as inputs. multiplexer 350
selects one of these inputs as output according to control signal 5EL2, and the output signal is output from bin) DVGDAT.
It can be connected to the buffer 5IIO to supply 11 to gl.

Decoder 352 receives signals MIXMODE 5-0 and generates color/luminance multiplexer 158 control and selection signals accordingly. Signal SEL2 is decoded to a low level and remains in PR7 to 4AR7 only during mode 50.
Select above. Therefore, signals DVGDAT 11-B represent C0L11-8 in modes O through 4, and C0L11-8 in mode 5.
The 0 signals DVGDAT7-4 representing PR7-11 are generated as the output of one of the two 5-state multiplexers 51+2,557. Multiplexer 557 has quad l! :J multiplexer, and multiplexer '51I2 is a quad 2:1 multiplexer.

The output enable input to multiplexer 357 is connected to signal MIXMODE 1, while the output enable input to multiplexer 31i2 is connected to signal MIXMODE 1.
Connected to El. Therefore, multiplexer 511
2 is active during modes 2 and 50, while multiplexer 557 is active during modes 0-1.4 and 5.

The decoder 352 generates a mode 2 open signal SEL0 low level and provides signals C0L7 and PR7-5 in place of the signals DVGDAT7-1I. During mode 5, signal 5ELO is generated high to select the B input and connect to signal PR7-ll: signal DVGDAT7-11.

Decoder 552 generates signals 5EL3, qt to indicate mode 0.
1. Select one of the four inputs A-D to multiplexer 57 between 4 and 5.

During mode 00, human power A is selected to couple signals DVGDAT7-ltK to signals C0L7-5 and pR7. During mode 1, input B is selected by signals C0L7-6 and PR7-6. During mode 4, input C is selected with signals C0L7-ll, and during mode 5, inputs C are selected to provide signals PR5-0.

The four least significant pins) 'DVGDAT 5-0 are the B inputs connected to receive signals C'OL3-0 and 4
It is connected to buffer 3110 by a quad 2:1 multiplexer 311g which is connected to the output of bit shifter 3111j and has a pc-A input. The SEL B input to multiplexer 34g is decoded to a high level, and between modes 4 and 50, the B input and signals C0L5 to
Select 0. During modes O through 50, signal 5EL5 is f-E at a low level and selects the output of chic 51111.

Shifter 51114 receives signals PR6-0 as inputs. The shift control manual to the shifter ll1l is responsive to the signal MIXMODE 1.0 to the output during mode O, in response to the open signal PR6-3 in mode 1, in response to the signal P5-2 during mode 20, And while in mode, signal PR5
~Respond OK.

Table 5 collectively shows various modes and signal combinations.

Table 5 MIXMODE DVGDAT 11-817/(XI
AT7-11 DV (D'1lT3-00000 CO
L 11-40OL? -5,PH1PH1-'5000
1 COL 11-g C0L7-6, PH7-6PH
1-20010' COL 11-8, 0OL? , P
H1-5PR1+-100110OL 11-8 PH
7-4PH1-00100COL 11-8 C'0L
7-11 0OL3-00101 PH7-1i P
H1-OC0L3-0 Next, referring to FIG.
06 race are both shown. The mask control for the digital vector generator 111 and the RDPIIO is configured in the usual way, with a controller of 291o and a controller of 14KX6.
11 microcode memory along with conventional decoding circuitry. Microcode controller 270 provides six mode control signals MODCNTL 5-0 that are used to control several different functional circuits throughout digital vector generator ill. These signals are conveyed to the data bus in a similar manner. For example, during execution of a clock generator initialization routine, a selected set of clock speed control signals are placed on the MODCNTL line and loaded into the clock generator control register. In a similar manner, the RDP mode register, box test control register, shift control register and multiplier control register can all be loaded sequentially for selectable control by the RDPIIO. Most of these mode control registers are used in a conventional manner and are not explicitly shown in the drawings.

Direction control register 256 (FIG. 7) is one example of such a control register. In this case following the calculation in RDPIIO, the three least significant bits MODCN
TL 2 to 0 are ALU2 output sign bits ALUDAT 15 (FIG. 10) to direction control sign register 2.
Used as a bit selection address to load into 55 selected bit positions. Each bit position is stored in the RBD by direction control latch 256 (FIG. 7).
Generates an output that drives one of the SIGN control signals.

The microcode controller 270 also outputs a set of source selection signals DATAMEMSRC8EL 7-O and a set of destination selection signals DEST 5-0.

These signals are passed to control decoder 252 to generate source and destination selection signals for pixel data generator 112.
RBSRC8EL 2~ decoded by (Figure 7)
0, RBDST 2-0 and group) BET balls 6-II are generated. These signals normally indicate that during a bus transfer, the destination register ti is to be strobed to remove data from the bus, as well as the register or memory that is to be allowed to place data on the bus. used to give instructions. 611 more destinations by applying the six destination signals in a two-step order, first selecting one of the plurality of decoders and then providing the code to be decoded by the selected decoder. A selection signal can be created from the signals DESTSEL 5-0.

Other control signals control the functions performed by the arithmetic unit (ALU) 272.
FNSEL 5-0), A and B ALU source select 27-0 (ALUSRC8EL)
27-0), defines the source of data applied to the inputs of the A and B portions of data memory 106;
8EL '7~0) and signals that control the operation of the data memory 106 Data memory control 6~0 (DATAM
EMCTRL 6-0).

In addition to the A and B ALU data buses 27II and 276, the RDPIIO main bus structure includes data memory 106
The human power of the A part of the memory A data bus 178 connected to the output port and the human power of the B part of the data memory 106 /
MEM B data bus 280 connected to output boat
Contains.

Message bus output interface circuit 2g2 is MEM
It provides an output connecting between the B data bus 280 and the message bus which connects to the digital vector generator 111'ii - image generation and storage device 12. memory·
A buffer input interface circuit zgq provides the input connection between the message bus and the MEM A data bus 27g. The message bus is 1 marked MBDl 5-0.
It includes five data lines and eight control lines labeled MBC7-0. AALU data bus 271I passes through RDP output data bus 90 to RDP input data buffer 9.
11 and serves the pixel data portion 112 of the digital vector generator 111.
15-096. Similarly, MEM
The B data bus 280 is connected to the RDP input Cadeca data bus 92.
The image data generation part 112 of the digital vector generator III is connected to the RDP output cover couch 98.
Connect to RB engineering N 15-0 bus 100.

A digital vector generator power/output interface 286, which includes a refresh controller for frame buffer memory 16, transfers data from digital vector generator bus DVGBUS 78-0 to A, ALU data bus 2711, and MEM o DVGBUS 78~0 connected to transfer data from B data bus 280 to DVGBUS 78~0.
0 is the data portion DVG connected to the output of color/luminance zeltiplexer 158 and frame buffer memory 16
DAT 15-0 and the output of address translation and interleaving circuit 146 and address portion DVGAD connected to memory buffer memory 16
DR15~O't, &tr. Data for two buffers 16a subvixel addressing storage and two overlay storages in frame buffer memory 16 is carried by data lines DVGDAT 33-16.

The arithmetic unit 272 is connected to the eight-person power'1 AALU data bus 2.
711 , the B input is connected to the B ALU data bus 276 , and the Y output is connected to the MEM B data bus 280 . 16X16 multiplication circuit 290
has its Y input and lowest product output connected to ALU data bus 271+, and its X input connected to BA and LU data bus 2.
76 and has its top product output connected to MEM A data bus 278 . Multiplier circuit 290 and arithmetic unit 272 together provide a program controlled ALU control circuit iog'4 with sophisticated high speed computing capability for rapid manipulation and transfer of vector data. Division search R
O'M292 provides fast division capability and its address input 'i' is connected to the MEM A data bus 278 and its output i
A Connected to the ALU data bus 2711. 1
A 6-bit data register 2911 connects between the MEM A data bus 278 and the 8 ALU data bus 2711. Similarly, a buffer 296 connects between BALU data bus 296 and MEM B data bus 280. 16-bit register 298 is MEM
Data is connected in the opposite direction from the B data bus 280 to the BkLU data bus 276. Immediate data buffer 500 stores 16-bit data f! :29i.

Microcode controller 270 connects to B ALU data bus 276 to connect microcode controller 270 to
can be placed directly on the data 'jii7B ALU data bus 276. The clock generator 302 receives mode control signals MODCNTL 5 to 0 from the microcode control port 111g270, and accordingly generates the mask system control clock signal, frame buffer memory clock FBMCLK, digital vector generator clock DVGCLK, and raster data processing. A device clock RDPCLK i is generated. Buffer 301i is ME
MA data bus 278 and MEM B data bus 2
Direct two-way communication is performed with 80.

The A address control circuit 306 is the MEM B data bus 2.
It receives address data from gO and generates an address signal for addressing portion A of data memory 106 in response. Similarly, B address control circuit 30g receives address information from MBM B data bus 280 and responsively provides an add signal to recall portion B of data memory 106. Message bus DMA
Times 1i! 25'5t.

is connected to the address outputs of the microcode control circuit 270 and the A-address control circuit 506 through control signals not explicitly shown in the drawings.
It is possible to access interview memory and transfer data to LO using the normal method.

A shift circuit 512 is connected to the inputs iA ALU bus 274 and BALU bus 276 and has an output connected to the 16-bit MBMB data bus 280. The shift circuit 312 is actually a 16-bit) AALU bus signal 2.
7L'i concatenated as the top term and 16 on bus 276
bit) BALU bus signals are concatenated as the least significant word and selected groups of 16 bits of these signals are enabled by the enable shift signal ENSHAFTK, the 4-bit shift command SHFN
Shift to output according to UM 5-0.

If SHFNUM 5-0 is 0, the contents of A_ALU bus 27# are shifted to IiEMB data bus 213o. Signal SHFNUM Each time the shift control number expressed in 5 to 0 increases by one, the signal on the connected bus is changed by one.
The signal ALU from the ALU bus 2711 is shifted to the left by a maximum of 15.
AO is displayed at the top focus position, and the signal ALU
B15-1 are output to lower bit positions.

Shift circuit 512 thus provides a mechanism for converting the independent signals on A and B ALU buses 2711 and 276 into selected groups of concatenated combinations thereof.

As a means for the normalization circuit 314 to improve the operating speed,
Facilitates hardware adjustment of advance points.

It detects the number of leading zeros present in the - signal on the ALU A bus 2711 and generates shift control signals SHFNUM 5-o1 accordingly. These shift control signals are transmitted to the shift circuit 512, which also sends the ME
M A data bus 27 F! Can be connected to VC.

A box test circuit 316 receives the most significant ALU output data bit ALUDAT 15, which is the output sign bit, along with the mode control signal MODCNTL 2-0 and the enable signal to determine whether a set of values is within a certain range. Operate. It is particularly useful for determining very quickly whether a vector is within a selected spatial range. Below we describe some examples that demonstrate the implementation of the invention.

Example 1: Prior Art--Normal Integer Pixel Addressing Consider the line vector 200 shown in FIG. 11 in the X, Y, Z Cartesian coordinate grid representing the surface 211i of n cathode ray tube 220.

The line vector 200 has a starting point (3, +10.2.75.1
) and endpoints (8, 85, 4, 22, l).

An integer X value is considered to define the left bound of a column of base or background pixel locations, while an integer Y value is considered to define the lower bound of a row of pace or background pixel locations. . In other words, each pixel is identified by the location of the pixel's upper left corner in FIG.

The raster data processing unit Mj, xo first rounds the start and end points to (5, u, 1) and (9, '14, 1), and then initializes the digital vector generator as follows. By comparing the difference between the rounded and X coordinates, X is determined to be the principal axis since ΔX is greater than ay. A distance 9-1=6 along the X-axis is then calculated and stored in pixel counter 11I8 (see FIG. 7). The X counter 1110 (see FIG. 4) is initialized to 5, the X accumulator 156 is initialized to α000, and the X fractional register is initialized to 0.999.

Since DVG
Step in increments of .

a) (is calculated as X=9.0O-1=6, and JY is 14
, 00-3.00 = 100. The initial small aY value (0, -000) is then stored in the Y accumulator and the slope ΔY/ΔX=O, L67 is stored in the Y fractional register. The initial integer Y pixel value is stored in the Y counter.

Similarly, the initial integer Z value (1) is stored in the Z integer accumulator 116b, the initial decimal 2 value (0) is stored in the Z decimal 7 accumulator 136a, and the ZM slope Δz/Δ
x=o is stored in 2 decimal register 131Ia and z integer register 131Jb. This zero slope value prevents the Z counter from incrementing and outputting a Z value of 1 at each pixel location along the full line 170.

Table 4 below tabulates the values generated when DVG X, Y, Zllg ~120 is stepped along line vector 200.
It is not used to determine pixel location, but is included for ease of reference. What we notice from Table 4 is that the value of Y stays at 5, 19, and then jumps to 4 at the end of the vector. When counter 250 counts back to 0, the operation is complete and the device is ready to reinitialize for the next generation of line vectors 0 4.000 3.167 t, oOo 55
．． 000 3.5314 1.000
116.000 3.501 1000
57.000? +, 6611! 10
00 28.000 3.855
1000 1'1000 11.002
Looo 0 Example 2: Sub-vixel according to the present invention
Addressing. Similar to line vector 200, but with
Consider line vector 202, except that it has been translated by 10 pixel positions along the axis. The line vector 202 is
(13,40,2,75,1) to (1a85.4.2
2.1). At ten pixel resolution, these points are (15, 50, 275, 1) and (1B, 75.
4.25.1). The raster data processing device 110 calculates the pixel values of these initial points together with the visual characteristic value (shading in this example) and calculates their iD
Stored in V011g-125.

The actual display coordinates for the endpoints of the line are determined by rounding each endpoint to the nearest integer pixel location within the display. Then 0.625-%→-tub is added to the rounded integer value. The % component of this value assigns a 2×+ background subpixel address value to each endpoint, while the Allowing rounding to the nearest ten pixels.Assigning each endpoint of a line vector to an integer pixel location with a 2,2 sub-pixel address value is
Ensures that the connecting line segments match properly without visible discontinuities.

In this example, each rounded end point is
Integer (2,75+0.5) = 5Z initial - = LO K initial = Integer (27 + 0.5) = 27X final - Integer (
18,85+0.5 )-19Y final = integer (4,22
+0.5) = 4Z final -10 final; determined as integer (17+o,5) = 17.

Z dimension values retain their exact integer and decimal values.

Next, calculate the difference value from the end point display position. ΔX=1 9-1 5=6 ΔY=11-3=1 ΔZ=LO-LO=0 Calculate as.

Since ΔX is clearly the larger value, the X axis is selected as the main spatial axis.

In this example, the luminance at the first point is 29 and the luminance at the final point is 17.
d) Let us further assume that shading should be used. In this shading mode, the DVG
K12'5 is used to generate the visual luminance value and is connected to logic zero AND gate 1 of normalization circuit 1511 (FIG. 8).
is disabled with signal PH0NGSHD at 91 to provide zero at the B input of adder 1911, such that the output is simply P]'(7~0=ABSK7~0.

The pattern shape multiplexer 152 receives the signal PATTE.
Disabled by N=0, causing address 0 to be provided to pattern RAM 156. Any desired hue can be stored in this location. Color/Brightness Multi-Flexa 1
5g, 12 bits of visual characteristic information stored in the frame buffer memory 16 are PR7-0 and C0L11.
It is preferable to set the mode to 5 so as to include 8 to 8. In the case of Gouraud shading, a linear interpolation is made between the beginning and ending intensity values of the vector to be generated. Δ is determined to be ~17-29--1'2.

ΔX remains 60, and the color luminance gradient Δ/ΔX=-
It is 200.

In the initial configuration, the pixel counter 1118 is set to a delta value of 6 on the major axis (Xl). DVG Xl 1 F!
VC writing case is available. Since X is the major axis, 099 delta values are written to fractional register 134.

DVG Yl19 writes 5 to counter, o625
is written to the accumulator register, and
It is initialized by writing X=1/6=0.1667' into the decimal register. DVG Z is initialized to 1 with the indicated value all 1's, with a decimal value of zero to keep it constant. The K accumulator is initialized with the actual rounded value of K - 29. The K fractional register is initialized with a color intensity slope of -2,0.

The successive values generated by the vector generation subsystem 126 are shown in Table 5 with the initial values shown in step 1.

In step 7, the pixel counter 148 is decremented by 0 to signal the end of processing for the current vector. Looking at vector 202 in FIG. 11, it can be seen that the Zabbixel addressing representation of vector 202 is much less jagged than the corresponding integer pixel addressing representation of line vector 200.

Through vector processing operations, address O indicates that the four most significant bits of the color stored in word position O are color bits C1l~
C8 is driven, while 7~KO is inserted into the frame buffer memory I in the eight absolute value pits from DVG K12.
It is added to the pattern RAM 156 to drive J Hass DVGDAT 11-1↓. The resulting effect is that the hue remains constant while the brightness changes.

The X and Y pixel values are, of course, placed on conductors DVGDAT 15-12 of the frame buffer memory bus 116, since visual characteristic data for each pixel point are stored.
13.625 3.625 29. 62
11t, 625 3.792 27 55
．． 15.625 3.958 25 1+4,
16.625 ヰ、125 25 3
5, 17.6251t, 292 21 2
6, 18.625'+, 1158 19
17, 19.625 4.625 1
70 Example 3 = polygon 210 according to the invention, Table 6
Table 6 The pattern shown in Table 6 starts with the display coordinate 0.0 and repeats vertically and horizontally every 8 pixels until the 0.0 is selected. 1
represents the color of the selected second color, and l is different from the first color.
It is designed to represent the color of.

Signal PATTSHPSEL is sent to vCl for pattern shape multiplexer 152 to provide as twelve address inputs 'kI5-0, J5-0) to f-turn RAM 156. BitE 2-0 and J2-0
The pattern RAM 156'r is controlled using only the pattern RAM 156'r. Bit E5~I5 and J5~J5 are set and DVG
1122 and DVG 1125.

Pattern RAM'! When addressing i, ■ and J define the spatial frequency and phase of the data generated by pattern RAM 156.

To allow different null patterns to be held at different locations within pattern RAM 156, the current pattern is stored in pattern RAM 156 at address 561.
Start with i0 (HE3g). This address is a logical 1
masked bits equal to) I5~■5 and J5~J5
Corresponds to setting f. top of pattern or Y
=0 rows are written to eight sequential word positions starting at address 3640 (HE3111). The background color corresponding to "o" in the pattern is the word memory location 140-112 (HE
8~ERA) and 36115~117 (HE3D~E
3F), while the foreground color corresponding to the month in the pattern is stored in address word storage locations 3643-1↓(HH5
B-E3C). The storage location of the next 63 memory address words is skipped and word address 5701i (H
Row Y=1 starting with E 78 ) is written. Row Y=2 starting at address 576g (HEB8) is folded,
First Y=7 starting at word address 4088 (HFF8)
Processing continues until rows are written.

Assume that color/luminance multiplexer 158 is set to mode 1 so that the 12-bit visual characteristic word stored in frame buffer memory 16 is retrieved as COD 11-6, PR 7-2.

Gouraud shading is used and the initial values for the polygon 210 are the four corner points 212, 215, 2111 and 2.
It is written in Table 7 defined for 15. The information in Table 7 is either given as source data or calculated by RDPIIO with the display positions of vertices shown in parentheses.

Table 7 Points X YZIJK 2126.020.1118 & ? 521510.9
20.41138115211116.112.011
8012112156.012.018091+, 6X
-Y and 2 are the spatial coordinates of the vertices of the quadrilateral. and J define the beginning and ending storage locations of the data to be selected from the pattern RAM. K is the magnitude of the normal luminance component of the surface oriented parallel to the two axes at the observer.

In order to fill this quadrilateral, the raster data processing device
Proceed as follows. The first of all the highest vertices is located. If there are two, the leftmost one is chosen. The raster data processor then executes a software DVG function that picks a pair of points with the same ordinate until the next highest vertex is reached. Next, software DV
G advances to the next lower vertex and finally the lowest vertex 0
For both points of each pair, the values of X, Y, J, Z, ■, J and K are calculated by interpolation.

Following the calculation of the six pairs of points, DvG X11g generates eleven horizontal fill lines by interpolating the pixel data between each point. DVG j 121 is advanced synchronously with DVG

The visual attribute data is supplied to the pattern RAM 156 as a function of the frame buffer 7 memory 1.
6 is stored. In this example DVG l121
is incremented in conjunction with DVG
Table 8 shows the interpolated data to generate the first line.

Data for the second line is generated in a similar manner by inserting the software interpolated values of X, Y, 2, M, J, and K as the final values of each DVG. Note that for the second line, Z=1 and J=1.
- At the end of the filling procedure, it will be obvious that each side of the quadrilateral is jagged. This is due to rounding of the endpoint Zabvixel address to the (2,2) bias value. To eliminate this effect, the quadrilateral boundaries are redrawn using DVGX, Y, Z, K, J, Ki. Next time.

The sub-vixel address bias is overwritten with the correct offset.

In Example I, line vector 220 is generated by using a combination of sub-vixel addressing and phono shading. Initial point 'iX= Y, Z=25.6.1
'1L11.4.2, and the three regular light vector components are defined as J = 66.125.82. The end point of life is X, Y, '000r-1
r-1000000 place! 1 o O0000o o Oo.

ψ 10- to nψ to o- to ψ ri Oo RO 00 o Q 00 Q QHωΦ0
-4F-11-1, -IF-11-11-IP-1,
-4 current N+-1r-1r-1r-+□+P'IP'l
11 ゝ 0008-Z = 28.1+, 6.5.1, and the three normal light vector components are calculated, J = = -116, 88 ,115
We will determine that.

Color/luminance multiplexer 158 is set to mode 1;
6 bits of color (hue) from pattern RAM 156) (
COL11-6) and 6 bits of luminance from the normalization circuit 154 are output. Pattern shape multiplexer 15
2 is enabled with signal FA, TTERN=0, so that address zero is continuously applied to pattern RAM 156.

Color bits C0L11-6 are loaded into pattern RAM 156 from the RBIN bus. C0L11-6 bits are sequentially output to color/luminance multiplexer 158.

The individual digital vector generators 119-125 are
Initialize as shown for step 1 of Table 1. Initial X pixel display position 26.625, X counter lll0 and X accumulator 136 are written.

X increment value Δx/aY - Y increment -20/(-12,0)(
-1) -0,1667 is placed in the decimal register. The (-1) factor in this calculation is due to the fact that the Y counter is the sludge.

DVG Y119 is initialized by placing an initial integer Y value of 19 in the counter and a decimal value of 0625 in the accumulator. A stepping distance of -0999 is placed in the fractional register.

DVG Z1'20 is created by placing the initial integer binary value 4 in the integer accumulator register and the small a values o, r (0,2 plus the rounded value of 0.500) in the decimal accumulator register. Initialized. Slope (jZ/'Y) (Y increment) = (-52/-12,
0) (-1) =-o, 266r is placed in the Z fractional register. The 2-output multiplexer is set to bypass the absolute value generator of 2, although in this particular example there are no negative binary values.
,500 rounded value) -66,500 to accumulator 1
711, slope i/ΔY = 50/(-1
20)(-1)=4.167e Initialized by placing in integer and fractional registers 1311d, 1'5110.

DVG J122 is initial value + (0,500 rounded value)
= 12a500 into the accumulator and slope (d
J/1Y) = (-57/-12,0)(-
Initialized by loading B==-xos5 into the integer and fractional registers.

DVG KL23 loads the initial value + (0,500 (7) rounded value) = 82.500 into the accumulator register and ramps ("K/"Y) (Y increment) = (-37/-
12,0)(-1)=-5,083 to DVG K12
It is initialized by loading the integer and fractional registers of 5.

The pixel counter iitg calculates the initial value of I N T (AABST (ΔY)) to count the main axis pixel steps.
Set to 12.

The steps encountered by the pixel data generator 112 while generating pixel information for the line vector 220 begin with initialization in step 1. 154 (Figs. 1 and 8), and the normalization circuit
Bit) Since the output values of I, J and I are treated as decimal values, in reality, at the input to the circuit, those values are divided by 611, and then at the output, the resultant PR-0 is multiplied by 6I1. Signal PR7~ to color/luminance multiplexer 158
The normal value N given through oy can be easily calculated using the normalization formula previously explained for each DVG step.

More sophisticated graphical representations can be generated by passing each vector through the vector generator 112'i more than once. During the first pass the desired color or hue pattern is patterned RA, M156'? Gouraud type shedding is used to generate the shading. During the second pass vector generator 112
is operated in the phono (Fhong) shading mode, and the brightness vector N generated by the sophisticated phono is placed in the two-frame buffer memory 16 in place of the previously generated Gouraud shading value.

Notes on Each Side The above sides of operation of the two-progressive graphics image generator 10 are merely illustrative of the many modes of operation available.

The various mode control options can be combined in any convenient combination to produce the desired effect. On each of the representative sides, subtract the positive delta value by adding the negative delta value and instead of rounding up or down, always round up or count the pixels using some other acceptable algorithm. It will be seen that several options have been selected, such as moving the D V G output value in the negative direction by obtaining the instrument start value as an integer of the principal axis delta value. allows a wide range of choices available to the user.

[Brief explanation of drawings]

1 is a block diagram and schematic representation of a graphical image generation apparatus according to the present invention; FIG. 2 is a block diagram and schematic representation of a video output and display system used in the apparatus shown in FIG. 1; 5 is a block diagram of the digital vector generation subsystem used in the apparatus shown in FIG. 1, and FIG.
A block diagram of a single X-dimensional position digital vector generator used in the digital vector generation subsystem shown in FIG. FIG. 6 is a block diagram of a two-dimensional digital vector generator; FIG. 6 is a block diagram of a single one-dimensional luminance digital vector generator used in the digital vector generation subsystem shown in FIG. 5; FIG. , a block diagram of the DVG control circuit used in the apparatus shown in FIG. 1, FIG. 8 is a detailed block diagram of the normalization circuit generally shown in FIG. 5, and FIG. FIG. 10 is a block diagram of the color/luminance multiplexer used in the digital vector generation subsystem shown in FIG. FIG. 11 is a graphical representation of an example used to illustrate the operation of the present invention. Cleaning of drawings N (no change in content) FIG, 1 Fig, l○

Claims (1)

[Scope of Claims] 1. A graphic image generating device for generating an array of pixels forming an image, which corresponds to one pixel of the image, and at least one visual characteristic of that pixel and the pixel in the array of pixels. a frame buffer memory having an array of elements, each element storing information indicative of a multidimensional spatial displacement from a normal position of the image, and receiving information indicative of the visual characteristics from the frame buffer memory; each pixel has a regular position within an array of pixels arranged at uniform intervals according to information indicative of the visual characteristic, and from the regular position according to spatial displacement information corresponding to each pixel. a visible image generator for generating an array of pixels forming an image, each pixel being displaced; visual characteristic information corresponding to a pixel on any boundary that is not parallel to at least defines a spatial displacement of said pixel from its normal position;
and a digital vector generator for providing the visual characteristic information to the frame buffer memory, the digital vector generator including information for reducing image aliasing occurring at the edges. 2. A graphic image generating device for generating an array of pixels forming an image, which corresponds to a pixel of the image and has at least one visual characteristic of that pixel and a difference from the normal position of said pixel within the array of pixels. a frame buffer memory having an array of elements, each element storing information indicative of a multidimensional spatial displacement; and a frame buffer memory connected to receive information indicative of the visual characteristic from the frame buffer memory; Each pixel has a regular position in the array of uniformly spaced pixels in accordance with information indicative of a visual characteristic, and is displaced from said normal position in accordance with spatial displacement information corresponding to each pixel. a visual image generator for generating an array of pixels forming an image; and a plurality of spatial vector generators connected to the frame buffer memory for generating a series of pixel coordinate points defining a line in the displayed image. at least two visual feature vector generators operating synchronously with the spatial vector generator to generate visual feature vector information corresponding to each pixel coordinate point generated by the spatial vector generator; A digital vector generator comprising: a normalization circuit that receives generated visual characteristic vector information and generates a normalized luminance representative of the magnitude of the received vector information;