JPH04213828A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04213828A JPH04213828A JP40099390A JP40099390A JPH04213828A JP H04213828 A JPH04213828 A JP H04213828A JP 40099390 A JP40099390 A JP 40099390A JP 40099390 A JP40099390 A JP 40099390A JP H04213828 A JPH04213828 A JP H04213828A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- resistant film
- hydrofluoric acid
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 title claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 230000003647 oxidation Effects 0.000 claims abstract description 17
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000005498 polishing Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 238000002955 isolation Methods 0.000 description 10
- 229910052681 coesite Inorganic materials 0.000 description 8
- 229910052906 cristobalite Inorganic materials 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 229910052682 stishovite Inorganic materials 0.000 description 8
- 229910052905 tridymite Inorganic materials 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Weting (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
係り， 特に素子分離用絶縁膜の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an insulating film for element isolation.
【０００２】近年， ＬＳＩ の集積度が上がり配線層
数も増加しているため，プロセス中の基板表面の平坦化
が一層要求されるようになってきた。本発明はこの要求
に対処した素子分離用絶縁膜の形成方法として利用でき
る。In recent years, as the degree of integration of LSIs has increased and the number of wiring layers has increased, there has been an increasing demand for flattening of the substrate surface during processing. The present invention can be used as a method for forming an insulating film for element isolation that meets this requirement.
【０００３】0003
【従来の技術】従来のＬ０ＣＯＳ（選択酸化） 法によ
って， シリコン（Ｓｉ）基板に素子分離用絶縁膜とし
て酸化膜 （ＳｉＯ２膜） を形成すると， ＳｉＯ２
膜の厚さは酸化に使われたＳｉの厚さの約２倍になるた
め，基板表面にＳｉＯ２膜の厚さの約半分の段差を生ず
る。[Prior Art] When an oxide film (SiO2 film) is formed as an insulating film for element isolation on a silicon (Si) substrate by the conventional L0COS (selective oxidation) method, SiO2
Since the thickness of the film is approximately twice that of the Si used for oxidation, a step approximately half the thickness of the SiO2 film is created on the substrate surface.
【０００４】したがって，Ｌ０ＣＯＳ 工程後の基板を
平坦化するためには， 例えば， 酸化した後一旦酸化
膜を除去し，再酸化する方法や，基板表面に突出した酸
化膜をコントロールエッチして所望の厚さを残すように
する方法等があるが，いずれも完全に平坦化することは
できない。また，横方向酸化によって耐酸化膜下に生ず
るバーズビーク（断面形状が嘴状の酸化膜）が延び，
その分素子形成領域が狭められ， デバイスの集積度を
低下させる等の問題がある。[0004] Therefore, in order to planarize the substrate after the L0COS process, there are two methods, for example, to remove the oxide film after oxidation and then re-oxidize it, or to perform controlled etching on the oxide film protruding from the surface of the substrate. There are methods to leave some thickness, but none of them can completely flatten the surface. Additionally, the bird's beak (an oxide film with a beak-shaped cross section) that occurs under the oxidation-resistant film due to lateral oxidation is extended.
This results in problems such as the element formation area being narrowed and the degree of device integration being reduced.
【０００５】[0005]
【発明が解決しようとする課題】従来例では，素子分離
絶縁膜を形成した後，プロセスが進むと段差に起因する
問題を生じ，特に配線工程で，配線膜形成の際の被覆不
良やパターニング精度の低下によるパターニング不良等
の問題が生ずる。[Problems to be Solved by the Invention] In the conventional method, after forming an element isolation insulating film, problems arise due to steps as the process progresses, and especially in the wiring process, problems arise such as poor coverage and patterning accuracy during wiring film formation. Problems such as defective patterning occur due to the decrease in .
【０００６】本発明は平坦な素子分離用絶縁膜の形成方
法の提供し，デバイスの微細加工を容易にすることを目
的とする。An object of the present invention is to provide a method for forming a flat insulating film for element isolation, thereby facilitating microfabrication of devices.
【０００７】[0007]
【課題を解決するための手段】上記課題の解決は，１）
基板上の一部に耐酸化膜を形成し，該耐酸化膜をマスク
にして該基板を熱酸化して酸化膜を形成する工程と，次
いで，該基板上に耐弗酸性膜を被着し，該酸化膜上の該
耐弗酸性膜を除去する工程と，次いで，該耐弗酸性膜を
マスクにして弗酸系の液を用いて該酸化膜をエッチバッ
クして該基板表面を平坦化する工程とを有する半導体装
置の製造方法，あるいは
２）前記基板がシリコンからなり，前記耐弗酸性膜がシ
リコンまたはフォトレジストからなることを特徴とする
前記１）記載の半導体装置の製造方法，あるいは３）前
記エッチバック終了後に，前記基板表面を研磨する工程
を有する前記１）
または２）記載の半導体装置の製造方法により達成され
る。[Means for solving the problem] The solution to the above problem is 1)
A step of forming an oxidation-resistant film on a part of the substrate, thermally oxidizing the substrate using the oxidation-resistant film as a mask to form an oxide film, and then depositing a hydrofluoric acid-resistant film on the substrate. , removing the hydrofluoric acid-resistant film on the oxide film, and then etching back the oxide film using a hydrofluoric acid-based solution using the hydrofluoric acid-resistant film as a mask to planarize the substrate surface. or 2) the method for manufacturing a semiconductor device according to 1) above, wherein the substrate is made of silicon and the hydrofluoric acid-resistant film is made of silicon or photoresist; 3) Achieved by the semiconductor device manufacturing method described in 1) or 2) above, which includes the step of polishing the substrate surface after the etch-back is completed.
【０００８】[0008]
【作用】本発明はＬＯＣＯＳ 工程後の凹部 （素子形
成領域） に耐酸化膜を残した状態でこれを覆って耐弗
酸性膜を埋込み， 耐弗酸性膜（あるいは耐酸化膜とと
もに）をマスクにして熱酸化膜（素子分離絶縁膜）を弗
酸系の液を用いてエッチバックすることにより，基板表
面を平坦化するようにしたものである。[Operation] The present invention leaves an oxidation-resistant film in the concave portion (element formation area) after the LOCOS process, buries it with a hydrofluoric acid-resistant film, and uses the hydrofluoric acid-resistant film (or together with the oxidation-resistant film) as a mask. The substrate surface is planarized by etching back the thermal oxide film (element isolation insulating film) using a hydrofluoric acid solution.
【０００９】[0009]
【実施例】図１（Ａ） 〜（Ｅ） は本発明の一実施例
を説明する断面図である。図１（Ａ） において，Ｓｉ
基板１上の緩衝用の厚さ ２００Åの熱酸化ＳｉＯ２膜
２を形成し，その上に厚さ１０００Åの窒化シリコン（
Ｓｉ３Ｎ４） 膜３を成長する。Embodiment FIGS. 1A to 1E are cross-sectional views illustrating an embodiment of the present invention. In Fig. 1(A), Si
A thermally oxidized SiO2 film 2 with a thickness of 200 Å for buffering is formed on the substrate 1, and a silicon nitride film 2 with a thickness of 1000 Å is formed on it.
(Si3N4) film 3 is grown.
【００１０】Ｓｉ３Ｎ４ の成長条件は，反応ガスとし
てトリクロルシランとアンモニアを用い，これを ０．
２〜１．０ Ｔｏｒｒに減圧した雰囲気中で基板を約
８００℃に加熱する。次いで， 通常のフォトリソグラ
フィによりＳｉ３Ｎ４ 膜３をパターニングして素子形
成領域上に耐酸化膜として残す。[0010] The growth conditions for Si3N4 are as follows: trichlorosilane and ammonia are used as reaction gases, and the growth rate is 0.
The substrate is heated in an atmosphere with a reduced pressure of 2 to 1.0 Torr.
Heat to 800°C. Next, the Si3N4 film 3 is patterned by ordinary photolithography to leave an oxidation-resistant film on the element formation region.
【００１１】次いで，基板を熱酸化して分離絶縁膜とし
ての厚さ６０００ÅのＳｉＯ２膜４を形成する。図１（
Ｂ） において，減圧気相成長（ＣＶＤ） 法を用いて
，基板上に耐弗酸性膜として厚さ２０００Åのポリシリ
コン膜５を成長する。Next, the substrate is thermally oxidized to form a SiO2 film 4 with a thickness of 6000 Å as an isolation insulating film. Figure 1 (
In step B), a polysilicon film 5 having a thickness of 2000 Å is grown as a hydrofluoric acid-resistant film on the substrate using a reduced pressure vapor deposition (CVD) method.
【００１２】ポリシリコンの成長条件は，反応ガスとし
てモノシランを用い，これを ０．５〜２．０ Ｔｏｒ
ｒに減圧した雰囲気中で基板を約 ６５０℃に加熱する
。図１（Ｃ） において，研磨により，凸部（分離絶縁
膜）上のポリシリコン膜５を除去し，凹部（素子形成領
域）にポリシリコン膜５を残す。[0012] The growth conditions for polysilicon are as follows: monosilane is used as a reaction gas, and the temperature is 0.5 to 2.0 Torr.
The substrate is heated to about 650° C. in an atmosphere reduced to r. In FIG. 1C, the polysilicon film 5 on the convex portion (isolation insulating film) is removed by polishing, leaving the polysilicon film 5 on the concave portion (element formation region).
【００１３】図１（Ｄ） は，研磨の際に研磨布の粘弾
性変形により，凹部が広い場合はポリシリコン膜５が凹
部に完全に残らない場合を示す。この場合も，選択酸化
に使用したＳｉ３Ｎ４ 膜３と凹部側面に残ったポリシ
リコン膜５とが耐弗酸性膜となるので問題はない。FIG. 1D shows a case where the polysilicon film 5 does not completely remain in the recess when the recess is wide due to viscoelastic deformation of the polishing cloth during polishing. In this case as well, there is no problem because the Si3N4 film 3 used for selective oxidation and the polysilicon film 5 remaining on the side surfaces of the recess become a hydrofluoric acid-resistant film.
【００１４】図１（Ｅ） において，弗酸系の液を用い
てＳｉＯ２膜４をコントロールエッチして基板表面を平
坦にする。コントロールエッチ条件の一例をつぎに示す
。In FIG. 1E, the SiO2 film 4 is subjected to controlled etching using a hydrofluoric acid solution to flatten the substrate surface. An example of control etching conditions is shown below.
【００１５】エッチャント：弗酸に弗化アンモニウムを
混合した緩衝弗酸溶液
コントロール方法：上記弗酸溶液を冷却し， 熱酸化膜
のエッチングレートが５００〜５５０ Å／分に保った
状態で約 ５〜６ 分間エッチングを行う。Etchant: Buffered hydrofluoric acid solution prepared by mixing ammonium fluoride with hydrofluoric acid. Control method: Cool the above hydrofluoric acid solution and heat it for approximately 5 to 50 minutes while maintaining the etching rate of the thermal oxide film at 500 to 550 Å/min. Etch for 6 minutes.
【００１６】さらに，基板表面を研磨することにより一
層良好な表面形状が得られる。研磨は， 例えばコロイ
ダルシリカを含むアルカリ溶液と不織布タイプの研磨布
を用いて行う。Furthermore, an even better surface shape can be obtained by polishing the substrate surface. Polishing is performed using, for example, an alkaline solution containing colloidal silica and a nonwoven polishing cloth.
【００１７】この実施例では，耐弗酸性膜としてポリシ
リコン膜を用いたが，これの代わりにフォトレジスト膜
を用いてもよい。In this embodiment, a polysilicon film is used as the hydrofluoric acid-resistant film, but a photoresist film may be used instead.
【００１８】[0018]
【発明の効果】以上説明したように本発明によれば，平
坦な素子分離用絶縁膜の形成が可能となり，デバイスの
微細加工を容易にすることができた。As explained above, according to the present invention, it is possible to form a flat insulating film for element isolation, thereby facilitating microfabrication of devices.
【図１】 本発明の一実施例を説明する断面図[Fig. 1] Cross-sectional view explaining one embodiment of the present invention
１ Ｓｉ基板 ２ 熱酸化ＳｉＯ２膜 ３ 耐酸化膜でＳｉ３Ｎ４ 膜 ４ 分離絶縁膜でＳｉＯ２膜 ５ 耐弗酸性膜でポリシリコン膜 1 Si substrate 2 Thermal oxidation SiO2 film 3 Si3N4 film as oxidation resistant film 4 SiO2 film as isolation insulating film 5 Polysilicon film with hydrofluoric acid resistant film
Claims (3)
耐酸化膜をマスクにして該基板を熱酸化して酸化膜を形
成する工程と，次いで，該基板上に耐弗酸性膜を被着し
，該酸化膜上の該耐弗酸性膜を除去する工程と，次いで
，該耐弗酸性膜をマスクにして弗酸系の液を用いて該酸
化膜をエッチバックして該基板表面を平坦化する工程と
を有することを特徴とする半導体装置の製造方法。Claim 1: A step of forming an oxidation-resistant film on a part of the substrate, thermally oxidizing the substrate using the oxidation-resistant film as a mask to form an oxide film, and then forming a hydrofluoric acid-resistant film on the substrate. A step of depositing a film and removing the hydrofluoric acid-resistant film on the oxide film, and then etching back the oxide film using a hydrofluoric acid-based solution using the hydrofluoric acid-resistant film as a mask. 1. A method of manufacturing a semiconductor device, comprising the step of planarizing a surface of a substrate.
弗酸性膜がシリコンまたはフォトレジストからなること
を特徴とする請求項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is made of silicon, and the hydrofluoric acid-resistant film is made of silicon or photoresist.
表面を研磨する工程を有することを特徴とする請求項１
または２記載の半導体装置の製造方法。3. The method according to claim 1, further comprising a step of polishing the surface of the substrate after the etch-back is completed.
Or the method for manufacturing a semiconductor device according to 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40099390A JPH04213828A (en) | 1990-12-10 | 1990-12-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40099390A JPH04213828A (en) | 1990-12-10 | 1990-12-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04213828A true JPH04213828A (en) | 1992-08-04 |
Family
ID=18510856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40099390A Withdrawn JPH04213828A (en) | 1990-12-10 | 1990-12-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04213828A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5858860A (en) * | 1996-02-08 | 1999-01-12 | Samsung Electronics Co., Ltd. | Methods of fabricating field isolated semiconductor devices including step reducing regions |
| US5882985A (en) * | 1995-10-10 | 1999-03-16 | Advanced Micro Devices, Inc. | Reduction of field oxide step height during semiconductor fabrication |
-
1990
- 1990-12-10 JP JP40099390A patent/JPH04213828A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5882985A (en) * | 1995-10-10 | 1999-03-16 | Advanced Micro Devices, Inc. | Reduction of field oxide step height during semiconductor fabrication |
| US5858860A (en) * | 1996-02-08 | 1999-01-12 | Samsung Electronics Co., Ltd. | Methods of fabricating field isolated semiconductor devices including step reducing regions |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04213828A (en) | Manufacture of semiconductor device | |
| JPH09326391A (en) | Manufacture of element isolation oxide film | |
| US6153482A (en) | Method for fabricating LOCOS isolation having a planar surface which includes having the polish stop layer at a lower level than the LOCOS formation | |
| JPH04150030A (en) | Manufacture of semiconductor device | |
| US5977608A (en) | Modified poly-buffered isolation | |
| JPH06163528A (en) | Fabrication of semiconductor device | |
| KR100248344B1 (en) | Method for manufacturing semiconductor device | |
| JPH0642510B2 (en) | Method of forming a semiconductor structure | |
| JPH01282836A (en) | Manufacture of semiconductor device | |
| JPH05218191A (en) | Manufacture of semiconductor device having different-width inter-element isolating regions | |
| JP2570729B2 (en) | Method for manufacturing semiconductor device | |
| JPH01291430A (en) | Manufacture of semiconductor device | |
| JPS5931215B2 (en) | How to form an insulating layer | |
| KR940009578B1 (en) | Semiconductor device and manufacturing method thereof | |
| JPH05335297A (en) | Fabrication of semiconductor device | |
| JPH0416019B2 (en) | ||
| JPH06196433A (en) | Method for formation of contact hole in semiconductor device | |
| JPH01162351A (en) | Manufacture of semiconductor device | |
| JPH04144231A (en) | Manufacture of semiconductor device | |
| JPS6156433A (en) | Manufacture of semiconductor device | |
| JPS6167934A (en) | Method for isolation by separation and burying in groove | |
| JPH065693A (en) | Manufacture of semiconductor device | |
| JPH0463431A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH02132830A (en) | Selective oxidation | |
| JPH0558578B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980312 |