JPH0421366A - Power exchanger using replaceable wire unit - Google Patents

Abstract

PURPOSE: To minimize downtime of an inverter by constituting a power converter of a plurality of interconnected subconverters being packaged as mutually replaceable line units so that they can be repaired off-line. CONSTITUTION: The power converter 16 comprises three replaceable line units LRU 20a-20c interconnected to receive control signals delivered from a main control unit. Phase output voltages are placed on output lines 24a-24c and a neutral output voltage is placed on an output line 24n. The LRU 20a-20c comprises a diode, a smoothing capacitor and a transistor and connected with the main control unit 22 through a connector having a series of pins. The LRU 20a-20c can be exchanged or replaced easily upon failure of the housing or an internal element.

Description

[Detailed description of the invention]

[0001]

【Technical field】

TECHNICAL FIELD The present invention relates generally to power converters, and more specifically to:
The present invention relates to a power converter having a modular configuration using replaceable line units. [0002]

[Background technology]

A variable speed motive force produced by a prime mover, such as an aircraft jet engine, is coupled to one or more ACs (
AC) It is often necessary to convert to constant frequency AC power for the load. Such conversion may be performed by a variable speed, constant frequency (VSCF) power generator comprising: a brushless synchronous generator coupled to a prime mover; and a brushless synchronous generator coupled to a prime mover; a power converter coupled to the generator output winding for converting variable frequency power to constant frequency power. [0003] Power converters typically include a rectifier that rectifies variable frequency power produced by a generator and a constant DC power converter to produce direct current (DC) power on a direct current (DC) link. and an inverter to convert the frequency to alternating current (AC) power. The inverter may be of the stepped waveform type, with a series of secondary inverters or sub-inverters coupled to a summing transformer that produces a stepped AC waveform. Such inverters produce an alternating current (AC) output with harmonic content that depends on the number of steps or stages produced in each output cycle. Typically, the inverter has four or six six inverters with outputs that are summed to produce a 24 step or 36 step waveform, respectively.
Contains a stage (6-step) inverter. 6 rows each (6
It can be seen that the secondary inverter of step 1 includes 6 or multiples of 6 power switches, thus a relatively large number of power switches are used to generate the inverter output power. Such power switches or other elements in the secondary inverters often fail, resulting in an undesirable increase in harmonic content in the output and even rendering the entire inverter inoperable. In such cases it is necessary to identify and replace the failed switch or element by inspecting each until it is found. This is a time consuming process and results in significant downtime for the inverter. [0004]

[Summary of the invention]

In accordance with the present invention, a power converter includes a plurality of interconnected sub-converters packaged as interchangeable inter-replaceable line units (LRU'S). [0005] More particularly, the inverter comprises: a plurality of sub-inverters, each of which includes a plurality of power switches connected in bridge form between a DC input and an AC output; a summing transformer associated with a secondary inverter and including a primary winding coupled to the AC output of the secondary inverter and a secondary winding having a termination terminal;
Also associated with each sub-inverter is operating means for operating the plurality of power switches to produce alternating current power at the termination terminal of the secondary winding. [0006] The sub-inverter and associated summing transformer and operating means include:
It is packaged as a replaceable line unit including a terminal coupled to the DC input of the secondary inverter and a termination terminal of the secondary winding. The secondary windings of the LRU are connected in series and the secondary inverter is operated such that a stepped waveform is generated across the series connected secondary windings. [0007] In the event of a failure of one or more elements of a replaceable line unit, a different replaceable line unit may be used in its place, so that the defective LRU can be repaired off-line. obtain. This facilitates repairs and minimizes inverter downtime. [0008]

[Description of preferred embodiment]

Referring to FIG. 1, a variable speed constant frequency (VSCF) device 10 converts variable speed motive power produced by a prime mover 12, such as an aircraft jet engine, into a constant frequency motive force that can be supplied to one or more loads. Convert frequency to AC power. The VSCF device 10 includes a brushless synchronous generator 14 driven by a prime mover 12 and a power converter 16 that converts variable frequency AC power generated by the generator 14 into constant frequency AC power. . [0009] Referring to FIG. 2, power converter 16 includes three interconnected replaceable line units (LRU's) 2 that receive control signals output by main control unit 22.
Contains 0a-20c. Phase output voltage is LRU20
a, while a neutral output voltage is output on output line 24n, which is coupled to LRU 20c. Each LRU 20a-20c includes synchronization inputs and outputs, as well as a clock input for receiving a clock signal output by master control unit 22. In a first embodiment of the invention, the synchronization input of LRU 20a receives the synchronization signal output by main control unit 22. The synchronization output of LRU20a is LRU
The synchronization output of LRU 20b is coupled to the synchronization input of LRU 20c. [0010] Each LRU 20a-20c is connected to the main control unit 2 by a connector 26a-26c, each having a series of pins relating each LRU 20a-20c to the main control unit 22.
2. The main control unit generates 2-bit codes containing access command signals for each LRU 20a-20c and sends the 2-bit codes to lines 28a-2.
8c and output across 30a-30c. As discussed in more detail below, these signals cause each LRU to output an appropriate output waveform that is summed with the outputs of the remaining LRU's to produce constant frequency AC output power. [0011] FIGS. 3A-3C illustrate elements included within each LRU 20a-20c. Only LRU20a is described in detail, LR
It is understood that U 20 b and 20c are the same. Preferably, LRU 20a includes a full bridge rectifier including a diode Di-D6 that converts AC input to DC power on a DC link including DC conductors 40a-40b. A smoothing capacitor C1 is coupled across DC conductors 40a, 40b to reduce ripple. Conductors 40a and 40b are coupled to first and second secondary inverters 42.44. The inverter 42 is
Insulated gate bipolar transistors (IGBT'5) Ql-Q with associated flyback diodes D7-D12
6 in the form of a power switch. In a similar fashion, secondary inverter 44 includes power switches Q7-Q12 in the form of IGBT's with associated flyback diodes D13-D18. It should be mentioned that if desired, the secondary inverters 42,44 may use different power switch types. [0012] Phase outputs 46a-46c of secondary inverter 42 are coupled to a first set of respective primary windings 48a-48c of first summing transformer 49. Phase output 50a of sub-inverter 44
-50c are the three primary windings 5 of the second summing transformer 54
2a-52c. -Next winding 4
Windings 8a-48c are connected together in a wye or star configuration, while -order windings 52a-52c are connected together in a delta configuration. The first summing transformer 49 is connected to the second winding set 5
6a-56c, and the second summing transformer 54 is
A second winding set 58a-58c is included. Winding wire 56
a and 58a are connected together in series, as are windings 56b and 58b and windings 56c and 58c. Winding wire 56a-
56c is the phase output line 24 at the terminal 60a-6°Oc.
a-24c, but the second winding 58a-58c
are coupled to terminals 62a-62c, respectively. [0013] Switch Ql-Q12 is a local control unit responsive to a synchronization input signal, a clock signal, and an access command signal.
70. These signals are sent to terminals 7z, 7
6 and 78a, 78b to the local control unit 70. Additionally, a synchronization output signal is provided by control unit 70 at terminal 79 . [0014] In addition to the foregoing, terminals 80a-80c are coupled to AC inputs of rectifiers that include diodes D1-D6. [0015] Secondary ishiverters 42, 44, summing transformers 49, 54 and local control unit 70 are packaged as a unit either within a housing or on a single circuit board 90. Terminals 60a-60c, 62a-62c, 72.7
6.78a, 78b, 79 and 80a-80c are placed so that they are accessible from outside the housing or so that they are easily accessible on the circuit board. The housing or board 90 facilitates replacement or replacement of the LRU in the event of internal component failure. [0016] As mentioned above, the rectifier bridge containing diodes D1-D6 is preferably a component of LRU 20a. Alternatively, this rectifier bridge and LRU20
The rectifier bridges corresponding to b and 20c may be replaced by a single rectifier bridge outside the LRU, and D
C (direct current) power is accessible from the outside of each housing or circuit board 90 through terminals of the LRU's 20.
It can be applied to the secondary inverter of a-20c. [0017] Referring to FIG. 4, local control unit 70 includes three 4-bit counters 100, 102 and 104;
Each of them includes a clock CLK that receives a clock signal output by the main control unit 22. Each counter 100-104 has one shot 1
It includes a reset input that receives the pulses generated by 06. In the preferred embodiment, one shot)
Although 106 outputs a negative-going pulse upon receiving a positive-going edge in the synchronization input (SYNCIN) signal, alternatively, if a different type of counter is used, the one Shot 106 may generate a positive going pulse. For LRU 20 a of FIG. 3A, the synchronization input signal is provided by main control unit 22 . For LRUs 20b, 20c, the synchronization input signals are provided by the preceding LRUs 20a, 20b, respectively. [0018] Counter 100.102 (7) Ripple Carry (ri
pple carry) outputs 107, 108 are coupled to enable inputs of counters 102, 104, respectively. Counters 100, 102 and 104 are therefore connected to form a 12-bit counter. [0019] Additionally, counters 100-104 include counter outputs that are coupled to low order or lower address inputs of memory 110. . All four bit outputs of counters 100, 102 are coupled to inputs of memory 110, as are the two lower outputs of counter 104. memory 110
may be of any suitable type, such as an EPROM. The two high level address inputs are connected to the main control unit 22.
receive an access command signal provided by the . [0020] In a preferred embodiment, memory 110 includes 4 kilobytes of storage, in which the memory is subdivided into four 1 kilobyte blocks. One of the blocks is accessed to control the secondary inverter 42,44 and the second block is the LRU 20
The third block is accessed to control the secondary inverter of LRU 20c, and the third block is accessed to control the secondary inverter of LRU 20c. counter 100.10
The particular blocks accessed by 2 and 104 are determined by access command signals provided by main control unit 22. The counter accumulates clock pulses and thus sequentially accesses the memory locations in each block to generate a sequence of digital words, and six of the eight retrieved bits of each word are base driven and across a series of lines 111 to an isolation circuit 112, which base drive and isolation circuit 112 then:
Produces an isolated base drive signal of the appropriate level for the secondary inverter switch of the appropriate LRU 20a, 20b or 20c. Therefore, the base drive/separation circuit obtains a series of 6-bit streams from memory 110, in which each bit stream is connected to inverter 4.
Controls one core leg, either 2 or 44. For example, the bit stream on line 111a is used to control switches Q1 and Q2 of secondary inverter 42. line 1
When the state of the signal on line 11a is high, base drive/isolation circuit 112 provides a high state base drive signal to switch Q1 on line 113a and a low state to switch Q2 on line 113b. Issues a drive signal. Conversely, line 1
When the signal state on 11a is low, the base drive signal 1
The state of 13a is low and the state of the base drive signal on line 113b is high. The base drive/isolation circuit 112 also prevents simultaneous conduction of both switches of the inverter core leg by providing a short pause interval between turning off one transistor and turning on the other transistor of the inverter core leg. Gives some degree of immunity. [0021] The design of the base drive/isolation circuit is simple in nature and can in fact be implemented by conventional circuits and therefore will not be described in more detail here. [0022] Synchronization output (SY
The NCOUT) signal is derived from the signal generated on line 113a. The synchronization output signal may alternatively be derived from a different output, such as the signal on line 113b, or from an unused memory output, if desired. [0023] FIG. 7 shows one phase (e.g., phase A) produced by the secondary inverter of LRU's 20 a-20c, and FIG. 8 shows one phase of the resulting output waveform from summing transformer 49. (i.e. phase A). As can be seen in FIG. 7, the secondary inverters 42 and 44 have stepped waveforms 120a and 12, respectively.
Generate 0d. Stepped waveforms 120b-120e and 12
0c, 120f are generated by corresponding secondary inverters 122, 124 in LRLIs 20b, 20c, respectively. The phase B and phase C waveforms are the same as shown in FIGS. 7 and 8, except that they are displaced 120° and 240°, respectively, with respect to the waveforms shown in FIGS. 7 and 8. It is. The LRUs 20b and 20C have terminals 130a, 130c, 132a-132c and 13 corresponding to terminals 60a-60c and 62a-62c, respectively.
4a-134c, 136a-136c. Terminals 62a-62c are connected to terminals 130a-130c, but terminals 132a-132c and 134a-134
c are interconnected. Therefore, LRU20a-20c
The second winding of the summing transformer in FIG. connected in series. [0024] The memories of the LRUs contain identical information such that each LRU can generate any of the waveforms 120a-120f shown in FIG. 7, as well as the corresponding Phase B and Phase C waveforms. It should be noted that The LRU identification signal determines which waveforms are generated by the LRU. [0025] As is evident from FIG.
The LRU produces identical waveforms, except that they are displaced. That is, the waveform generated by the sub-inverter of LRU 20 b is transmitted to sub-inverter 42.4.
The waveform generated by the sub-inverter of LRU 20c is displaced by 10' in time with respect to the waveform generated by the sub-inverter of LRU 2ob. is displaced. By loading each 1 kilobyte block of memory with the same data and at substantially the same time, except that the data is shifted relative to the data of other blocks within the memory locations of each block,
This 10° phase shift is achieved by resetting the counter of a-20c. The latter is achieved by continuing <LRU synchronized output and input interconnections, as shown in FIG. Any sequence errors that may occur are automatically corrected at the end of each cycle of output. [0026] In addition to the foregoing, the phase shift between < LRU outputs may be controllably variable to allow voltage regulation. However, varying the phase shift will result in different harmonic content at the inverter output and it may therefore be necessary to limit the range of variation in order to keep the harmonic content below a certain maximum value. A circuit for performing such a result is proposed by Dh
Patent Application Ser. The contents are incorporated herein by reference. [0027] An alternative to the synchronization mechanism of FIG. 2 is shown in FIGS. 5 and 6. Elements common to FIGS. 2, 5 and 6 are provided with like reference numerals. In FIG. 5, each LRU includes an enable input that is coupled to a counter enable input that corresponds to counter 100 of FIG. Each enable input of LRUs 20a-20c receives an enable signal output by main control unit 22. When the enable signal occurs, L
RUs 20a-20c store memories 11 in the manner described above.
These LRs give digital words sequentially starting from 0.
Start the U sequence. All three LRU20
Such a synchronization mechanism is less desirable than that shown in FIG. 2, since a sequence error can only be corrected by disabling a-20c and re-enabling a-20c. Thus, there is no automatic correction of sequence errors. [0028] FIG. 6 illustrates a further alternative embodiment, in which LRU 20 a sends a synchronization output signal to LRU 20
b and 20c to both synchronization inputs. in this case,
LRU 20b imposes a 10° phase delay on the synchronization signal provided by LRU 20a, whereas LRU 20c imposes a 20° phase delay on the synchronization signal provided by LRU 20a. impose a delay; These phase delays may be implemented by delay elements or circuits that delay the reset signal for the LRU's counter by an appropriate amount with respect to the synchronization input signal provided to the counter. [0029] Power converters or converters constructed using the LRUs disclosed herein are simple in design and can be easily repaired in the event of a power failure or other malfunction. If desired, the power converter may include a fourth spare or extra LRLI that can be used in place of the defective LRU in the field so that counter down time is minimized.

[Brief explanation of drawings]

[Figure 1] FIG. 2 is a block diagram of a power converter.

[Figure 2] FIG. 2 is a block diagram of the power converter of FIG. 1 according to the present invention.

3 is a block diagram illustrating the LRU of FIG. 2 when A, B, and C are combined along the dotted line, with A above B and C below B; FIG.

[Figure 4] FIG. 3 is a block diagram of the local control unit of FIG. 2;

5 is a block diagram similar to FIG. 1 showing a power converter according to another embodiment of the invention; FIG.

FIG. 6 is a block diagram similar to FIG. 1 showing a power converter according to another embodiment of the present invention.

FIG. 7 is a series of waveform diagrams showing only one phase generated by each sub-inverter of each LRU. 8 is a waveform diagram showing one phase of the AC output of the power converter in FIG. 1. FIG.

[Explanation of symbols]

10 Variable speed/constant frequency device 12 Prime mover 14 Brushless synchronous generator 16 Power converter 20a-20c Replaceable line unit (LRU)
22 Main control unit 42 First sub-inverter 44 Second sub-inverter 49 First summing transformer 54 Second summing transformer 60a-60C162a-62C172, a-80c
Terminal 70 Local control unit 90 Circuit board 100.102.104 106 One shot 110 Memory 112 Base drive and separation circuit counter 4 bits 76, 8a1 8b1 79,

【Document name】

[Figure 1] drawing JP-A-4-2+36e (%)

[Figure 2]

[Figure 3]

[Figure 4] J co

[Figure 5]

[Figure 6]

[Figure 7]

[Figure 8]

Claims (14)

[Claims] 1. A power switch, a control means coupled to the power switch for controlling the power switch, and a transformer having a primary winding and a secondary winding coupled to the power switch. packaging means for packaging the power switch and the transformer as a unit; and terminals accessible from the outside of the unit connected to the power switch and the transformer secondary winding. , a replaceable line unit (LRU). 2. The replaceable line unit of claim 1 further comprising a rectifier packaged within said unit and coupled between said power switch and one of said terminals. 3. The control means includes a synchronization input responsive to a synchronization signal for synchronizing operation of the power switch with other LRUs, and a terminal accessible from outside the unit connected to the synchronization input. 2. The replaceable line unit of claim 1, further comprising: 4. The control means of claim 3, further comprising an access command input responsive to an access command signal, and further comprising a terminal accessible from outside the unit connected to the access command input. Replaceable line unit. 5. The LRU comprises: a counter that accumulates clock pulses in response to the synchronization signal; and a counter coupled to the counter and configured to generate a control signal for the power switch in response to the access command signal. 5. The replaceable line unit of claim 4, comprising a memory for generating. 6. The replaceable line unit of claim 1, wherein said packaging means includes a housing within which said power switch, control means and transformer are disposed. 7. The replaceable line unit of claim 1, wherein said packaging means includes a circuit board on which said power switch, control means and transformer are disposed. 8. A plurality of replaceable line units, comprising:
a secondary inverter each including a plurality of power switches connected in a bridge configuration between a DC input and an AC output; a secondary winding having a primary winding and a termination terminal coupled to the AC output of the secondary inverter; a transformer including a wire; a control means for controlling the plurality of power switches to produce alternating current power at a terminal terminal of the secondary winding; packaging means for packaging the sub-inverter, transformer and control means as a unit, including terminals coupled to the DC input of the inverter and the termination terminals of the secondary winding; and a series-connected secondary winding. connecting means for connecting the secondary windings of said LRUs together in series such that a summed voltage is produced across said LRUs; A power converter comprising: synchronization means for synchronizing the operation of a sub-inverter; 9. The power converter of claim 8, wherein each LRU includes a synchronization input and a synchronization output, and the synchronization output of one LRU is coupled to the synchronization input of another LRU. 10. The power converter includes first, second, and third LRUs, and a synchronization input of the first LRU receives a synchronization signal generated by the synchronization means, and a synchronization input of the first LRU receives a synchronization signal generated by the synchronization means,
10. The power converter of claim 9, wherein a synchronization output of an LRU is coupled to a synchronization input of the second LRU, and a synchronization output of the second LRU is coupled to a synchronization input of the third LRU. 11. The power converter includes first, second, and third LRUs, a synchronization input of the first LRU receiving a synchronization signal generated by the synchronization means, and a synchronization input of the first LRU receiving a synchronization signal generated by the synchronization means; The synchronized output of the LRU of the second and third LR
10. The power converter of claim 9 coupled to a synchronization input of U. 12. The power converter of claim 8 further comprising a rectifier bridge packaged within said unit and coupled to said power switch. 13. The power converter of claim 8, wherein said packaging means comprises a housing within which said power switch, transformer and control means are disposed. 14. The power converter of claim 8, wherein said packaging means includes a circuit board on which said power switch, control means and transformer are disposed.