JPH04213106A - One chip microcomputer - Google Patents

Abstract

PURPOSE:To exactly operate the releasing operation of the power save mode of a one chip microcomputer having the power save mode by a few RAM and program utilizing amount. CONSTITUTION:The one chip microcomputer 7 is equipped with an RAM enable register 11 which inputs a reset signal 12 and a power save mode releasing signal 13, and whose value is set to be 1 or o by each input signal. The power save mode releasing operation can be realized by a few RAM and program capacity, so that the areas can be availably utilized. And also, the above mentioned operations can be exactly operated by 100%, so that a reliability can be improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for canceling the power save mode and returning to the normal operation mode in a one-chip microcomputer having a power save mode.

0002

[Background Art] For the purpose of reducing system power consumption,
In recent years, one-chip microcomputers have stopped the operation of the CPU and peripheral functions when normal operation is not required.
A low power consumption operation mode (hereinafter referred to as power save mode) is now provided in which only RAM data is held. Conventionally, methods for returning from power save mode to normal operation mode in such a one-chip microcomputer equipped with power save mode have been
There is one disclosed in JP-A-57-147198. FIG. 3 is a diagram showing a system configuration for implementing the method. In FIG. 3, 1 is a battery, 2 is a power save mode release switch, 3 is a power-on reset device, 4 is a power save mode signal generator, 5 is a reset terminal, 7 is a one-chip microcomputer, 8 is a CPU, and 9 is a RAM 10 is an internal data bus.

The operation of the one-chip microcomputer 7 starts when the battery 1 is connected. First, a reset signal is inputted to the CPU 8 by the power-on reset device 3 via the reset terminal 5. At this time, the CPU 8 starts operating from a predetermined location in the program, and first checks a specific area of the RAM 9 to see if a predetermined value that should be written before entering the power save mode has been written. . Here, since it is a power-on reset time, the predetermined value is not written in the RAM 9, so the CPU 8 determines that the data in the RAM 9 is undefined, and initializes the RAM 9. Furthermore, after the CPU 8 completes the necessary operations in the normal operation mode,
Shifts to power save mode to reduce current consumption. At this time, before transitioning to power save mode, R
In order to check the state of AM9, a predetermined value is written in a specific area of RAM9. Next, in the power save mode, the power save mode is canceled by turning on the switch 2. At this time, the CPU 8 reads the pre-written data in the RAM 9 and checks to see if it has changed from when it was written. However, since there is no change when the power save mode is canceled, the CPU 8 retains the data in the RAM 9 and returns to the normal operation mode. Process.

0004

[Problems to be Solved by the Invention] In the conventional power save mode release method, the undefined RAM is
Since the data is compared with the determination data that should be written before entering the power save mode, there is a possibility that the two will match. At this time, the one-chip microcomputer malfunctions. Here, if the number of data (number of bits) of the RAM to be compared is n, the probability x that both values match is expressed by the following equation.

[0005]

[Math 1]

From Equation 1, in order to reduce the probability x that the one-chip microcomputer malfunctions at the time of power-on reset, it is necessary to increase the number of bits n of RAM data. For example, if n=16, x=1.5×
10-5, which means that for every 100,000 one-chip microcomputers, 1.5 will malfunction. If you try to reduce this defect rate,
There is a problem in that a large amount of RAM area and program area must be used to perform the power save mode release operation, and as a result, there is a possibility that the RAM capacity and program capacity will be insufficient.

The present invention has been made in view of the above points, and as described above, it is possible to perform the power save mode cancellation operation reliably without using extra RAM area and program area. Our goal is to provide a one-chip microcomputer.

[0008]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a RAM enable register (hereinafter referred to as RAME) was established.

[0009]

[Operation] In the one-chip microcomputer according to the configuration of the present invention, when a reset is applied, the RAME
When the value of R becomes 0, and when power save mode is canceled, R
The value of AME becomes 1. On the other hand, in either case, the CPU starts operating from the same address on the program. At this time, if the value of RAME is 0, the RAM data is initialized, and if the value of RAME is 1, the program structure is such that the next process is performed while saving the RAM data, so that the excess data is saved as in the conventional example. It is possible to easily identify whether a reset has been applied or the power save mode has been canceled without using a large RAM area or program area.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit for detecting return from power save mode, which is an embodiment of the present invention. In Figure 1,
When the voltage of the battery 1 drops, the power-on reset device 3 causes the one-chip microcomputer 7 to
A reset signal 12 is input via the reset terminal 5. Further, the power save mode release signal generator 4 generates a rising edge when the switch 2 is turned on, and sends a power save mode signal to the microcomputer 7 via a power save mode release terminal (hereinafter referred to as PSMC terminal) 6. Mode release signal (hereinafter referred to as PSMC signal) 13
Enter. On the other hand, RAME11 is a register that sets the value to 0 when the reset signal 12 is input, and sets the value to 1 when the PSMC signal is input. At this time, both of these input signals perform a reset operation on the CPU 8.

FIG. 2 is a diagram showing an example of a flowchart of a program for detecting return from power save mode. Figure 1
An example will be described using FIG. 2. First, at the time of power-on reset (step 106), the reset signal 13
By inputting , the value of RAME11 is set to 0 (step 108). At this time, the CPU 8 goes through the initial setting routine (step 101), determines the value of RAME11 (step 102), and as a result (proceeds to NO because the value of RAME11 is 0), initializes the RAM9 (step 103). ). Thereafter, the main routine (step 104) is entered and pre-programmed processing is performed. When the processing in the main routine is completed, the one-chip microcomputer 7 shifts to a power save mode (step 105) to reduce current consumption. The power save mode is canceled using either the reset signal 12 or the power save mode release signal 13, and in the case of inputting the reset signal 12, the same as the above explanation (from step 106) is performed. In the case of power save mode release signal 12 input (step 107), RAME
The value of 11 is set to 1. At this time, the CPU 8 goes through the initial setting routine (step 101), and then the RAM
The value of E11 is determined (step 102), and the result (R
The value of AME11 is 1, so proceed to YES), and proceed to the main routine (step 10) with the data in RAM9 saved.
4) Enter.

0012

According to the present invention, the power save mode release operation of a one-chip microcomputer can be realized with a small amount of RAM area and program area, which makes it possible to effectively utilize the RAM and program area, or to reduce the capacity. (miniaturization) is possible. Also, the above operation,
This can be done with 100% certainty and is effective in improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for detecting return from power save mode.

FIG. 2 is a flowchart for detecting return from power save mode.

FIG. 3 is a conventional example showing a method of returning from power save mode.

[Explanation of symbols]

5...Reset terminal, 6...Power save mode release terminal,
10...Internal data bus, 11...RAM enable register.

Claims (1)

[Claims] 1. A one-chip microcomputer having a power save mode, characterized in that the one-chip microcomputer is provided with a register that can distinguish between a reset signal and a power save mode release signal.