JPH04212797A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To allow random access during serial access by building a simplified redundancy circuit as a column redundancy function to a RAM with a serial output function. CONSTITUTION:The redundancy circuit consisting of a sense amplifier RSA for redundancy, an FFRA for redundancy, a multiplexer (MPX) 4, a counter 5, and a ROM 6 for redundancy address is added. If there is the column defect of a sense amplifier SA3, the address of the defective column is stored in a ROM 6 concerning a random access system and the redundancy column is coupled from the amplifier RSA to a data bus when the input address coincides therewith. As to a serial output system, the information on this defective column is transferred to a register SR3 and is taken into an MPX 4. The MPX 4 is so selectively operated as to transmit the data of the redundancy column of the circuit RA at this time.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device.
In particular, the present invention relates to a semiconductor memory device in which a redundant circuit having a column redundancy function is added to a semiconductor memory device that combines a random access memory and a high-speed read shift register.

0002

2. Description of the Related Art Conventionally, a semiconductor memory device has been proposed in which a shift register is attached to a RAM for simultaneously taking in data from each column in parallel and outputting it in high-speed serial fashion. This is extremely suitable for an image memory that requires high-speed serial data transfer to and from a display device and relatively low-speed random access from a CPU. In this RAM with a serial output function, no attempt has been reported yet to apply a redundant circuit configuration that has already been put into practical use in some highly integrated RAMs. In this case, for the row side redundancy function, conventional redundancy technology can be applied as is, but for the column side, although it is possible to correct defective column data in the random access system with only the conventional column redundancy configuration, it is not possible to correct defective column data in the serial output system. The defective column information is included as is and it cannot be repaired.

0003

[Problem to be solved by the invention] R with serial output function
When attempting to realize a column redundant circuit that is also effective for a serial output system for AM, there are problems such as the area occupied by the redundant circuit becomes large and the circuit configuration becomes complicated. That is,
Not only must the column on the RAM side be redundantly saved, but the 1 bit of the shift register added to each column must also be saved correspondingly, but each 1 bit of the shift register is connected in series to the adjacent bit. RAM
Unlike when each column is independent like the side columns, it is difficult to adopt a redundant configuration in terms of functionality.

[0004]The area occupied by the shift register itself is about 10% of that of the RAM side, so when performing column relief including the shift register side, it is important to avoid spending too much area on the redundant function. In the first place, meaning is lost due to the nature of redundancy. The present invention focuses on this point and provides a semiconductor memory device in which a simplified redundant circuit having a redundancy function is added to a semiconductor memory device that combines RAM random access and a shift register that operates asynchronously.

[0005]

[Means for Solving the Problem] The above problem provides a memory section (3) including a plurality of columns and a redundant column to be replaced with a defective column among the plurality of columns, and a memory section (3) that is accessed randomly. and a serial access system that serially accesses the memory section (3), and the random access system includes a row decoder (2) for selecting a row, and a row decoder (2) for selecting the column or redundant column. The serial access system is provided with a plurality of column decoders (1) for serially outputting the held data asynchronously with the operation of the random access system, which is provided corresponding to each of the plurality of columns. The latch means (SR1 to SRn), the redundant latch means (RA) provided corresponding to the redundant column, and the transfer control signal (
TR) is selectively rendered conductive in response to the memory section (3).
), the data read out in parallel from the plurality of columns and the redundant column are transferred in parallel to the plurality of latch means and the redundant latch means, and the random access system is made non-conductive during the serial output. a transfer gate means that enables access to the memory section (3) by the user; a storage means (6) for storing information corresponding to the address of the defective column; and a transfer gate means for storing information corresponding to the address of the defective column; The problem is solved by a semiconductor memory device characterized by comprising: control means for replacing data from the defective column with data held in the redundant latch means among the data serially output from the means and outputting the data. .

[0006]

[Operation] According to the present invention, since the serial access system can be separated from the memory section by the transfer gate means, random access can be performed during serial output, and redundant latch means is provided in the serial access system. Since the data in the defective column is replaced with the data held in the latch means, redundant control of the serial access system can also be realized with a simple configuration similar to that of the random access system.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a semiconductor memory device as an embodiment of the present invention. In FIG. 1, 1 is column data, 2 is a row decoder, 3 is a memory, 4 is a multiplexer, 5 is a counter, 6 is a redundant address ROM as a storage means, SA1 to SAn are sense amplifiers, and RSA is a redundant sense amplifier. ,SR1
-SRn is a redundant shift register, RA is a redundant flip-flop as a latch means having an amplifier, and TR is a transfer gate control signal.

The present invention adds a redundant sense amplifier RSA, a redundant flip-flop RA, a multiplexer 4, and a counter 5 to a semiconductor memory device that combines a conventional random access memory 3 and shift registers SR1 to SRn.
This is a semiconductor memory device to which a redundant circuit consisting of a redundant address ROM 6 and a redundant address ROM 6 are added. In such a configuration, basically, if a defect occurs in any of the memory cells, a redundant circuit operates, and the semiconductor memory device operates externally as a defect-free semiconductor memory device.

This operation will be explained in detail below. for example,
When a defect occurs in the column of the sense amplifier SA3, for the random access system, the address of this defective column is stored in the redundant ROM6, and when it is detected that the input address matches it, the column decoder is transferred from the redundant column of the redundant sense amplifier RSA. By selecting 1, this redundant column is connected to the data bus in place of the defective column and read/written, so that correct redundant information is written or read.

On the other hand, regarding the serial output system, when parallel data is taken into the shift register SR by the transfer gate control signal TR, the defect information of this defective column is transferred as is to the shift register SR3, and then shifted. The register operates asynchronously with the memory and is sequentially shifted up to SRn by the shift clock Sclk.
The defect information is taken into the multiplexer 4. The output of a latch circuit RA that holds the data of the redundant column is simultaneously applied to the multiplexer 4, and when the data of the defective column reaches the shift register output stage SRn and defect information is input, the multiplexer 4 is connected to the redundant column. A switching operation is performed so that the output of the latch circuit holding the column data is sent out, and the output of the final stage of the shift register SRn is sent out for other cases. Redundant column data is taken into latch circuit RA by transfer gate control signal TR. As a result, the defective column information is replaced in the multiplexer 4 with correct information in the latch circuit RA, and a correct serial data output Sout is obtained.

Next, the information replacement control operation in the multiplexer will be explained in more detail. As mentioned above, the redundant address ROM 6 is provided to store the address indicating where the defective column is located in order to control redundancy switching in the random access system, but this ROM 6 is also used to control the multiplexer 4. Ru. This redundant address ROM is constituted by, for example, a polysilicon fuse ROM, and stores addresses by turning on and off the fuses. Thereby, when it is detected that the address input matches the defective column address, the decoder 1 switches from the defective column to the redundant column. This is equivalent to storing in the ROM 6 which column from the SRn column is a defective column, and the column addresses on the RAM side are made to correspond to the order of the SR columns.

[0012] Using the contents of this ROM 6, the counter 5
The number of columns up to the defective column is entered in . On the other hand, the shift clock Sclk is input to the counter 4 at the same time as it is input to the shift register, so the counter 4
Every time lk is input, the number of columns is subtracted and the count becomes 0.
When this happens, a signal is sent to the multiplexer 4. Based on this signal, the multiplexer 4 replaces the shifted defective information with correct information from the RA and serially shifts it out. In this case, when the transfer gate control signal TR is on, data is transferred in parallel from each column of the memory to the shift register all at once, but the shift register shifts data asynchronously, regardless of the RAM, except during this transfer. .

Therefore, after the value corresponding to the defective column address is set in the counter by the transfer gate control signal TR, serial output is possible using a high-speed shift clock independent of RAM operation as described above. The counter is decremented every time this shift clock is input, so that no matter where the defective column is, the data is replaced with the normal data in the redundant latch RA during serial output, resulting in a normal serial output. I get the output.

FIG. 2 is a block diagram showing a semiconductor memory device as another embodiment of the present invention. Elements that are the same as those in the embodiment of FIG. 1 are given the same numbers and symbols. In this case, unlike the embodiment of FIG. 1, instead of the multiplexer 4 and the counter 5, flip-flops FF1 to FFn are used.
A decoder 7, a bus line B for returning the data of the redundant flip-flop RA to the shift register stage having defective information, and gates G1 to Gn for replacing the output of the shift register stage having defective information with normal information are provided. It will be done.

In such a configuration, it is necessary to rewrite the defective information in one of the shift register stages to normal information, but this is done by sending the normal information via bus line B. In this case, by turning on the gate corresponding to the shift register stage coupled to the defective column among the gates G1 to Gn for transferring normal information on bus line B during the first shift operation in the serial transfer mode. , a latch circuit R that holds normal information of the redundant column.
Correct information from A is applied to the output of the shift register stage through the gate and forcibly rewrites the defective information. The contents of the redundant address ROM 6 as a storage means are applied to a decoder 7, which sets the flip-flop corresponding to the corresponding gate.

Each of the flip-flops FF1 to FFn is controlled by a reset signal SRT, and the reset is released at the first shift operation after entering the serial transfer mode, and only the set flip-flop turns on the corresponding gate, and the above-mentioned operation is performed. An operation is performed to replace defective information with normal information. During other periods, the reset signal RS
T is activated and all gates G1 to Gn are kept off.

[0017]

[Effects of the Invention] As described above, according to the present invention, the RAM
It is possible to provide a semiconductor memory device that allows random access during serial access and incorporates a simplified redundancy circuit as a column redundancy function of a semiconductor memory device that combines a shift register and a shift register.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a semiconductor memory device as an embodiment of the present invention.

FIG. 2 is a block diagram showing a semiconductor memory device as another embodiment of the present invention.

[Explanation of symbols]

1...Column decoder 2...Row decoder 3...Memory 4...Multiplexer 5...Counter 6... ROM for redundant address 7...Decoder SA1~SAn...Sense amplifier SR1~SRn...Shift register RSA...Redundant sense amplifier RA...Redundant latch circuit FF1~FFn...Flip-flop

Claims (1)

[Claims] 1. A memory section (3) including a plurality of columns and a redundant column to be replaced with a defective column in the plurality of columns.
), a random access system for randomly accessing the memory section (3), and a serial access system for serially accessing the memory section (3), and the random access system includes a row decoder for selecting a row. (2)
and a column decoder (1) for selecting the column or redundant column, and the serial access system includes:
A plurality of latch means (SR1 to SRn) provided corresponding to each of the plurality of columns and serially outputting the held data asynchronously with the operation of the random access system; and a plurality of latch means (SR1 to SRn) provided corresponding to the redundant columns. Redundant latch means (R
A) and the plurality of latching means are selectively made conductive in response to a transfer control signal (TR), and the plurality of latching means are selectively made conductive in response to a transfer control signal (TR), and the plurality of latching means read out data in parallel from the plurality of columns and the redundant column of the memory section (3). and a transfer gate means that performs parallel transfer to the redundant latch means and is rendered non-conductive during the serial output to enable the random access system to access the memory section (3), and corresponds to the address of the defective column. storage means (6) for storing information to be stored, and data from the defective column among the data serially output from the plurality of latch means is held in the redundant latch means based on the information of the storage means. 1. A semiconductor memory device comprising: control means for replacing and outputting data.