JPH04212571A - Clamping device - Google Patents

Abstract

PURPOSE:To decrease the H sag and V sag of video signals by the clamping device which removes energy diffusion signals from the composite video signals superposed with the energy diffusion signals, such as satellite broadcasting. CONSTITUTION:A charging means which fixes the peak-to-peak value of the horizontal synchronizing signal of the composite video signals to a certain fixed potential, a 1st resistor R1 and 2nd resistor R5 for discharging the charged charges, a detecting means 5 which detects a vertical synchronizing signal, and a switch Q3 which is connected in series to the 2nd resistor R5 and is so connected as to parallel the series circuit thereof with the 1st resistor R1 are provided. The 1st resistor R1 and the 2nd resistor R5 are parallel connected by conducting the switch Q3 in the period of the vertical synchronizing signal to increase the discharge charge quantity in the part of the vertical synchronizing signal, by which the H sag and V sag are decreased.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applicable to satellite broadcasting, etc.
The present invention relates to a clamp device that removes an energy diffusion signal from a composite video signal on which the energy diffusion signal is superimposed.

0002

2. Description of the Related Art In recent years, satellite broadcasting has been put into practical use, and scrambled broadcasting using satellite broadcasting is about to begin. In this scrambled broadcasting, an intra-scan line signal switching method and a scanning line transition method that switch the left and right signals in the scanning line are standardized. There is a need for a clamping device with improved H-sag.

An example of the above-mentioned conventional clamp device will be explained below with reference to the drawings.

FIG. 2 shows a circuit diagram of a conventional clamp device. In Fig. 2, 1 is a composite video signal input terminal;
is a composite video signal output terminal, 3 is a buffer, Q1 is an NPN transistor, Q2 is a PNP transistor, R1, R2,
R3 and R4 are resistors, and C1 and C2 are capacitors.

The composite video signal at terminal 1 has an energy diffusion signal superimposed thereon, and the DC component is removed by capacitor C1, and transistors Q1 and Q2 and resistors R1 and R
2, R3, R4, and a clamp circuit composed of capacitor C2. The base voltage of NPN transistor Q1 is determined by resistors R2 and R3 (capacitor C2 is a capacitor for voltage stabilization) and is fixed, and there is also the emitter voltage of transistor Q1, which changes from on to off (or from off to on). It becomes a constant voltage (this constant voltage will be referred to as a clamp level from now on). Further, the collector of the transistor Q1 is connected to the power supply voltage Vcc via the base of the transistor Q2 and the resistor R4. The emitter of the PNP transistor Q2 is connected to the power supply voltage Vcc,
The collector is connected to the capacitor C1, the emitter of the transistor Q1, the resistor R1, and is connected to the terminal 2 through the buffer 3.
It is configured so that a composite video signal output can be obtained.

The operation of the clamp circuit configured as described above will be explained below.

When the composite video signal from which the DC component has been removed by capacitor C1 (ie, the emitter voltage of transistor Q1) is lower than the clamp level, transistor Q1 is turned on, lowering the base voltage of transistor Q2, and transistor Q2 is also turned on. . Therefore, transistor Q2 charges capacitor C1.
1's emitter voltage increases. On the contrary, transistor Q
If the emitter voltage of 1 is higher than the clamp level, transistor Q1 is turned off, the base voltage of transistor Q2 increases, and transistor Q2 is also turned off. At this time, the charge on the capacitor C1 is discharged through the resistor R1.

[0008] In a steady state, the charged charge and the discharged charge are equal, and the minimum voltage value of the composite video signal, that is, the peak value of the synchronization signal, is fixed at the clamp level and the energy diffusion signal can be removed. .

[0009]

[Problem to be Solved by the Invention] However, in the above configuration, since the width of the peak value is different between the vertical synchronizing signal and the horizontal synchronizing signal of the composite video signal, the vertical synchronizing signal portion and the other portions are DC. The charging/discharging balance of the component removal capacitor is also different. That is, in the vertical synchronization signal portion, since the peak value width of the synchronization signal is wide, a large amount of charge is charged, and in order to maintain a balance between charging and discharging, the amount of charge to be discharged must also be large. Therefore, it is necessary to reduce the value of resistor R1. However, if the value of the resistor R1 is made small, the so-called H sag, which is a DC level change in the horizontal scanning period, increases. This situation is shown in Figure 3. Figure 3
, (a) is a composite video signal input with a vertical scanning period on which an energy diffusion signal is superimposed, (b) is a composite video signal input with a horizontal scanning period, and (c) and (d) are vertical scanning signals after clamping. It is a composite video signal with period and horizontal scanning period.

On the other hand, in order to reduce the H sag, the resistor R
When the value of 1 is increased, a DC level change in the scanning period, so-called V sag, occurs. This situation is shown in Figure 4. Figure 3
Similarly, in FIG. 4, (a) is a composite video signal input with a vertical scanning period on which an energy diffusion signal is superimposed, (b) is a composite video signal input with a horizontal scanning period, and (c) and (d)
are composite video signals of a vertical scanning period and a horizontal scanning period after clamping, respectively.

[0011] Such H sag and V sag are caused by image processing in which the scrambled video signal is descrambled by cutting the video signal within the horizontal scanning period and swapping the left and right sides or the order of the scanning lines. When this is done, a problem arises in that a difference in brightness occurs in signals that should originally have the same brightness or continuous brightness, which is a major cause of deterioration in image quality, such as vertical lines and uneven brightness appearing in the restored image.

In view of the above problems, the present invention provides a clamping device that improves the H sag and V sag of a video signal.

[0013]

[Means for Solving the Problems] In order to solve the above problems, the clamp device of the present invention includes a charging means for fixing the peak value of a horizontal synchronizing signal of a composite video signal to a certain fixed potential; A first resistor and a second resistor for discharging charges, a vertical synchronizing signal position detecting means for detecting the position of the vertical synchronizing signal, and a signal obtained by the vertical synchronizing signal position detecting means. the switch is inserted between the second resistor and ground, and the switch is made conductive and the second resistor is grounded only when the composite video signal is at the vertical synchronization signal position. It is.

[0014]

[Operation] With the above-described configuration, the present invention can change the amount of charge discharged by the DC component removal capacitor between the vertical synchronization signal and other parts, and can improve both the H sag and V sag of the composite video signal. .

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A clamping device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a clamping device according to an embodiment of the present invention. In Figure 1, Q1
, Q2 is a transistor, C1 and C2 are capacitors, R1
, R2, R3, and R4 are resistors, and 3 is a first buffer, which has the same structure as the one with the same number in FIG. The difference from FIG. 2 is that the transistor Q3 is a switch.
, a resistor R5, a second buffer 4, and a vertical synchronization signal position detection means 5 are provided. The clamped composite video signal is supplied to the vertical synchronization signal position detection means 5 through the second buffer 4, and the vertical synchronization signal position detection means 5 supplies a signal indicating the vertical synchronization portion of the composite video signal to the base of the transistor Q3. . The emitter of transistor Q3 is grounded, and the collector is connected to resistor R5. Also, resistor R5 and transistor Q3 are placed in parallel with resistor R1.

The operation of the clamp device constructed as described above will be explained below with reference to FIG. In FIG. 1, transistors Q1, Q2, capacitors C1, C2,
Resistors R1, R2, R3, R4 and buffer 3 are shown in Figure 2.
Since it functions in the same way as the one with the same number, detailed explanation will be omitted. The vertical synchronization signal position detection means 5
A signal indicating the position of the vertical synchronizing signal of the composite video signal applied through the buffer 4 is supplied to the base of the transistor Q3, and the transistor Q3 is turned on when the vertical synchronizing signal is received. Therefore, in the vertical synchronization signal portion, the charge of the capacitor C1 is discharged by the resistor R1 and the resistor R5, so that the amount of discharged charge increases.

Further, in a portion other than the vertical synchronizing signal, the transistor Q3 is turned off, and the charge in the capacitor C1 is discharged only by the resistor R1.

That is, in the vertical synchronizing signal portion, the synchronizing signal has a wide peak value width and the transistor Q2 is on for a long time, so a large amount of charge is charged. Therefore, by turning on the transistor Q3 to increase the amount of charge to be discharged and maintaining a balance between charging and discharging, a stable clamping operation is performed. On the other hand, transistor Q3 is used for parts other than the vertical synchronization signal.
By turning off the capacitor C1, the amount of charge discharged from the capacitor C1 can be reduced, and H sag can be reduced.

[0020]

As described above, according to the present invention, the V sag is reduced by increasing the amount of discharge charge in the vertical synchronizing signal portion and performing stable clamping operation, and in the other portions other than the vertical synchronizing signal. By reducing the amount of discharged charge, H sag can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a clamp device according to an embodiment of the present invention.

[Figure 2] Circuit diagram of a conventional clamp device

FIG. 3 is a waveform diagram showing a composite video signal clamped by a conventional clamp device.

FIG. 4 is a waveform diagram of a composite video signal clamped by a conventional clamp device.

[Explanation of symbols]

1 Composite video signal input terminal 2 Composite video signal output terminal 3 Vertical synchronization signal detection means Q1, Q2, Q3 transistor C1, C2 capacitor R1, R5 Resistor

Claims (1)

[Claims] 1. Charging means for fixing the peak value of a horizontal synchronizing signal of a composite video signal to a certain fixed potential; a first resistor and a second resistor for discharging the charged charge; , comprising a vertical synchronizing signal position detecting means for detecting the position of the vertical synchronizing signal, and a switch controlled by the signal obtained by the vertical synchronizing signal position detecting means, the switch being connected to the second resistor and grounded. The clamp device is inserted between the two resistors and makes the switch conductive to ground the second resistor only when the composite video signal is at the vertical synchronization signal position.