JPH04212071A - Peak value detection circuit - Google Patents

Abstract

PURPOSE:To achieve stabilization by suppressing fluctuation of an output signal and prevent a production cost from being increased simply by adding a simple circuit. CONSTITUTION:By transmitting output signals V1 and V2 of a pre-stage differential circuit 10 whose peak value is to be detected to a full-wave rectification circuit 1 through capacitors C1 and C2, fluctuation of an output signal V0 due to fluctuation of a DC voltage of the signals V1 and V2 is eliminated. Also, since resistance elements R1-R4 are formed to have an equal layer resistance, a high level of the signal V0 is determined only by a setting ratio of the elements R1-R4 regardless of fluctuation and temperature change of process conditions at the time of manufacture, thus enabling level fluctuation to be suppressed. Also, the low level of the signal V0 is determined by ON resistance of transistors Q1 and Q2 and fluctuation can be ignored by setting the resistors R1-R4 to approximately several KOMEGA since this ON resistance is approximately several 10OMEGA. Therefore, a stable signal V0 can be obtained without being affected by influence of the circuit 10 or temperature change, production process, etc.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a peak value detection circuit, and in particular to a peak value detection circuit for detecting a GHz value such as a GaAs field effect transistor circuit.
The present invention relates to a peak value detection circuit for detecting the peak value of an ultra-high-speed signal of the order of magnitude.

0002

2. Description of the Related Art Conventionally, this type of peak value detection circuit has often been in the form of a differential circuit, an example of which is shown in FIG.

This circuit connects the drain to the output terminal TO in common and the source to the front differential circuit 10.
A full-wave rectifier circuit 1 includes first transistors Q1 and Q2 that directly input two output signals V1 and V2 into the corresponding gates, respectively, and a source connected to the first transistor Q.
1, a second transistor Q commonly connected to the sources of Q2
3, a first resistance element R2 whose one end is connected to the drains of the transistors Q1 and Q2 and serves as a load for these transistors Q1 and Q2, and whose one end is connected to the drain of the transistor Q3 and whose other end is the other end of the resistance element R2. A second resistive element R3 is connected to serve as a load for the transistor Q3, and a resistive element R1 has one end connected to the other ends of the resistive elements R2 and R3, and the other end connected to the first power supply terminal (power supply voltage VDD). and a transistor Q10 whose drains are connected to the sources of the transistors Q1 to Q3 and whose sources are connected to the second power supply terminal (power supply voltage VSS) to serve as a constant current source for the differential circuit formed by the transistors Q1 to Q3. , and a bias circuit 3 that includes resistive elements R9 and R10 and supplies a bias voltage to the gate of the transistor Q3.

Note that the peak value can be detected by connecting a resistor with a predetermined time constant and a capacitive element to the output terminal TO.

[0005]

[Problems to be Solved by the Invention] In the conventional peak value detection circuit described above, the output signals V1 and V2 of the front-stage differential circuit 10 are directly connected to the gates of the transistors Q1 and Q2, and the difference formed by the transistors Q1 and Q3 is Since the constant current source of the dynamic circuit is configured to be formed by the transistor Q10, the current value of the constant current source, that is, the transistor Q
There is a drawback that the current value of the differential circuit formed by Q1 to Q3 varies, and therefore the current voltage (center potential) of the output signal VO varies.Furthermore, when the current value of this differential circuit varies, the circuit gain varies. , therefore, the amplitude of the signal VO 2 also varies, which is a serious drawback as a circuit for detecting a peak value.

In order to compensate for this drawback, if a compensation circuit is provided to adjust the gate voltage of the constant current source transistor Q10 against temperature changes, etc., the circuit becomes complicated, and the number of control parameters increases, resulting in lower yield and manufacturing cost. The disadvantage is that it increases.

Furthermore, since the gates of transistors Q1 and Q2 are directly connected to the output terminal of the front-stage differential circuit 10, if the DC value of the output signal of the front-stage differential circuit 10 varies, this will directly change the DC value of the output signal VO. The disadvantage was that it resulted in variations.

Furthermore, since the bias voltage to the gate of transistor Q3 is fixed, the input signals VIA,
Output voltage VO for VIB (or V1, V2)
The disadvantage is that the level characteristics are fixed and the scope of application is limited.

An object of the present invention is to provide a peak value detection circuit that can suppress and stabilize output signal variations by simply adding a simple circuit, and can therefore suppress an increase in manufacturing costs. be. Another object of the present invention is to provide a peak value detection circuit that can expand the range of application.

0010

[Means for Solving the Problems] The peak value detection circuit of the present invention includes a capacitive element that removes the direct current component of a signal from a previous stage circuit and transmits the signal, and a source-drain circuit that responds to the signal from the capacitive element. a rectifier circuit including a first transistor through which current flows; and a second rectifier circuit having one of its sources and drains commonly connected to one of the sources and drains of the first transistor.
a transistor, and first and second resistive elements whose one ends are connected to the other of the source and drain of each of the first and second transistors, respectively, and serve as loads for the first and second transistors; These first and second resistance elements are formed to have the same layer resistance, and one end is connected to the first resistance element.
and a third resistance element connected to the commonly connected sources and drains of the second transistor and serving as a constant current source of a differential circuit formed by the first and second transistors;
and a bias circuit that supplies predetermined bias voltages to the gates of each of the first and second transistors.

Further, the bias circuit is formed including a diode element, and is configured to obtain a bias voltage from a voltage generated by the constant voltage characteristic of the diode element.

[0012] Furthermore, the second transistor is constructed by providing a terminal to the gate of the second transistor to apply a bias voltage from the outside.

[0013]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional peak value detection circuit shown in FIG. Capacitive elements C1 and Q2 transmitting to the
A bias circuit 2 including resistive elements R5 to R8 and supplying a predetermined bias voltage to the gates of transistors Q1 and Q2 is provided, and a constant current source of a differential circuit formed by transistors Q1 to Q3 is connected to the resistive element. The point is that the resistance element R4 is formed to have the same layer resistance as R1 to R3.

In this embodiment, since the signals (V1, V2) whose peak values are to be detected are transmitted to the full-wave rectifier circuit 1 via the capacitive elements C1, C2, the DC component of the front-stage differential circuit 10 is Therefore, variations in the output signal VO due to variations in the DC voltage of the output signals V1 and V2 of the front-stage differential circuit 10 can be eliminated.

Furthermore, since the resistance elements R1 to R4 are formed to have the same layer resistance, even if there are variations in process conditions or temperature changes during manufacturing, the high level of the output signal VO will be the same as that of these resistance elements. It is determined only by the setting ratios of R1 to R4, and therefore, this level fluctuation can be suppressed.

Furthermore, the low level of the output signal VO is determined by the on-resistance of the transistors Q1 and Q2, and since this on-resistance is approximately several tens of Ω at most, the resistors R1 to R4
If it is set to about several kΩ, the variation can be ignored.

Therefore, a stable output signal VO can be obtained without being affected by the front stage differential circuit 10, temperature changes, manufacturing processes, etc.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, a bias circuit 2A for transistors Q1 and Q2 and a bias circuit 3A for transistor Q3 are connected to diodes D1 to D3, D4 and D, respectively.
The bias voltage is generated using the constant voltage characteristics of the transistor Q5, and compared to the first embodiment, the transistor Q
There is an advantage that the bias voltages of Q1 to Q3 are further stabilized, and a more stable output signal VO can be obtained.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

The bias voltage to the gate of transistor Q3 is supplied from the bias circuit 3 in the first embodiment shown in FIG. 1, but in this third embodiment,
A bias supply terminal TB is provided, and the bias is directly supplied from the outside through this terminal TB.

FIG. 4 is a characteristic diagram of the output signal VO with respect to the input signals VIA and VIB when the externally supplied bias voltage VB is changed in this embodiment.

Adjusted bias voltage V to terminal TB
When B is changed to be higher than the bias voltage to transistors Q1 and Q2, the current flowing toward the output terminal TO becomes smaller, so the DC voltage (VO) at the terminal TO shifts to the higher side, increasing the bias voltage VB. When the voltage is changed to a lower value, the DC voltage (VO) at the terminal TO shifts to a lower value for the opposite reason. In other words, it becomes possible to adjust the DC voltage level of the output signal VO by the bias voltage VB of the terminal TB, and it is possible to compensate for a wider range of defects such as variations in the conventional technology.
The characteristics of the output voltage VO with respect to VIB can be adjusted arbitrarily, and the range of application can be expanded.

Although this third embodiment is based on the embodiment shown in FIG. 1, it can be similarly applied to the embodiment shown in FIG.

[0027]

[Effects of the Invention] As explained above, the present invention supplies a signal from the previous stage via a capacitor to the gate of the first transistor constituting a full-wave rectifier circuit, and also supplies a bias voltage by a bias circuit. , by forming the constant current source of the differential circuit formed by the first transistor and the second transistor with a resistance element having the same layer resistance as the load resistance of these transistors, a simple structure can be achieved. By simply adding a circuit, it is possible to eliminate the adverse effects of the previous stage circuit, temperature changes, manufacturing process conditions, etc., so it is possible to suppress and stabilize output signal variations, and to suppress increases in manufacturing costs. There is an effect that can be done.

Furthermore, by configuring the bias voltage for the gate of the second transistor to be directly supplied from the outside, it is possible to compensate for variations in a wider range, and the characteristics of the output signal with respect to the input signal can be adjusted arbitrarily. It has the effect of being able to be adjusted and therefore expanding the range of application.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

4 is a characteristic diagram of an output signal with respect to an input signal when the bias voltage applied to the gate of the second transistor of the embodiment shown in FIG. 3 is changed; FIG.

FIG. 5 is a circuit diagram showing an example of a conventional peak value detection circuit.

[Explanation of symbols]

1 full wave rectifier circuit 2, 2A, 3, 3A bias circuit 10
Pre-stage differential circuit C1, C2 Capacitive element D1-D5 Diode Q1-Q10 Transistor R1-R14 Resistive element TO, TB terminal

Claims (3)

[Claims] 1. A rectifier circuit comprising: a capacitive element that removes a direct current component of a signal from a previous stage circuit and transmits the signal; and a first transistor that causes a current to flow between the source and drain in accordance with the signal from the capacitive element. , a second transistor having one of its sources and drains commonly connected to one of the sources and drains of the first transistor, and one end of which corresponds to the other of the sources and drains of each of the first and second transistors, respectively. first and second resistance elements that are connected and serve as loads for these first and second transistors; a third resistance element connected to the commonly connected source and drain of the second transistor and serving as a constant current source of a differential circuit formed by the first and second transistors; 1. A peak value detection circuit comprising: a bias circuit that supplies a predetermined bias voltage to the gates of two transistors. 2. The peak value detection circuit according to claim 1, wherein the bias circuit includes a diode element and is configured to obtain the bias voltage from a voltage generated by the constant voltage characteristic of the diode element. 3. The peak value detection circuit according to claim 1, further comprising a terminal for externally applying a bias voltage to the gate of the second transistor.