JPH04211518A - Superconduction circuit - Google Patents

Abstract

PURPOSE:To provide a superconduction circuit having an output driver circuit with high reliability in operation which improves the output logical amplitude of a semiconductor circuit. CONSTITUTION:A superconduction circuit 1 performing a logical operation consists of a Josephson processing circuit 2 transmitting an output logical signal at a first logical amplitude, a voltage amplifier circuit 3 receiving the output logical signal from the Josephson processing circuit for transmitting an output signal having second logical amplitude essentially larger than the first logical amplitude, an impedance conversion circuit 4 receiving the output signal from the voltage amplifier means generating the output of the superconduction circuit at an output impedance appropriate for the signal transmission to an external circuit.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD The present invention relates generally to superconducting circuits equipped with Josephson elements, and more particularly to superconducting circuits including an output conversion circuit for converting the output of a superconducting circuit into a signal suitable for use in a semiconductor processor. Concerning conducting circuits.

0002

2. Description of the Related Art Generally, a superconducting circuit having a Josephson element provides an output logic signal having a logic amplitude determined by the energy gap inherent in the material used for the Josephson junction. When niobium (Nb), one of the typical materials for Josephson junctions, is used for this purpose, a logic amplitude of approximately 3 mV is obtained. Although this low logic amplitude is advantageous in reducing power consumption, this logic amplitude level is too low to drive semiconductor circuits operating at room temperature conditions. It must be noted that Josephson circuit operation requires an extremely low temperature environment. For this reason, cryogenic containers containing a coolant such as liquid helium are used to house Josephson circuits. Processing circuits that operate at room temperature are thus essential for post-processing the Josephson processor's output. Generally, a logic amplitude of about several hundred mV is required in such a processing circuit, and if a CMOS (complementary metal oxide semiconductor) device is used for this purpose, for example, the logic amplitude required to drive the device is about 1. It becomes 5V. On the other hand, GaAs F
When using ET (field effect transistor), the preferred logic amplitude is approximately 800 mV. Using bipolar transistors, the preferred logic amplitude is approximately 400 mV.

[0003] If the Josephson processor outputs directly to these semiconductor processing circuits, the semiconductor processing circuits may not operate properly or at all. Even when operating properly, such systems are extremely susceptible to external noise. Under these circumstances, there is a strong demand for a superconducting output device that can operate in a low-temperature environment together with the Josephson processor as part of the Josephson integrated circuit that converts the logic amplitude of the Josephson processor to a level suitable for processing by semiconductor circuits. It will be done.

FIG. 16 is a circuit diagram showing a conventional Josephson gate circuit according to Japanese Patent Application No. 61-1715511. In the same figure, the circuit includes a first junction group 11 including a plurality of Josephson junctions J11, J12, , J1n connected in series, a plurality of Josephson junctions J21, J22,
, , a second junction group 12 including a first resistor R1 connected in series to the first junction group 11;
2, the junction group 11 and the resistor R1 constitute a first branch of the bridge circuit, and the junction group 12 and the resistor R2 constitute a second branch of the bridge circuit. Configure. A drive current Ib is applied to the driver 10 at a terminal PVcc connected to the neutral connection point of the bridge, and the Josephson junctions of junction groups 11 and 12 have the same critical current Is in each Josephson junction.

In operation, the bias current Ib supplied at the terminal PVcc branches and flows through the first and second branches with the same magnitude. In this way, the current Ib/2 is the first, second
flows through the branches of As long as this current Ib/2 is lower than the critical current of the Josephson junction included in the branch, the junction groups 11 and 12 maintain their superconducting state.

In this state, the input current Iin is in the junction group 11.
When the current Iin is supplied to the input terminal Pin connected to the connection point between the R1 and the resistor R1, the current Iin passes through the path shown by the dotted line in Figure 1, and the current with magnitude Iin/2+Ib/2 flows through the second flows through the branch, while the magnitude is −Iin
A current of /2+Ib/2 will flow through the first branch. In this way, the current value of the second branch Iin/
2+Ib/2 exceeds the critical current of at least some of the Josephson junctions in the second group of junctions 12, these Josephson junctions transition to a finite voltage state and the second
Resistance appears at the branch of In response to the appearance of this resistance, the drive current Ib/2, which has been flowing through the second branch, changes its flow to the first branch. This causes an overshoot of the current Ib flowing through the first junction group 11, and the Josephson junctions J11-J1n of the first group 11
Both transition to a finite voltage state. Furthermore, in response to these transitions of Josephson junctions J11-J1n, Josephson junctions J21-J2n all change to a finite voltage state, and the output connected to the connection point between resistor R2 and the second group of junctions 12 A voltage corresponding to the energy gap of each Josephson junction multiplied by the number of stages of the Josephson junction appears at the terminal Pout.

FIGS. 17(A) to 17(F) show the operation of a conventional Josephson circuit. Figure 17(A) defines the parameters of the circuit in Figure 1, and Figures 17(B) to 17(
F) shows a waveform that appears in response to the above operation.

Input terminal Pin shown in FIG. 17(B)
With the rise of the input current Iin in the second branch, the current IR flowing through the second branch increases and some of the Josephson junctions begin to switch to the finite voltage state at time T1. After timing T1, current IR drops significantly. On the other hand, the current IL flowing through the first branch enters a surge state at timing T2 shown in FIG. 2(D). This current IL
In response to the surge, all Josephson junctions in the first branch switch to a finite voltage state, and the current IR is
B) It rises again as shown by the large peak at timing T3 shown in FIG. As a result, all the Josephson junctions in the second branch are switched to a finite voltage state, and an output voltage having a value multiplied by the gap voltage multiplied by the number of Josephson junctions connected in series appears at the output terminal Pout. Correspondingly, the output current IRL to the load RL is shown in Figure 2 (F).
rise as shown in .

[0009]

[Problems to be Solved by the Invention] However, in this conventional driver, when connecting a semiconductor processing circuit to the output terminal Pout, the current IL or IR that should cause a Josephson junction transition is caused by the input impedance of the semiconductor circuit Since the voltage is low, there is a problem that the voltage flows to the semiconductor circuit that constitutes the load RL. In particular, if current loss occurs at time T2 or T3, the operation of the output driver becomes unstable. In addition, the large number of Josephson junctions connected in series creates large but unpredictable parasitic inductances in many Josephson junctions and their corresponding first and second branches, leading to , T3
The overshoot of the current at may not be strong enough to occur as expected. Thus, the conventional circuit shown in FIG. 1 suffers from the problem of lacking sufficient reliability.

The present invention has been made in view of the above points, and includes a Josephson processor that performs predetermined logical operations, and an operation that can receive the output logic signal of the Josephson processor in order to increase the logic amplitude and output the output signal. The purpose is to provide highly reliable superconducting circuits.

[0011]

SUMMARY OF THE INVENTION FIG. 1 is a block diagram showing the principle of the present invention. Perform a logical operation and store the result as the first
The superconducting circuit 1 includes a Josephson arithmetic circuit 2 that outputs an output logic signal having a logic amplitude of Multiple superconducting quantum interference elements connected in series that have a control line and are supplied with a bias current, transition from a superconducting state to a finite voltage state in response to a signal on the control line, and generate a basic logic amplitude along with the transition. and a bias current is configured to sequentially flow through the plurality of superconducting quantum interference devices, and an output logic signal is configured to sequentially flow through the plurality of superconducting quantum interference devices through a control line. Voltage amplification means for outputting to an output terminal a logic signal having a second logic amplitude that is substantially larger than the first logic amplitude as a sum of logic amplitudes;
connected to the output terminal, suitable for outputting a logic signal having a second logic amplitude to an external circuit, and when the transition of the superconducting quantum interference element in the power amplification means 3 is performed;
The impedance converting means 4 has an output impedance such that the bias current flowing into the superconducting quantum interference device does not substantially flow out from the output terminal.

[0012] Also, one superconducting quantum interference element
Josephson junction, second Josephson junction and first
a first superconducting loop in which inductances of a first magnetic field control line that is magnetically coupled to an inductance, and a second magnetic field control line that is magnetically coupled to a second inductance, and the first Josephson junctions of each superconducting quantum interference device are connected in series. A superconducting circuit in which first magnetic field control lines and second magnetic field control lines of each superconducting quantum interference element are connected in series.

[0013]

[Operation] The output driver circuit of the present invention includes a voltage amplifier circuit and an impedance conversion circuit for increasing the logic amplitude of an output amplitude signal, the voltage amplifier circuit includes one or more Josephson junctions, and the voltage amplifier circuit includes one or more Josephson junctions. An impedance conversion circuit is connected which receives the output signal of the voltage amplifier circuit, and since the impedance conversion circuit has a high impedance, the operation of the voltage amplifier circuit is not affected by the current flowing to this impedance conversion circuit.

Further, a sufficiently large output voltage can be obtained from the impedance conversion circuit to drive the semiconductor circuit, and
In this case, reliable voltage conversion is possible since no adverse effects occur on the operation of the intensifier circuit.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram illustrating the principles of the invention. The figure shows the overall structure of the superconducting circuit 1. The superconducting circuit 1 is a Josephson processor 2 that performs logical operations and outputs an output logic signal with a first low logic amplitude appropriate for the Josephson element. A voltage amplification circuit 3 is supplied with an output logic signal from the son processor 2 and outputs an output logic signal having a logic amplitude that increases in response to the signal, and is connected to the voltage amplification circuit 3 to stabilize its operation. The impedance conversion circuit 4 includes an impedance conversion circuit 4. It should be noted that the Josephson processor 2, voltage amplification circuit 3, and impedance conversion circuit 4 are all housed in a cooling container (not shown) to maintain the Josephson junction used in the superconducting circuit in a superconducting state. can do.

The output of the impedance conversion circuit 4 is then supplied to a semiconductor processing circuit 5, which may be located outside the cooling vessel. Thereby, the voltage amplification circuit 3 and the impedance conversion circuit 4 constitute an output driver circuit 1' that converts the output of the Josephson processor 2 into a signal suitable for processing by the semiconductor processing circuit 5. Since the impedance conversion circuit 4 has a high input impedance, the operation of the voltage amplification circuit 3 is not affected by connecting the semiconductor processing circuit 5.

FIG. 2 is a circuit diagram showing a specific configuration of the first embodiment of the present invention. This figure shows the detailed structure of the voltage amplification circuit 3 of the output driver circuit 1'. 5 and 6, which will be described later, only outline the Josephson processor 2, impedance conversion circuit 4, and semiconductor processing circuit 5. Impedance conversion circuit 4
The structure of will be explained in detail later. A Josephson processor may, for example, have the structure of a well-known IIR filter and include one or more Josephson elements, generally indicated as J. Furthermore, the semiconductor processing circuit 5 may take any known configuration and is supplied with input logic signals via a low impedance stripline 8.

With reference to FIG. 2, the voltage amplifier circuit 3 includes Josephson interferometer logic (JIL) gates 6 and 6', each of which has two impedances L connected in series.
a, Lb, and three Josephson junctions Ja, Jb, and Jc connected in parallel. In particular, each JIL gate 6 has an inductance La and Lb connected at one end to the central connection point. Bias current IB
is supplied from terminal P1 to the center connection point via resistor Rs. Furthermore, the Josephson junction Jb has one end connected to the center connection point, the Josephson junction Ja has one end connected to the second opposite end of the inductance La, and the Josephson junction Jc similarly has one end connected to the second opposite end of the inductance Lb. 2
connected to the end of the Further, the other ends of each Josephson junction Ja, Jb, and Jc are connected to each other to form a superconducting interferometer.

The JIL gate 6' has the same structure as the JIL gate 6 except for the following. That is, the second end of the Josephson junction Ja-Jc is the JIL gate 6
The bias current is shared with the Josephson junction Ja-Jc of JIL through the Josephson junction Ja-Jc.
It is supplied from gate 6. Therefore, JIL gate 6
and the JIL gates 6' are arranged in pairs, and the bias current Ib is passed through the center junction of the JIL gates 6' to the next pair. The Josephson junction Ja-Jc has, for example, a structure in which a thin aluminum oxide (Alox) film is sandwiched between a pair of Nb superconducting layers.

JIL gates 6 and 6' shown in FIG.
(total 34 in the illustration) extend from the output terminal of the Josephson processor 2 and are magnetically coupled to an external control line k which is grounded via a bias resistor RL, and each of the control lines k is It includes an inductance consisting of a pair of inductances LA, LB, which are connected in series corresponding to JIL gates 6 and 6'. In this way, in each set of JIL gates consisting of gate 6 and gate 6', inductance La and inductance Lb of JIL gates 6 and 6' are equal to inductance LA
and is coupled to the inductance LB.

FIG. 3 is a threshold curve diagram showing the threshold characteristics of the first embodiment of the present invention. The figure shows Josephson junction Ja
and Jc has a critical current of 0.1 mA, the Josephson junction Jb has a critical current of 0.2 mA, and both the inductances La and Lb have an inductance value of 3.4 pH. shows the static properties of In particular, the control line k for the bias current flowing through gates 6 and 6' is shown in the figure.
It is plotted as a function of the current Ic flowing through it. Furthermore, the highest bias current IB that can be supplied without causing a transition of the JIL gate obtains a value of approximately 0.4 mA with the above parameter settings.

As shown in FIG. 3, four different modes appear: "00", "01", "10", and "11". The mode "00" corresponds to the case where no magnetic flux quantum is held in the JIL gate 6 or 6' and corresponds to the logical value "0". On the other hand, modes "01" and "10" are either the first superconducting loop formed in the JIL gates 6 to 6' by the inductance La and the Josephson junctions Ja, Jb, or the first superconducting loop formed by the inductance Lb and the Josephson junctions Jb, Jc. This corresponds to the case where one flux quantum is held in any of the second superconducting loops formed in the same JIL gate. Furthermore, the characteristics are shown when both the first and second superconducting loops hold magnetic flux quanta. The point to note is that the shaded area in Figure 3 is J.
IL refers to the region where the Josephson junction forming the gate transitions to a finite voltage state. This area corresponds to a logical value of 1.

During operation, the bias current IB is set to a value such as the value IB1 shown in FIG.
is determined such that it does not transition to a finite voltage state when there is no input current IC on line k. Thereby, each JIL gate of the voltage amplifier circuit 3 is initially kept in a superconducting state.

On the other hand, when there is an input current IC in line k, the maximum value of the bias current (critical current) at which the JIL gate 6 or 6' does not cause a finite voltage transition is determined by the characteristic curve as a function of the input current Ic. In response to exceeding a threshold level, a transition is made to a finite voltage state. In a voltage amplifier circuit 3 in which a number of JIL gates are connected in series, the gate with the smallest IC1 value makes a transition first, followed by the other JIL gates. It should be noted that the voltage amplifier circuit 3 outputs an output signal on the line k1 connected to the resistor Rs as a voltage corresponding to the sum of the voltages present at each JIL gate. Output signal logic value of Josephson processor 2
The magnitude of the voltage thus obtained on line k1 for a logic value "0" can be, for example, 100 mV. be.

The voltage amplifying circuit 3 thus obtained has various advantages such as a large output voltage, reliability of operation, and easy increase/decrease in the number of JIL gates 6 and 6'. The point to note is that the number of JIL gates can be easily changed.
This is because the input current Ic to each JIL gate can be supplied by a single control line k that is magnetically coupled in series to all JIL gates. On the other hand, if logic signals are supplied to the JIL gates by a parallel fan-out configuration of line k, the current supplied to each JIL gate is expected to vary depending on the number of JIL gates involved, and the number of JIL gates, It is not easy to change the magnitude of voltage amplification.

FIG. 4 is a circuit diagram showing the main part of a second embodiment of the present invention. In the figure, JIL gates 6 and 6' shown in FIG. 2 are two Josephson junctions Ja' and Jb.
' have been replaced by JIL gates 16 and 16' with only '. Thus, each JIL gate 16 or 16' has the inductance La, Lb of the first embodiment.
Inductances La', Lb' connected as
The bias current IB is composed of the inductance La
', Lb' are supplied to the connection point where the first ends are connected to each other. Meanwhile, the Josephson junctions Ja' and Jb' are connected to the second ends of the inductances La' and Lb'. JIL gates 16 and 16' are arranged like JIL gates 6 and 6' in the first embodiment, and JIL gates 16 and 16' are arranged like JIL gates 6 and 6' in the first embodiment,
Josephson junction Ja' and JIL of L gate 16
Josephson junction Ja' of gate 16' is JIL
The gates 16 and 16' are connected in common on the sides opposite the ends connected to the inductance La'.

FIG. 4B shows the characteristics of JIL gates 16 and 16', with both Josephson junctions Ja' and Jb' having critical currents set at 0.2 mA, and inductances La' and Lb'. both have L/2 values, and the L is set to 5.18ph. With the parameters set as above, the maximum bias current IB that can flow without causing a transition in JIL gates 16 and 16' is 4.0 mA, corresponding to the case in Figure 3.
becomes the value of In FIG. 4B, the curve marked "0" represents the threshold bias current for a certain mode, and no magnetic flux quantum is held in the superconducting loops forming the JIL gates 16 to 16'. On the other hand, “1
” represents the threshold bias current for a mode in which one flux quantum is held in the superconducting loop that constitutes the JIL gate. In the figure, the shaded area is the This refers to the region where the Son junction transitions to a finite voltage state.

In this way, a similar voltage amplification operation is performed in the first
A second example with JIL gates 16 and 16' used in place of JIL gates 6 and 6' in the embodiment of
This can be obtained in this example. However, the structure of the first embodiment is preferable. The reason is that this embodiment has a wider region (shaded in FIGS. 3 and 4(B)) for transition to a finite voltage state, so there is more margin for operation.

FIG. 5 is a circuit diagram showing a specific configuration of a third embodiment of the present invention. This figure shows the structure of a voltage amplification circuit according to a third embodiment. In the figure, parts corresponding to the parts described above are given the same reference numerals, and the explanation thereof will be omitted.

In this embodiment, the control line k of the first embodiment is a first control line kk and a second control line k.
k', the JIL gates 6, 6' (34 in total) are divided into a first group containing 17 JIL gates 6, 6' and a second group containing the same number of JIL gates 6, 6'. . The first control line kk is sequentially coupled to the first group of JIL gates 6, 6', and the second control line kk' is coupled to the second group of JIL gates 6, 6'.
6'. In this structure, the length of the line kk or kk' is shortened by half, and the signal delay due to the inductance of the control line is reduced.

FIG. 6 is a circuit diagram showing a specific configuration of the fourth embodiment. In the first to third embodiments, the resistor Rs for sending the bias current IB can be replaced with an active element such as a transistor shown in the figure. figure
The embodiment shown in 6 is a modification of the first embodiment. Since the structure and operation are obvious, further explanation thereof will be omitted. HEMT (high electron transfer transistor)
, HBT (heterojunction bipolar transistor), M
A composite transistor that can operate in the low temperature environment of liquid helium, such as an ESFET (metal semiconductor field effect transistor), can be used for the transistor 9.

FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention. This figure corresponds to another modification of the circuit of the first embodiment shown in FIG. In this example, the same JI
L gates 6 are connected in series, alternately replacing JIL gates 6 and 6'. In the figure, only the voltage amplification circuit 3 is shown. Even in this case, the operating characteristics explained in connection with FIG. 3 apply, and voltage amplification is possible. The same reference numerals are given to the parts corresponding to the parts already described in connection with the previous figure, and the explanation thereof will be omitted.

FIG. 8 is a layout diagram showing the configuration of the first embodiment, and FIG. 9 is a layout diagram showing the configuration of the fifth embodiment. Figure 8 and Figure 9 are voltage amplification circuit 3
shows the layout.

FIG. 8 shows a superconductor pattern corresponding to the inductances La and Lb of the JIL gate 6. This pattern 11 is a Josephson junction Ja,
It is connected to another superconductor pattern 12 via Jb and Jc. Furthermore, superconductor pattern 12 is JIL
Extending towards gate 6', Josephson junction Ja, J
Inductance La of gate 6 via b, Jc,
It is connected to the superconductor pattern 11 that constitutes Lb. As a result, the bias current IB flows from the superconductor pattern 11 to J via the Josephson junctions Ja, Jb, and Jc.
From the superconductor pattern 12 of the JIL gate 6 to the superconductor pattern 12 of the JIL gate 6, to the superconductor pattern 11 of the JIL gate 6' via Josephson junctions Ja, Jb, and Jc, and then to the superconductor pattern 11 of the JIL gate 6' It flows into the superconductor pattern 11.

In the layout of FIG. 8, the control line k made of superconductor strips is magnetically coupled to the superconductor pattern 11 of the JIL gate 6, which is formed corresponding to this pattern 11. 11, which is separated from this loop 11 by an insulating layer. Control line k is further connected to JIL gate 6
', forming a loop corresponding to the superconductor pattern 11 of the gate 6'. Furthermore, the control line k extends to the next JIL gate 6 , where this line k forms another loop and connects with the superconductor pattern 11 forming the JIL gate 6 . The point to note in the layout pattern of FIG. 8 is that another path is formed in line k at the portions marked X, Y, and Z as shown in the figure. These paths form parasitic inductance, and therefore, although the structure of the first embodiment is reliable in voltage amplification operation, it is not sufficient in terms of operating speed of the Josephson circuit. This same problem is seen in the embodiment shown in FIG. As can be seen from FIG. 9, additional paths X and Y appear which cause a delay in the signal propagation on line k.

In FIG. 9, parts corresponding to those in FIG. 8 are given the same reference numerals, and their explanations will be omitted. What should be noted in FIG. 9 is that the superconductor 12 of the JIL gate 6 is in turn connected to the superconducting pattern 11 of the JIL gate 6 via a contact hole 13.

A sixth embodiment of the invention which minimizes the delay problem will now be described in conjunction with FIGS. 10 and 11.

FIG. 10 is a circuit diagram showing the configuration of the sixth embodiment. With reference to FIG. 10, the control line 1 each includes a plurality of inductances LA connected in series in succession, and a plurality of inductances LB connected in series in succession after these LA. In this, each inductance LA is magnetically coupled to the corresponding inductance La of the corresponding JIL gate, and each inductance LB is magnetically coupled to the corresponding inductance Lb of the corresponding JIL gate. Each JIL gate J1, J
1', , Jn have the same configuration as the previously described JIL gate, and a description of the operation of the voltage amplification circuit will be omitted.

FIG. 11 is a layout diagram corresponding to the sixth embodiment of the present invention. In relation to FIG. 11, JIL gates J1, J1', , Jn have inductances La, Lb
form. The pattern 22 includes a superconductor pattern 22 corresponding to the superconductor pattern 11 shown in FIG.
A bias current 18 is supplied from the terminal P1. The bias current IB is then applied to the Josephson junctions Ja, Jb,
The superconductor pattern 25 corresponding to the superconductor pattern 12 shown in FIG. 10 is supplied via Jc. The bias current IB supplied to this superconductor pattern 25 is then J
IL Gate J1' flows into the superconductor pattern 22 forming the inductances LA, LB of gate J1'. Furthermore, the bias current IB is supplied to the next stage JIL gate, and finally the last JIL gate Jn
reach.

In this structure, the control line k is connected to the portions 23a,
JIL gates J1, J1',,, at 23b and 24
Magnetically coupled to Jn. Therein part 23a
is coupled to the superconductor pattern 22 forming an inductance La at each JIL gate, and the portion 23b
is coupled to a superconductor pattern 22 forming the inductance Lb of each JIL gate. Furthermore, part 2
4 is a portion 23a for one JIL gate, and
It extends between portions 23a for the next JIL gate. More precisely, portions 23a and 24 appear repeatedly in the left half of line k2, while portions 23 and 24 appear repeatedly in the right half of line k2. Furthermore, the left and right halves of this line k are connected at the bottom by a portion 24, as shown. Points to note in Figure 11 are X and Y in Figure 8 or Figure 9.
Alternatively, another inductance with the Z portion is no longer formed and the circuit is more responsive when operating.

FIG. 12 is a circuit diagram showing the main parts of a seventh embodiment of the present invention. This figure corresponds to a modified example of circuit 3 of FIG. 10. In the same figure, the control line k is
The first control line kk and the second control line kk'
This first control line 11 is sequentially connected to the inductance L on the left of the JIL gates J1, J1', .
a, and is finally grounded via a resistor RL1. On the other hand, the line kk' is sequentially coupled to the inductance Lb on the right of the JIL gate, and is connected to the resistor R1
2 and is grounded via. In particular, line kk includes inductances LA connected in series one after another, while line kk' includes inductances LB connected in series and one after another. According to this embodiment, the response of the voltage amplifier circuit 3 is further improved by reducing the number of signal paths for coupling the line logic signals to the JIL gate.

Next, an eighth embodiment of the present invention relating to an impedance conversion circuit of which only an outline has been shown will be described. In particular, in order to ensure operational reliability of the voltage amplification circuit 3, the circuit immediately following this circuit must have sufficiently high impedance. This is because the direction of the drive current IB must not change during the transition operation of the Josephson junctions Ja, Jb, and Jc forming the JIL gate.

FIG. 13 is a circuit diagram showing the configuration of an eighth embodiment of the present invention. Voltage amplification circuit 3 in line k1
The output of
sent to the gate. The HEMT transistor has a drain connected to a DC voltage source E2, and has a drain connected to a voltage amplification circuit 3.
The current flowing from the drain is controlled according to the logic output of the drain. At this time, the logic output of the voltage amplification circuit 3 is supplied to the HEMT gate together with the bias voltage. It is thus supplied via an inductance L3 from another DC voltage source. An output current is thereby obtained at the power supply of the HEMT transistor, and the current obtained in this way is supplied to the semiconductor processor 5 via a commonly used strip line with an impedance of 50 ohms.

FIG. 13 is a circuit diagram showing the configuration of an eighth embodiment of the present invention. In the figure, an extremely large impedance of approximately several megohms or more can be obtained at the input side of the impedance conversion circuit 4, while a low impedance such as 50 ohms is possible in the impedance conversion circuit 4 in preparation for external connection. be. As a result, the switching operation of the Josephson junction included in the JIL gate forming the voltage amplification circuit is controlled by the impedance conversion circuit 4.
The reliability of the operation of the voltage amplifying circuit 3 is guaranteed without being influenced at all by the output current supplied to the voltage amplifying circuit 3. on the other hand,
The circuit 4 allows a low output impedance suitable for driving the semiconductor processor 5 through a coaxial cable or stripline followed by the superconducting circuit 1. Transistor TR of impedance conversion circuit 4 is H
Not limited to EMT, HBT using GaAs active layer
, MESFET, or MOSFET that operates below the liquid helium temperature environment.

FIG. 14 is a circuit diagram showing the structure of a ninth embodiment of the present invention. In the figure, a transformer T is used for impedance transformation. This transformer T has a primary superconducting winding L1 connected to line kk via a resistor RL', and a primary superconducting winding L1 that is magnetically coupled to this winding L1.
It has a next-side superconducting winding L2. The superconducting winding L1 has at least one times as many turns as the superconducting winding L2, allowing a large impedance to the line kk. On the other hand, the secondary superconducting winding L2 has a low impedance suitable for taking out the output via the low impedance strip line 8.
It can be obtained with

FIG. 15 is a circuit diagram showing essential parts of a tenth embodiment of the present invention. In the figure, HBTs TR1 and TR2 are used to form an ECL gate. The output of this ECL gate is supplied to the strip line 8 through another HBT 8 having an emitter follower structure. In the example shown in the figure, the logic amplitude of the input logic signal from the voltage amplifier circuit 3 is approximately 0.1 volt,
The collector current of transistor TR1 flows through a path including a 100 ohm resistor R1, a 25 ohm resistor R2, and a 250 ohm resistor R5. Similarly, the collector current of transistor TR2 is 100 ohm resistor R3
, then flows through a 25 ohm resistor R4 and then joins the collector current of transistor TR1 at resistor R5. This causes approximately 4 mA of layer current to flow through resistor R5. The input logic signal from the voltage amplifier circuit 2 is fed to the base of the transistor TR1, while
Transistor TR2 is supplied with a 0.05 volt reference voltage at its base. Transistor TR3 is now formed at the base of transistor TR1 and at its collector.
It takes over the output of the CL gate and supplies it with an emitter with an emitter-follower structure. Therefore, the transistor T
It is supplied by the emitter of R3. For this reason, the emitter of transistor TR3N is connected to a resistor R6 of approximately 250 ohms.
to the voltage source VEE. Thereby, a collector current of 4 mA flows through transistor TR3. In this structure, an input logic amplitude of approximately 0.1 volts is further amplified, and a logic amplitude of approximately 0.2 volts is obtained at the strip line 8 forming the outgoing terminal of the circuit 4. Due to the emitter follower structure of transistor TR3, a low output impedance is achieved, matching the 50 ohm impedance of the stripline. On the other hand, a large input impedance is obtained at the base of transistor TR1.

By providing the impedance conversion circuit 4, the operation of the voltage amplification circuit 3 is stable regardless of the input impedance of the semiconductor processor 5 connected after the superconducting circuit 1.

[0048]

According to the present invention, the output driver circuit of the present invention includes a voltage amplifier circuit and an impedance conversion circuit for increasing the logic amplitude of an output amplitude signal, and the voltage amplifier circuit includes one or more Josephson junctions. and an impedance conversion circuit that receives the output signal of the voltage amplifier circuit is connected, and since the impedance conversion circuit has a high impedance, the operation of the voltage amplifier circuit is not affected by the current flowing to the impedance conversion circuit.

In addition, a sufficiently large output voltage can be obtained from the impedance conversion circuit to drive the semiconductor circuit,
In this case, reliable voltage conversion is possible since no adverse effects occur on the operation of the intensifier circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the principle of the invention.

FIG. 2 is a circuit diagram showing a specific configuration of a first embodiment of the present invention.

FIG. 3 is a threshold curve diagram showing threshold characteristics of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing main parts of a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific configuration of a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a specific configuration of a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing main parts of a fifth embodiment of the present invention.

FIG. 8 is a layout diagram showing the configuration of the first embodiment of the present invention.

FIG. 9 is a layout diagram showing the configuration of a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram showing the configuration of a sixth embodiment of the present invention.

FIG. 11 is a layout diagram corresponding to a sixth embodiment of the present invention.

FIG. 12 is a circuit diagram showing main parts of a seventh embodiment of the present invention.

FIG. 13 is a circuit diagram showing the configuration of an eighth embodiment of the present invention.

FIG. 14 is a circuit diagram showing the configuration of a ninth embodiment of the present invention.

FIG. 15 is a circuit diagram showing essential parts of a tenth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a conventional Josephson gate circuit.

FIG. 17 is a diagram showing the operation of a conventional Josephson gate circuit.

[Explanation of symbols]

1 Superconducting circuit 1’ output driver circuit 2 Josephson processor 3 Voltage amplification circuit 4 Impedance conversion circuit 5 Load circuit

Claims (2)

[Claims] 1. A Josephson operation circuit that performs a logic operation and outputs the result as an output logic signal having a first logic amplitude, and converts the result into a logic amplitude suitable for processing performed by the output logic element and an external circuit. In superconducting circuits that output signals, each has magnetic field control lines that are magnetically coupled to each other and is supplied with a bias current, and depending on the signal on the control line, the superconducting state transitions to a finite voltage state, and as the transition occurs, the basic logic A plurality of superconducting quantum interference devices that generate amplitude are connected in series, and the output logic signal is passed through a control line so that the bias current sequentially flows through the plurality of superconducting quantum interference devices, Voltage amplification configured to sequentially flow through a plurality of superconducting quantum interference elements and outputting to an output terminal a logic signal having a second logic amplitude that is substantially larger than the first logic amplitude as a sum of the basic logic amplitudes. means connected to the output terminal and connected to the external circuit;
is suitable for outputting a logic signal having a logic amplitude of and impedance conversion means having an output impedance that does not flow out from the output terminal. 2. One of the superconducting quantum interference elements includes a first superconducting loop in which a first Josephson junction, a second Josephson junction, and a first inductance are connected in a loop; a second superconducting loop in which a Josephson junction, a third Josephson junction, and a second inductance are connected in a loop; a first magnetic field control line magnetically coupled to the first inductance; A superconducting circuit including a second magnetic field control line magnetically coupled to an inductance of the first Josephson junction of each superconducting quantum interference device, the superconducting circuit connecting the first Josephson junctions of each superconducting quantum interference device in series, the first A superconducting circuit characterized in that two magnetic field control lines and a second magnetic field control line are connected in series.