JPH0421031A - Register reallocating system - Google Patents

Abstract

PURPOSE:To reduce the size of an object program and to improve the execution speed by investigating a state of a dependence relation related to a register of an instruction and an equivalence relation between a memory and a register and executing a reallocation of the register and eliminating an unnecessary load instruction. CONSTITUTION:An inter-block register flow analyzing means 3 investigates a dependence relation of a register between instruction blocks divided by an instruction block dividing means 2 and derives a register living in an inlet and an outlet of the instruction block, and an equivalence relation analyzing means 4 analyzes a state of an equivalence relation of an instruction along a control flow with regard to the instruction block of an equivalence relation analytic object. Subsequently, when there is an unnecessary load instruction from a memory in which the equivalence relation is analyzed, a register reallocating means 5 executes a reallocation of the register so that there is no inconsistency and eliminates an unnecessary load instruction, and an instruction output means 6 outputs a list of instructions to which the register is reallocated to an instruction store medium 10. In such a way, the size of an object program can be reduced, and the executing speed can also be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a register reallocation method, and in particular, register reallocation on an architecture that has load/store instructions between memory and registers and does not have indirect branch instructions. Regarding the method.

[Conventional technology]

Traditionally, register allocation has been done to intermediate text inside the compiler or to text after code generation, and there is no way to re-allocate registers (including register allocation) after machine language instruction generation is complete. Ta.

[Problem to be solved by the invention]

In the conventional register allocation method described above, register allocation was done to intermediate text inside the compiler or to text after code generation, so it is not necessary to have an equivalence relationship (memory contents at a certain point during instruction execution). Register allocation is not always done taking into account the relationship that the content of the register has the same value, and unnecessary load instructions that do not make effective use of the equivalence relationship may be generated.
This has the drawback of increasing the size of the object program and decreasing the execution speed.

Furthermore, since registers are allocated to intermediate text or text after code generation that depends on the compiler configuration, there is a drawback that it is necessary to prepare a compiler-specific register allocation process for each compiler.

In view of the above-mentioned points, an object of the present invention is to analyze a sequence of instructions along the control transition of the sequence of instructions, investigate dependencies regarding registers of instructions and equivalence relationships between memory registers, and reallocate registers. The object of the present invention is to provide a register reallocation method that reduces the size of an object program and improves its execution speed by eliminating unnecessary load instructions.

[Means to solve the problem]

The register reallocation method of the present invention is based on an architecture that has load/store instructions between memory registers and no indirect branch instructions. Analyzes the instructions expanded on the memory by this instruction input means, divides the sequence of instructions immediately after the branch instruction and at the branch destination label position to create instruction blocks, and controls the control between the divided instruction blocks. An instruction block dividing means that determines the flow and limits the instruction blocks to be analyzed for equivalence relations, and an instruction block dividing means that investigates the register dependencies between the instruction blocks divided by this instruction block dividing means and determines the register dependencies at the entrance and exit of the instruction blocks. an inter-block register flow analysis means for determining registers; an equivalence relation analysis means for analyzing the state of instruction equivalence relations along the control flow for instruction blocks to be analyzed for equivalence relations limited by the instruction block division means; If there is an unnecessary load instruction from the memory whose equivalence relation has been analyzed by the relation analysis means, register reallocation is performed to ensure there are no conflicts and the unnecessary load instruction is deleted. and an instruction output means for outputting a sequence of instructions whose registers have been reallocated by the means to an instruction storage medium.

[Effect]

In the register reallocation method of the present invention, the instruction input means inputs a sequence of instructions from the instruction storage medium and expands them onto the memory, and the instruction block dividing means analyzes the instructions expanded onto the memory by the instruction input means. The sequence of instructions is divided into instruction blocks immediately after the branch instruction and at the branch destination label position, and the flow of control between the divided instruction blocks is determined to limit the instruction blocks subject to equivalence relationship analysis, and registers between blocks are determined. The flow analysis means investigates the register dependencies between the instruction blocks divided by the instruction block division means and determines registers that are active at the entrance and exit of the instruction block, and the equivalence relation analysis means is limited by the instruction block division means. Analyze the state of equivalence relations of instructions along the control flow for the instruction block to be analyzed for equivalence relations,
For register reallocation, if there is an unnecessary load instruction from the memory whose equivalence relations have been analyzed by the equivalence relation analysis means, the registers are reallocated so that there are no conflicts, the unnecessary load instructions are deleted, and the instruction output means The register reallocation means outputs the sequence of instructions for which register reallocation has been completed to the instruction storage medium.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a register reallocation system according to an embodiment of the present invention. Register reallocation in this embodiment is performed by an instruction manual means 1, an instruction block division means 2, an inter-block register flow analysis means 3, an equivalence relation analysis means 4, a register reallocation means 5, and an instruction output. means 6, an instruction expansion memory 7, a plurality of block tables 8, a plurality of equivalence relation tables 9, and an instruction storage medium 10, which is composed of files, memories, etc., and stores machine language instructions (hereinafter simply referred to as instructions). It is configured.

Referring to FIG. 2, each block table 8 includes an address sequential chain, an address pre-sequential chain, an instruction pointer, a register alive at the entrance, a register alive at the exit, and the number of immediately preceding blocks (P ), the number of immediately following broncs (S), the immediately preceding block pointer of the immediately preceding block number (p>), the immediately following block pointer of the immediately following block number (S), the equivalence relation table pointer, and the non-target block flag. and an equivalence relationship analysis completed flag.Each block table 8 is chained in address order from the block table starting point pointer by an address sequential chain and an address sequential chain.The instruction pointer is connected to the instruction expansion memory. 7 or a relative offset within the expanded instruction on the instruction expansion memory 7, and the corresponding instruction block in the instruction expanded on the instruction expansion memory 7 (hereinafter simply referred to as a block)
It points to the first instruction. The immediately preceding block pointer points to the block table 8 of the block that immediately precedes the block in the block table 8 in the control flow. The immediately succeeding block pointer points to the block table 8 of the block immediately following the block of the relevant block table 8 on the control flow.

The equivalence relation table pointer points to the equivalence relation table 9 when the block in the block table 8 is a block to be analyzed for equivalence relations (hereinafter referred to as a block to be analyzed for equivalence relations). The non-target block flag is a flag for identifying a block that is not subject to equivalence relationship analysis. The equivalence relationship analysis processing completed flag is a flag for identifying whether the block to be analyzed for equivalence relationships has been processed.

Similarly, referring to FIG. 2, the equivalence relationship table 9 is composed of a plurality of equivalence relationship information consisting of an equivalence register, an address of an equivalence memory (for example, based on pace register B2), and a length.

Next, the operation of the register reallocation system of this embodiment configured as described above will be explained.

First, the instruction input means 1 inputs instructions one by one from the instruction storage medium 10, expands them onto the instruction expansion memory 7, and then
The instruction block dividing means 2 is called.

The instruction block dividing means 2 analyzes the instruction code and performs block dividing processing only when the instruction is a branch instruction. A block is a unit in a sequence of instructions that has one entrance and one exit for control purposes, and there are no branches other than the exit, and the divided blocks are as shown in Figure 2. , the block table 8 is stored in the instruction expansion memory 7 by the instruction pointer.
It is indicated by pointing to the first instruction of the block inside. In the block division process, the instruction block division means 2 divides the block immediately after the branch instruction and at the branch destination Rahel position by the following processes 2.1 to 2.4, and performs process 2.
5 to limit the blocks to be analyzed for equivalence relations.

Search the program table 8 pointing to the instruction immediately after the electric branch instruction using the instruction pointer, and if it already exists, do nothing. If not, block table 8
The instruction pointer is set to the instruction immediately after the branch instruction as the first instruction of the block, and the created block table 8 is created using the address sequential chain and the address sequential chain in the order of the instructions' addresses to create the block table immediately before and after the branch instruction. Chain with 8.

Crab 1 Yu 1: When the branch instruction is a conditional branch instruction, the block table 8 pointing to the first instruction of the block containing the conditional branch instruction and the block table 8 pointing to the instruction immediately after the conditional branch instruction are used as the immediately preceding block pointer and Chain with each other by the immediately following program pointer. Here, the immediately preceding block refers to the immediately preceding block on the control flow, and the immediately following block refers to the block immediately following on the control flow.

Process I-1: If the branch is a downward branch from the branch relative offset of the branch instruction, create block table 8 unconditionally,
The block table 8 created in the same manner as in Process 2.1 is chained with the immediately preceding and succeeding block tables 8 using an address sequential chain and an address forward chain in the order of the addresses of the instructions, and further blocks containing branch instructions are created in the same manner as in Process 2.2. The block table 8 pointing to the first instruction of the block table 8 is chained with the bronch pieces 8 of the immediately preceding block and immediately following block in control flow order using the immediately preceding bronc pointer and the immediately following block pointer.

n↓Works: If the branch instruction is an upward branch from the branch relative offset, create a professional block table 8 only when there is no block table 8 pointing to the branch destination instruction.
When the block table 8 created in the same manner as in process 2.1 is chained with the immediately preceding and succeeding block 9-bull 8 in the address order of the instructions using the address sequential chain and the address forward chain, and a new block table 8 is not created. Similarly to Process 2.2, the block table 8 that points to the first instruction of the block containing the branch instruction is updated in the order of the control flow using the immediately preceding block pointer and the immediately following block pointer. Chain with 8.

! ! I! JLL-i: If it is an upward branch from the branch relative offset of a branch instruction, there is a possibility of a loop, so trace the blocks in the reverse order of addresses from the block containing the branch instruction, and check all blocks up to the branch destination block. As a block that is not subject to equivalence relation analysis, a non-target block flag is set in each block table 8.

By repeating the processing by the instruction input means 1 and the instruction block division means 2 and processing all the instructions, a control flow of 8 units of block tables is completed, and at the same time, blocks to be analyzed for equivalence relationships that are not included in the loop on the control flow are It can be recognized by the non-target block flag.

Next, the inter-block register flow analysis means 3 determines the dependency relationship of registers between blocks (relationship of whether or not the value is inherited across blocks, and whether the register is "active" while the value on the register is inherited). ) to represent the register flow between blocks.
Registers that are active at the entrance of each block and registers that are active at the exit of each block are set in the block table 8 for all blocks. Specifically, after performing process 3.1, the inter-block register flow analysis means 3 repeats processes 3.2 to 3.3 in the reverse order of the control flow.

Process 1d: Set a register that is alive at the exit of the block in the block table 8 of the last block on the control flow.

mU1: Assign the register that satisfies either of the following conditions ■ and ■ to the register that is alive at the entrance of the block.
Set in block table 8.

■ Lives at the exit of the block and is not defined by its professional seven.

■ The first register access instruction that appears in a block is a register reference instruction.

Processing plate master - master: A register that satisfies the following condition (1) is set in the block table 8 as a register that resides at the exit of the block.

■ It is alive at the entrance of the bronc immediately following it.

Next, the equivalence relation analysis means 4 uses the equivalence relation table 9 chained by the equivalence relation table pointer from the block table 8 as shown in FIG. Analyze relationships (equivalence relationships here are relationships in which the contents of memory and the contents of registers have the same value at a certain point during instruction execution,
(commonly related by memory-to-register load and register-to-memory store instructions)
. Specifically, the equivalence relationship analysis means 4 traces the block table 8 in the order of the control flow from the block table starting point pointer, and performs the process 4 on each of the sets of blocks to be analyzed for equivalence relationships that have formed a cluster on the control flow. After executing .1, processes 4.2 to 4.4 are repeatedly executed until block B is not found in process 4.4.

Processing (engineering: Traverse block table 8 in order of control flow, search for block B that satisfies either of the following conditions ■ and ■, generate and initialize equivalence relation table 9, and use equivalence relation table pointer Chaining.

■ There is no immediate preceding block (the number of immediate preceding blocks is 0)
.

■ All immediately preceding blocks are blocks that are not subject to equivalence relationship analysis (the non-target block flag is set) or blocks that have been subjected to equivalence relationship analysis (the equivalence relationship analysis completed flag is set).

1L4ff engineering: Performs one of the following processes (1), (2), and (2) for all instructions in block B, depending on the type of each instruction in control order.

1 If the address and length (determined by the instruction) of the load source memory for load t are set in equivalence relation table 9 (= if an equivalence relationship is attached to the load source memory), register reloading is performed. The allocation calls means 5. In other cases, the address and length of the load source memory and the load destination register are set in the equivalence relation table 9.

■ If the equivalence relation table 9 is set for any part of the memory indicated by the address and length of the 8-person storage destination of store t (= equivalence relation for even part of the memory of the storage destination) ), the equivalence relationship information is deleted from the equivalence relationship table 9. Furthermore, the address and length of the storage destination memory and the storage source register are set in the equivalence relation table 9.

■ Neither load nor store 4 Do nothing.

Write! ``Yo-''-The equivalence relationship information is inherited to the block to be analyzed for equivalence relationships among the blocks immediately following block B as follows.

■ Block table 8 of the block immediately following block B
If the equivalence relation table pointer of block B is a null pointer, an equivalence relation table 9 is generated and chained by the equivalence relation table pointer from the block table 8, and the equivalence relation table 9 of block B is created.
Copy.

■ Block table 8 of the block immediately following block B
If the equivalence relationship table pointer of is not a null pointer, the equivalence relationship information that is different from the content of the equivalence relationship table 9 of the block B out of the equivalence relationship information of the equivalence relationship table 9 is deleted.

■ Set the equivalence relationship analysis processed flag.

Processing ↓ 2nd step: Among the blocks immediately following Block B, block B satisfies all of the following conditions ■ and ■
shall be.

■ All immediately preceding broncs are blocks that are not subject to equivalence relation analysis or blocks that have undergone equivalence relation analysis.

■ It is a target block for equivalence relation analysis.

If there is no block that satisfies conditions (2) and (2), a block that satisfies the following conditions (2) and (2) in addition to the above conditions (2) and (2) is designated as block B, starting from the immediately preceding block of the block immediately following block B.

■ It is not Flock B.

■ It is a block that has not been subjected to equivalence relation analysis.

Condition ■ for the block immediately preceding the block immediately following block B
If there is no block that satisfies ~■, further follow the block that immediately precedes the block that satisfies condition ■~■, and find condition ■~
Find a block that satisfies (1) and call it block B. As a result, if there is even one flock that is not subject to equivalence relation analysis in the immediately preceding block of block B, and if the equivalence relation table pointer of the block table 8 of block B is an empty pointer, the equivalence relation table 9 is generated. It is initialized and chained from the block table 8 using the equivalence relation table pointer.

If the equivalence relation table pointer of the block table 8 of block B is not a null pointer, the equivalence relation table 9 is initialized.

When the register reallocation means 5 is called by the equivalence relation analysis means 4, it tries to reallocate the registers through the following processes 51 to 5.3 in order to take over the equivalence relations and delete unnecessary load instructions. Here, it is assumed that the block currently being processed is B, and that memory M and register R1 have an equivalence relationship. Also, a load instruction is executed from memory M to register R2, and an instruction with an equivalence relationship between memory M and register R1 is written as Si (i=1..., nun≧
1) Let α be the interval from the beginning of block B to the instruction immediately before the load instruction, and β be the interval from the instruction immediately after the load instruction to the end of block B.

Furthermore, for register R that can be referenced with a load instruction,
The active section γ (
R) and the active interval δ (R) of the register R after the load command is obtained as follows (however, the interval γ (R) and the interval δ (R) are the blocks of the target block for equivalence relation analysis. (within range).

For IIT (R) ■ If there is a definition instruction for register R (load instruction, operation instruction, etc.) in interval α, the last register in the interval after the last definition instruction for register R in interval α Let the interval up to the reference instruction of R be an interval γ (R). If there is no register R reference instruction in the interval after the last register R definition instruction in the interval α, only the register R definition instruction is transferred to the interval γ (
R).

■ If there is no definition instruction for register R within the interval α, the immediately preceding block PBi of block B (i=1°...,
n) in the reverse order of control, and let γi (R) be the interval from the first definition instruction for register R found to the load instruction and to the last reference instruction for register R. , the interval that is the sum of all the intervals from interval γ1 (R) to interval yn (R) is γ
(R). If there is no instruction to refer to register R, the procedure is the same as ■. If there is no definition instruction for register R in the immediately preceding block PBi, then the immediately preceding block PBi
Obtain in the same way by tracing the immediately preceding block.

) of day δ(R) ■ If there is a definition instruction for register R within interval β, then interval β
Let δ(R) be the interval up to the last reference instruction for register R in the interval before the definition instruction for the first register R in the register R. If there is no reference instruction for register R before the first definition instruction for register R within interval β, δ(R)=φ (empty).

(2) If there is no definition instruction for register R within interval β and register R is not alive at the exit of block B, the interval up to the last reference instruction for register R within interval β is set to 6 (R). If there is no instruction to reference register R within interval β, δ
(R)=φ.

■ If there is no definition instruction for register R within the interval β and register R is alive at the exit of block B, the block SBj to be analyzed for equivalence relations among the blocks immediately following block B
Follow the instructions in (j=1. ・=, m: m≧1) in control order, and trace the instructions from the load instruction to the first register R reference instruction found in the interval to the last register R reference instruction. Letting each interval be δj (R),
Let δ (R) be the sum of all the intervals from the interval δ1 (R) to the interval δm (R). If there is no reference instruction for register R, δj (R) =
Let it be φ.

If there is no definition instruction for register R in the block SBj to be analyzed for equivalence relations and register R is alive at the exit of block SBj to be analyzed for equivalence relations, then the block to be analyzed for equivalence relations among the blocks immediately following the block to be analyzed for equivalence relations SBj. Find it in the same way. If the register R is not alive at the exit of the block SBj to be analyzed for equivalence relations, the interval up to the last register R reference instruction in the block SBj to be analyzed for equivalence relations is set as δj (R).

``myu'' engineering: Attempts to delete the load instruction by replacing register R2 defined in the load instruction with register R1. If the following condition (2) is satisfied, register R2 in the reference instruction for register R2 in interval δ(R2) is changed to register R1, and the load instruction is deleted.

■ While register R2 defined by a load instruction is alive, there is no definition instruction for register R1.

In other words, if the load instruction is deleted while satisfying the [δ(R2) Definition instruction condition for trunk register R1], and if the interval δ(R2) spans a block other than block B, the connection with the spanned block is Reexamine the register dependencies between each pro.

The information of the live registers is reset in each block table 8 at the entrance and exit of the block.

myu main: If it is impossible to delete the load instruction by replacing register R2 with register R1 in process 5.1,
An attempt is made to eliminate the load instruction by replacing register R1 with an equivalence relationship with register R2. If the following condition (2) is satisfied, the register R1 of the definition/reference instruction for register R1 in the interval (γ (R1) + δ(R1)l) is changed to register R2, and the load instruction is deleted.

(2) While the register R1 with the equivalence relationship in the instruction Si is alive and the register R2 defined by the load instruction is alive, it is removed, and there is no definition/reference instruction for the register R2. That is, [γ(R1)+δ(R1)−δ(
R2) Definition/reference command of main disk R2] If the condition ■ is satisfied and the load command is deleted, the section (
If γ (R1) + δ (R1)l spans a block other than block B, re-examine the register dependencies with the spanned block and check the registers that are alive at the entrance and exit of each block. information is reset in each block table 8.

Mars] Uni: Processing 5.2 register R1 to register R
If it is also impossible to delete the load instruction by replacing it with 2, the registers are not reallocated.

The instruction output means 6 optimizes all the blocks to be analyzed for equivalence relations by the equivalence relation analysis means 4 and the register reallocation means 5, and then outputs the registers to any instruction storage medium 10 in which instructions have been stored. Outputs the list of instructions that have been reallocated.

〔Effect of the invention〕

As explained above, the present invention analyzes an instruction sequence along the sideward transition of the instruction sequence, investigates the dependencies of instructions on registers and the state of equivalency relationships between memory registers, and reallocates registers. By deleting unnecessary load instructions, the size of the object program can be reduced and the execution speed can be improved.

In addition, since it is applied to machine language instructions, it can be applied universally to compilers on the same architecture, and it can also be applied to object programs output by compilers. be.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a register reallocation method according to an embodiment of the present invention, and FIG. 2 is a diagram showing the contents of the instruction expansion memory, block table, and equivalence relationship table in FIG. 1. In the figure, 1... instruction input means, 2... instruction block division means, 3... inter-block register flow analysis means, 4...
Equivalence relationship analysis means, 5...Register reallocation means, 6...Instruction output means, 7...Instruction expansion memory, 8...Block table, 9...Equivalence relationship table, 10...Instruction It is a storage medium.

Claims (1)

[Scope of Claims] An instruction input means for inputting a sequence of instructions from an instruction storage medium and expanding them onto memory in an architecture that has load/store instructions between memory and registers but does not have indirect branch instructions; Analyzes the instructions expanded on the memory by the instruction input means, divides the sequence of instructions immediately after the branch instruction and at the branch destination label position, creates instruction blocks, and determines the flow of control between the divided instruction blocks. An instruction block dividing means that limits the instruction blocks to be analyzed for equivalence relations, and a block that investigates register dependencies between instruction blocks divided by this instruction block dividing means and finds registers that are alive at the entrance and exit of the instruction block. an equivalence relation analysis means for analyzing the state of instruction equivalence relations along the control flow for the instruction block to be analyzed for equivalence relations limited by the instruction block division means; A register reallocation means that reallocates registers and deletes unnecessary load instructions to avoid conflicts if there is an unnecessary load instruction from memory whose equivalence relationship has been analyzed, and register reallocation by this register reallocation means. 1. A register reallocation method comprising: instruction output means for outputting a sequence of completed instructions to an instruction storage medium.