JPH04141737A - Register re-assignment system - Google Patents

Abstract

PURPOSE:To reduce object size by studying the dependence of included commands on a register as well as the state of equivalence relationships between a memory and the register with respect to a command block which is a maximum unit of the linear migration of control, executing re-assigning the register and deleting unnecessary commands. CONSTITUTION:The system consists of a command input means 1, a command block dividing means 2, a means 3 analizing register flow between blocks, an equivalence relationships analizing means 4, a register re-assignment means 5, a command output means 6, a command development memory 7, block tables 8, equivalence relationships table 9 and a command storage medium 10. With respect to a command block which is a maximum unit of the linear migration of control, the dependence of included commands on the register as well as the state of the equivalence relationships between the memory and the register are studied, the re-assignment of the register is executed and unnecessary load commands are deleted. Thus, the object size can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for register reallocation, particularly register reallocation on architectures that have load/store instructions between memory and registers but do not have indirect branch instructions. is related to the method.

[Conventional technology]

Traditionally, register allocation has been done to intermediate text inside the compiler or to text after code generation, and register allocation has to be done again after machine language instruction generation (including register allocation) has been completed. There was no.

[Problem to be solved by the invention]

Conventional register allocation methods for intermediate text inside the compiler or text after code generation described above do not necessarily involve equivalence relationships (at some point during instruction execution,
A relationship in which the contents of memory and the contents of a register are the same value)
Renostar allocation is not always carried out in consideration of this, and unnecessary load instructions that do not effectively utilize equivalence relationships may be generated, leading to problems such as an increase in object size and a decrease in execution speed. .

Furthermore, since registers were allocated to intermediate text depending on the compiler configuration or text after food generation, there was a problem in that each compiler had to prepare a process for register allocation specific to Hubbaira.

An object of the present invention is to provide a register reallocation method that can reduce object size, improve execution speed, and eliminate the need for compiler-specific register allocation processing for each compiler.

[Means to solve the problem]

The register reallocation method of the first invention is an architectural register reallocation method that has load/store instructions between memory and registers and does not have indirect branch instructions. (B) An instruction input means for inputting a sequence of instructions from a medium and expanding it onto a memory; (B) analyzing the inputted instructions and dividing the sequence of instructions immediately after a branch instruction and at a branch destination label position to create an instruction block; (C) An instruction block dividing means for determining the flow of control between the instruction blocks created and divided at the same time; (D) For an instruction in the divided instruction block, the contents of the memory and the contents of the register have the same value at a certain point during instruction execution. (E) an equivalence relationship analysis means for analyzing the state of an equivalence relationship that violates the relationship; Register reallocation is a means to delete unnecessary load instructions. (F) After performing equivalence relationship analysis and register reallocation for all the divided instruction blocks, register reallocation is carried out on the medium where the instructions were stored. The apparatus includes an instruction output means for outputting a list of completed instructions.

In addition, the register reallocation method of the second invention has load/store instructions between memory and registers, and the register reallocation method based on the architecture does not have indirect branch instructions. (B) Analyzes the input instructions and divides the instruction sequence immediately after the branch instruction and at the branch destination label position to generate instructions. (C) Definition of registers between the divided instruction blocks (C) Definition of registers between the divided instruction blocks
interpreting reference dependencies and finding live registers at the entry/exit of the instruction block; (D) instructions in the divided instruction block (1. A step to analyze the state of an equivalence relationship in which the contents of the memory and the contents of the register have the same value; (E) If there is an unnecessary load instruction from the memory with the equivalence relationship, it is determined whether there is a contradiction. (F) All divided instruction blocks (after performing equivalence relationship analysis and register reallocation) The program is configured to execute a step that outputs a sequence of instructions that have been stored on the medium (this register reallocation has been completed).

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The register reallocation shown in Figure 1 consists of an instruction input means 1 that inputs a sequence of instructions from a medium storing instructions and expands them on memory, and an instruction input means 1 that analyzes the input instructions and stores them immediately after the branch instruction and at the branch destination. An instruction block dividing means 2 which creates instruction blocks by dividing a sequence of instructions at label positions and simultaneously determines the flow of control between the divided instruction blocks; Inter-block register flow analysis means 3 to investigate and find registers that are alive at the entrance/exit of an instruction block.For instructions in divided instruction blocks, the contents of memory and the contents of registers are the same at a certain point during instruction execution. Equivalence relationship analysis means 4 that analyzes the state of equivalence relationships that indicate value relationships.If there is an unnecessary load instruction from memory with an equivalence relationship, registers are reallocated to avoid conflicts and the unnecessary load instructions are removed. Means 5 is an instruction to perform equivalence relation analysis and register reallocation for all divided instruction blocks, and then output a sequence of register reallocated instructions to the medium where the instructions were stored. output means 6,
It is composed of an instruction expansion memory 7, a block table group 8, an equivalence relationship table 9, and an instruction storage medium (file or memory) 10.

Note that the flow of processing between each block in FIG. 1 is shown by thick line arrows, and the flow of data is shown by thin line arrows.

Next, the operation will be explained.

First, the command input means 1 inputs a sequence of commands from any medium (file or memory) '10 storing commands. Input is performed one instruction at a time, and after expansion on the instruction expansion memory 7, the instruction is analyzed by the instruction block dividing means 2 for each instruction. The sequence of instructions is divided into units (hereinafter referred to as "instruction blocks" or simply "blocks") that have no branches other than exits.

The processing flow of the instruction block dividing means 2 is as shown in FIG. The divided instruction programs are expressed by pointing the block table shown in FIG. 4 to the first instruction of the block in the instruction expansion memory 7.

The instruction block division means 2 analyzes the instruction code (step 11), determines whether the target instruction is a branch instruction (step 12), and performs block division processing only when the instruction is a branch instruction. That is, if the target instruction is a branch instruction, first the block table pointing to the next instruction of the branch instruction is searched (step 13), and if it already exists, nothing is done. If there is no block table pointing to the next instruction after the branch instruction, create one (step 14).
, sets the instruction next to the branch instruction as the first instruction of the next block (or the relative offset within the expanded instruction on the instruction expansion memory 7, and the same goes for the pointer to subsequent instructions), and The table is checked with the preceding and succeeding block tables so that the table is checked in the order of the addresses of the instructions (step 15). Then, it is further determined whether the branch instruction is a conditional branch instruction or not (step 16).
, In the case of a conditional branch instruction, even if a new block table is not created, the current block table is chained with the control order preceding block pointer and the control order succeeding block pointer (step 17).
. Also, from the branch relative offset of the branch instruction, it is determined whether it is a downward branch or not (Step 18), and if it is a downward branch, a block table is unconditionally created (Step 20).
If it is an upward branch, it is determined whether there is a block table that points to the branch destination instruction (step 19), and only if there is no block table, a block table is created (step 20), and the address of the instruction is determined in the same way as above. Step 2 Chaining with the front and rear block tables in order
1), chaining is performed with the current block table in the same control order as described above, even if no new block table is created (step 22). Now, the block is divided immediately after the branch instruction and at the branch destination label position.If the instruction input means 1 and the instruction block division means 2 are repeated and the above processing is performed for all instructions, the block table will be divided. A control flow is created.

This collection of block tables is called a block table group 8.

Next, by the inter-block register flow analysis means 3,
Determine the dependencies of registers between blocks (the relationship of whether or not the value is inherited across blocks; while the value on the register is inherited, the register is said to be "alive"), Find the registers that are alive at the entrance of the block and the registers that are alive at the exit of the block.

For each block, the included instruction string is analyzed focusing on each register, and if the first register access instruction that appears in the block is a register reference instruction, that register is alive at the entrance of the block. The block table is traced from the block table starting point pointer according to the address order chain, and as described above, registers that are active at the entrance of all blocks are identified and set in each block table. Next, the block table is traversed in reverse order of control flow to determine which registers are alive at the exit of the block and set in each block table. Registers that are alive at the exit of a block are registers that are alive at the exit of the block that immediately follows on a control transition and are not defined in that block, and registers that are alive at the entrance of the block that immediately follows on a control transition. is the union of

Once the information on the registers alive at the entrance/exit of the block is obtained, the equivalence relationship analysis means 4 analyzes the equivalence relationship between the memory and the register (the equivalence relationship here refers to the It is a relationship in which the contents of memory and the contents of a register have the same value at a certain point during instruction execution, as shown above, and is generally created by load instructions from memory to registers and store instructions from registers to memory. ).

The processing flow of the equivalence relation analysis means 4 is as shown in FIG. The equivalence relation analysis means 4 uses an equivalence relation table 9 as shown in FIG.
The following processing is performed for each instruction using the instruction code.

First, it is determined whether it is a load instruction or not (step 31). If it is a load instruction, then the equivalence relation table 9 has already been established for the memory at the load destination (that is, the memory of the same address and the same length has an equivalence relation table 9). If it is set, it is determined whether or not it is attached (step 32), and if an equivalence relation is attached, an attempt is made to reallocate the register as described below (step 33).

If the equivalence relationship does not exist for the memory to which the load is to be loaded (that is, if there is no equivalence relationship table 9 for the memory with the same address and the same length), a new equivalence relationship table 9 will be created with the address of the memory to which the load is to be performed. length (determined by instruction),
and sets the load destination register (step 37).

In step 31, if it is not a load instruction, it is further determined whether or not it is a store instruction (step 34); if it is a store instruction, it is determined whether there is a register with an equivalency relationship with any of the target memories (step 34); 35) If there is an equivalence relation even for a part of the storage destination memory (that is, even for a part of the memory indicated by the address and length, the equivalence relation table 9 is If it is set), delete that information from the equivalence relation table 9 (Step 36), and newly set the store destination memory address and length (determined by the instruction) in the equivalence relation table 9, and the store source register. (Step 37).

In addition, if there is no equivalence relation even in part of the storage destination memory (that is, if there is no equivalence relation table 9 for any part of the memory indicated by the address and length), The address and length of the store destination instruction (determined by the instruction) and the store source register are newly set in the equivalence relation table 9 (step 37).

Furthermore, if it is neither a load instruction nor a store instruction in steps 31 and 34, the process ends without doing anything.

Only when it becomes possible to reallocate registers through the above analysis process (when a load instruction is generated for a memory with an equivalence relationship), register reallocation is performed by inheriting the equivalence relationship by means 5. Reallocate registers to remove unnecessary load instructions.

Here, the instruction that set the equivalence relationship is 81, the target memory with the equivalence relationship is M1, the load instruction from M that attempts to delete the target register is Rz, and the load destination register of L is Rz.
2. Let α be the interval from the beginning of the block to the immediately preceding instruction.
The interval from the instruction immediately after L to the end of the block is β, α
The interval after the last definition instruction of the A register in the interval is expressed as γ(
A), in the interval before the A register reference instruction in the β interval,
Let δ(A) be the maximum interval that does not include the A register definition instruction (see FIG. 6).

However, if there is no A register definition instruction within the α interval, γ(A) = α + ε, and if there is no A register definition instruction within the β interval and the A register is alive at the exit of the block, δ(A ) = β + ε, and if there is an A register definition instruction within the β interval, then up to the first A definition instruction, and if there is no A register reference instruction within the interval up to the end of the block, then δ(A) = 0. shall be.

First, L is deleted by replacing the R2 registers after L with registers R1 having an equivalence relationship. If the following conditions are all satisfied, R in the δ(R2) interval
Change the register of the 2-register reference instruction to R1 and delete L.

(1) The life of the R2 register defined by L ends within the block.

[δ(R2)≦β] (2) While the R2 register defined by L is alive, R
+ There is no register definition instruction.

[δ(R2) R, register definition instruction] If it is impossible to replace the R2 register → R1 register, L is deleted by replacing register R1 with an equivalency relationship before and after L with register R2.

If all of the following conditions are met, γ(Ro)+6(R
8) Change the register of the R1 register definition/reference instruction in the interval to R2 and delete L.

(1) The life of the R1 register with an equivalence relationship set in S begins and ends within the block.

[γ (R1)≦α & δ (R,)≦β] (2
) There is no definition/reference instruction for the R2 register except while the equivalence relationship is set in S and the register R is alive and the R2 register defined by is alive.

[γ (R1) + δ (R,) - δ (R2) R2 register definition/reference instruction R1 register → R2 register replacement is also impossible,
No register reallocation is performed.

After tracing the block table from the block table starting point pointer in accordance with the address order chain and optimizing all blocks by the equivalence relation analysis means 4 and the register reallocation means 5, the instruction output means 6 stores the instructions. A list of instructions whose registers have been reallocated is output to the instruction storage medium 10 that has been previously allocated.

In this way, for an instruction block, which is the largest unit of linear control transfer, we investigate the register dependencies of included instructions and the equivalence relationship between memory number registers, and reallocate registers to eliminate unnecessary registers. By removing unnecessary load instructions, the object size can be reduced and execution speed can be improved.

Furthermore, by performing this on machine language instructions, there is no need to prepare compiler-specific register allocation processing for each compiler, and it can also be applied to objects output by the compiler.

〔Effect of the invention〕

As explained above, the present invention investigates the register dependencies of included instructions and the equivalence relationship between memory and registers for an instruction block, which is the largest unit in which control is transferred linearly. By reallocating and deleting unnecessary load instructions, the object size can be reduced and the execution speed can be improved.

Moreover, by performing this on machine language instructions, there is an effect that there is no need to prepare a register allocation process specific to Funvira for each compiler.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a flowchart showing the processing flow of the instruction block dividing means shown in FIG. 1, FIG. 4 is a flowchart showing the processing flow of the equivalence relation analysis means shown in FIG. , FIG. 5 is a diagram showing details of the equivalence relation table shown in FIG. 1, and FIG. 6 is a diagram showing a related image of instructions in the block during processing of the register reallocation shown in FIG. 1. It is. DESCRIPTION OF SYMBOLS 1... Instruction input means, 2... Instruction block division means, 3... Inter-block register flow analysis means, 4... Equivalence relation analysis means, 5・・・
...Register reallocation is a means, 6...Instruction output means, 7...Year instruction expansion memo 1c8...Block table group, 9...Equivalent Relationship table, 10.
...Instruction storage medium. Agent: Susumu Uchihara, Patent Attorney

Claims (1)

[Scope of Claims] 1. In an architectural register reallocation method that has load/store instructions between memory and registers but does not have indirect branch instructions, (A) A sequence of instructions from a medium storing instructions; (B) Analyzes the inputted instruction, creates an instruction block by dividing the instruction sequence immediately after the branch instruction and at the branch destination label position, and divides the instruction block at the same time. (C) definition of registers between the divided instruction blocks;
inter-block register flow analysis means for investigating reference dependencies and finding live registers at the entry/exit of the instruction block; (D) for the instructions in the divided instruction block, the an equivalence relationship analysis means for analyzing the state of an equivalence relationship in which the content of the memory and the content of the register have the same value; (E) if there is an unnecessary load instruction from the memory with the equivalence relationship; (F) register reallocation means for reallocating the registers and deleting unnecessary load instructions so as to avoid unnecessary load instructions; A register reallocation method comprising: instruction output means for outputting a sequence of register reallocated instructions to the medium where the registers have been reallocated. 2. In an architectural register reallocation method that has load/store instructions between memory and registers but does not have indirect branch instructions, (A) A sequence of instructions is input from the medium storing the instructions and transferred to memory. (B) Analyzing the inputted instructions, dividing the sequence of instructions immediately after the branch instruction and at the branch destination label position to create instruction blocks, and simultaneously developing control between the divided instruction blocks. (C) Defining registers between the divided instruction blocks.
(D) examining reference dependencies and determining live registers at the entry/exit of the instruction block; (E) If there is an unnecessary load instruction from the memory with the equivalence relationship, rewriting the register to avoid conflicts; performing allocation and deleting unnecessary load instructions; (F) After performing equivalence relationship analysis and register reallocation for all the divided instruction blocks, register reallocation has been completed on the medium in which the instructions were stored; A register reallocation method characterized by executing the steps of outputting a sequence of instructions.