JPH04209394A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the speed for an access at the time of reading operation by amplifying the reading data of a memory cell transmitted to the input/output lines pair from the bit lines pair through plural transistors. CONSTITUTION:The reading data of memory cell transmitted to the input/output lines pair I/Oa, I/Ob from the bit lines pair BLa, BLb through the transistors Q10, Q11 are amplified by a potential difference amplifying circuit 7. Then, the high level voltages of adequately different values are supplied to the sources of transistors Q31, Q32 in the circuit 7. When the potential difference is generated in the lines pair I/Oa, I/Ob at this stage, the transistor Q31 or Q32 is complementarily made ON or OFF in correspondence thereto, and a prescribed minute potential difference is immediately amplified by the circuit 7. Then, the lines pair BLa, BLb and lines pair I/Oa, I/Ob can be connected without standby. The timing speed for connection is thereby increased and the high speed access can be performed.

Description

[Detailed description of the invention]

[00011

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of high-speed reading. [0002] [0002] In recent years, for example, dynamic type MO8R
For highly integrated semiconductor memory devices such as AM (random access memory using MOS transistors),
In addition to higher integration to increase the storage capacity, there is a desire to speed up the read operation by significantly shortening the access time (time required to read data). [0003] FIG. 4 is a diagram schematically showing the overall configuration of a conventionally used semiconductor memory device. [00041] In FIG. 4, the memory cell array 101 includes a plurality of memory cells arranged in rows and columns to have a folded bit line configuration. Address buffer 1O2
receives an externally applied address signal ADD and generates an internal row address signal and an internal column address signal. Row decoder 103 responds to an internal row address signal from address buffer 1O2 to
Select 1 or 61 rows (1 word line). Column decoder 104 selects one column (one bit line pair) from memory cell array 101 in response to an internal column address signal from address buffer 1O2. (Sense amplifier +
I10) Block 105 amplifies the signal potential difference on the bit line pair and connects the selected bit line pair to the data input/output line in response to the column decode signal from column decoder 104. The write buffer 106 receives externally applied write data D1, converts it into a mutually complementary data set (DIN, DI11), and transmits it to the I10 portion of the block 105. Note that the data DIN bar is the inverted data of the data DIN. The read buffer 107 receives data from the I10 portion of the block 105 and outputs it to the outside as an output signal D OU r . The clock generator 108 generates a row address strobe signal RAS bar (RAS bar corresponds to a horizontal line drawn above RAS in the drawing) and a column for giving the start of a memory cycle, the timing of taking in an address signal, etc. An address strobe signal CAS bar (in the drawing, CAS bar corresponds to a horizontal line drawn on CASO), etc. is generated. [0005] The row address strobe signal RAS from the clock generator 108 is applied to the address buffer 1.
O2, row decoder 103, etc., and column address strobe signal CAS bar is applied to address buffer 10
2, is given to the column decoder 104, etc. [00061 As shown in FIG. 5, the row address strobe signal RAS provides the timing for taking in the row address signal in the address buffer 1O2, and the column address strobe signal CAS provides the timing for taking in the row address signal in the address buffer 1O2.
This provides the timing for taking in the column address signal in step 2. In this configuration, row addresses and column addresses are given to address buffer 1O2 in chronological order. Also,
The timing of decoding the address signal in the row decoder 103 and the column decoder 104 is as follows.
It is given by a row address strobe signal RAS and a column address strobe signal CAS. [00071] FIG. 6 is a diagram showing the configuration of a main part of the memory cell array shown in FIG. 4, and is a diagram specifically showing an example of the configuration of the block 150 shown by the dotted line. [0008] In FIG. 6, a pair of bit lines BLa and BLb forming a folded bit line is representatively shown. The bit lines BLa and BLb form a pair and constitute a folded bit line pair. That is, mutually complementary signals appear on the bit lines BLa and BLb. Bit line BLa
, BLb are provided in a direction perpendicular to the word lines. However, in FIG. 6, only one word line WL is representatively shown. Memory cells are provided at the intersections of word lines and bit lines. Therefore, memory cells are arranged in rows and columns. In FIG. 6, only one memory cell 1 provided at the intersection of bit line BLa and word line WL is representatively shown. The memory cell 1 has a one-transistor/one-capacitor configuration, and includes a memory capacitor Co for storing information and an N-channel NIS (metal-insulator-semiconductor) transistor QO. [00091 Flip-flop type sense amplifiers 2 and 3 are provided to differentially amplify the signal potential difference on the bit line pair BLa and BLb. Sense amplifier 2 is composed of N-channel NIS transistors Ql and Q2. The sense amplifier 2 is activated in response to a signal from the sense amplifier activation means 4, and discharges the bit line potential on the low potential side to the ground potential. The sense amplifier activation means 4 is turned on in response to the sense amplifier activation signal SO, and the node N1 is turned on.
N-channel NIS transistor Q connecting to ground potential
Consists of 5. Sense amplifier 3 is P channel NI
S transistor Q3. Consists of Q4. The sense amplifier 3 is activated in response to a signal from the sense amplifier activation means 5, and changes the bit line potential on the high potential side to the power supply potential Vc.
Charge C. The sense amplifier activation means 5 receives a sense amplifier activation signal SO bar (SO bar is SO in the drawing).
(corresponding to the symbol with a horizontal line drawn above it), the transistor Q6 is turned on in response to the symbol , and connects the node N2 to the power supply potential Vcc. [00101 The equalize/precharge means 6 precharges each bit line BLa, BLb to a predetermined precharge potential VBL before and after the start and end of a memory cycle (that is, during standby), and sets each bit line potential to a predetermined precharge potential VBL. Equalize. Usually, precharge potential VBL is generated by an internal voltage generation circuit and is set to a predetermined potential (for example, half of power supply voltage Vcc, ie, a potential of Vcc/2). [00111 Furthermore, between each bit line pair BLa, BLb and data input/output line pair l10a, l10b, there is an N-channel NIS which turns on in response to a column decode signal Y from a column decoder (see FIG. 4). transistor Q
10 and Qll are connected respectively. The data input/output line pair l10a, l10b is normally connected to an N-channel NIS transistor Q that is turned on in response to a clock signal CLK.
22 and Q23 to precharge to a predetermined potential v-nt. Data input/output line pair l10a and l10b exchange data via an input/output buffer. [00121 FIG. 7 is a signal waveform diagram showing the read operation of the conventional semiconductor memory device shown in FIGS. 4 and 6. In FIG. 7, the same symbols as those shown in FIG. 6 indicate potential changes in corresponding parts. The read operation of the conventional semiconductor memory device shown in FIG. 6 will be described below with reference to FIG. [0013] Before time T1, equalize signal E
Q is at high level, equalizing transistor Q7
, precharge transistor Q8. Q9 is all ON
state, and the bit lines BLa and BLb are at a predetermined potential V!
It is precharged to LL. [0014] When the equalize signal EQ falls from high level to low level at time T1, transistor Q
7.Q8. Q9 are all turned off, and bit line B
La and BLb are in an electrically floating state. This completes the precharge/equalize operation. [0015] At time T2, when one word line WL is selected in response to a row decode signal from a row decoder, the potential of the word line WL shifts from low level to high level. As a result, the transistor QO of the memory cell 1 connected to the word line WL is turned on, and the memory capacitor Co is connected to the bit lines BLa and BLb. As a result, a potential change occurs on the bit lines BLa and BLb according to the information held by the memory cell 1. Now, when the memory cell stores information "1°", as shown by the solid line in FIG. Holds charge potential. [0016] When the read signal potential on the bit line pair BLa and BLb is determined, the sense amplifier activation signals so and so begin to rise and fall, respectively, at time T3. This causes transistor Q5. Q6 becomes ON state,
The node N1 is charged and discharged to the ground potential, and the node N2 to the power supply potential Vcc. As a result, both flip-flop type sense amplifiers 2 and 3 are activated, and the bit line BL
Among the bit lines a and BLb, the potential of the bit line BLa on the high potential side is charged to the power supply potential Vcc via the sense amplifier 3, and the potential of the bit line BLb on the low potential side is discharged to the ground potential via the sense amplifier 2. . That is, bit line pair BL
a, the minute signal potential difference occurring on BLb is amplified. [0017] After the amplification operations of the sense amplifiers 2 and 3, at time T4, when the column decode signal Y from the column decoder becomes high level, the transistors QIO and Q1
1 is turned on, and the potential on the bit line pair BLa, BLb is transmitted onto the data input/output line pair l10a, l10b. The potential transmitted onto the data input/output line pair l10a, l10b is amplified by an amplifying means such as a preamplifier (not shown), and then transferred to a data output buffer and an external output terminal (
(not shown) to the outside. [0018] When the transmission of data to the external output terminal is completed, the potential of the word line WL decreases from high level to low level at time T5, and the level of column decode signal Y also decreases from high level to low level. As a result, the potential on the data input/output line pair l10a, l10b returns to the precharge potential. [00191] Next, at time T6, sense amplifier activation signals so and so-bar transition to low level and high level, respectively, and both sense amplifiers 2 and 3 are rendered inactive. At this time, the equalize signal EQ also becomes high level, the precharge/equalize means 6 is activated, and the bit line pair BLa, BLb is set to a predetermined potential V.
81 and each bit line pair BLa, B
The potential of Lb is equalized. The above operation is an outline of the operation when reading data. [00201 On the other hand, when writing data, the timing of the signal waveform is similar to that shown in FIG. It becomes a memory cell. That is, the write data provided externally by a write buffer (not shown) is in a complementary form (for example, D1■, DIN bar).
The data is transmitted onto the data input/output line pair l10a and l10b. After passing through the sequence of operations from time T1 to T3,
When the column decode signal Y changes from low level to high level at time T4, transistors QIO and Qll turn on, and data input/output line pair l10a and l10b
The upper signal potential will be transmitted to the selected memory cell. Writing is performed in this manner. [00211 At this time, sense amplifiers 2 and 3 also operate at time T3.
, and amplifies the signal potential difference appearing on bit lines BLa and BLb when the potential of word line WL shifts to high level. However, since the write data is externally transmitted onto the data input/output line pair l10a and l10b by the write buffer, even if the signal level amplified by the sense amplifiers 2 and 3 and the signal potential level of the write data are Even if it is the other way around, a signal potential will appear on the bit line pair BLa, BLb in accordance with the write data. As a result, writing of write data into the selected memory cell is performed via the transistor QO which is in the ON state. [0022]

As described above, in the configuration of a conventional semiconductor memory device, when reading data, the bit line pair BLa, BLb and the data input/output line pair l
10a and l10b are connected via transistors QIO and Qll. In order to read data stored in memory cells at high speed, it is preferable to connect the bit line pair and the data input/output line pair as quickly as possible. [0023] In FIG. 7, for example, from the rise time T2 of the potential of the word line WL, the sense amplifier 2
．． If the bit line pair and the data input/output line pair are connected between the sense start time T3 when the signal 3 is activated, the load capacitance of the data input/output line is added to the bit line, so The read signal level decreases, making it impossible for the sense amplifier to perform a reliable sensing operation, and depending on the case, there is a possibility that a malfunction may occur. Therefore, the bit line pair and the data input/output line pair must be connected after the sense amplifiers 2 and 3 are activated and the signal potentials on the bit line pair BLa and BLb are determined. [0024] Therefore, in the conventional semiconductor memory device, there is a limit in speeding up the read operation, and there is a problem in that it is difficult to further shorten the access time. [0025] Therefore, an object of the present invention is to provide a semiconductor memory device in which the access time for a read operation is shorter than that of conventional semiconductor memory devices. [0026]

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a plurality of word lines, a plurality of bit line pairs arranged to intersect with the word lines, and each word line and bit line pair. A plurality of memory cells arranged at intersections, a word line selection means for selecting one of the word lines, a bit line pair selection means for selecting one set of bit line pairs, and a plurality of memory cells for each bit line pair. a plurality of bit line pair potential difference amplifying means for amplifying the potential difference between the corresponding bit line pairs; a data input/output line pair; and a bit line provided between each bit line pair and the data input/output line pair; a plurality of gate means for coupling the selected bit line and the data input/output line pair in response to the output of the pair selection means; and gate means provided on the data input/output line pair to amplify the potential difference between the data input/output line pair. and data input/output line-to-potential difference amplification means. [0027]

In the present invention, the data input/output line pair potential difference amplifying means amplifies the potential difference between the data input/output line pairs. Therefore, even if the timing of coupling the selected bit line pair and the data input/output line pair is advanced during reading, if there is a slight potential difference between the bit line pair, that is, read data, the input/output line pair potential difference amplifying means It is amplified and accurate reading is performed. Therefore, high-speed access during reading is possible. [0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing the configuration of the main parts of a semiconductor memory device according to an embodiment of the present invention, and corresponds to FIG. 6 of the conventional example. Note that the overall configuration of a semiconductor memory device according to an embodiment of the present invention is the same as that of the conventional example shown in FIG. 4, so its illustration is omitted. [0029] In FIG. 1, data input/output line pair l10a
, l10b are provided with a flip-flop type potential difference amplification circuit 7. This potential difference amplification circuit 7 includes transistors Q31. Including Q32. Transistor Q31゜Q
A high level voltage V-ML+ΔV is applied to each of the 32 sources. The gate of transistor Q31 is connected to the drain of transistor Q32. The gate of transistor Q32 is connected to the drain of transistor Q31. A data input/output line l10a is connected to the drain of the transistor Q31. A data input/output l10b is connected to the drain of the transistor Q32. The rest of the structure of the embodiment shown in FIG. 1 is the same as that of the conventional semiconductor memory device shown in FIG. 6, and corresponding parts are given the same reference numerals and explanations thereof will be omitted. [00303 Next, the operation of the potential difference amplification circuit 7 shown in FIG. 1 will be explained. Transistor Q31. As described above, the voltage V-BL+ΔV is applied to each source of Q32. Here, ΔV is an appropriate value, for example, transistor Q3
1, is selected as the threshold voltage IVTF+ of Q32. Therefore, if a slight potential difference occurs between the data input/output line pairs l10a and l10b, each data input/output line pair l10a and l1
Depending on the potential of transistor Q31. Q32 becomes ON or OFF in a complementary manner. For example, when the potential of data input/output line I/○a is higher than the potential of data input/output line l10b, transistor Q31 is turned on and transistor Q32 is turned off. As a result, the potential of the data input/output line l10a becomes the voltage V-BL+Δ
It can be increased to VIVTF+. Conversely, data input/output line l
When the potential of the data input/output line l10a is higher than the potential of the data input/output line l10a, the transistor Q31 is turned off and the transistor Q32 is turned on. As a result, the potential of data input/output line l10b (7) becomes voltage V-at+Δv-I
It can be increased to VTF l. In this way, the potential difference amplifying circuit 7 immediately amplifies the minute potential difference that occurs between the data input/output line pair ◯/◯a, l10b. [00311 FIG. 2 is a signal waveform diagram in the read operation of the embodiment shown in FIG. The advantages of the embodiment shown in FIG. 1 will be explained below with reference to FIG. 2. [0032] As can be seen by comparing FIG. 2 with FIG. 7, FIG.
The read operation of the embodiment shown in FIG. 6 is almost the same as that of the conventional semiconductor memory device shown in FIG. However, in the embodiment shown in FIG. 1, the timing T4 for connecting the selected bit line pair BLa, BLb and the data input/output line pair l10a, l10b is advanced compared to the conventional semiconductor memory device shown in FIG. ing. This is because even if the potential difference transmitted from the bit line pair BLa, BLb to the data input/output line pair l10a, l10b is minute, the minute potential difference is accurately amplified by the potential difference amplification circuit 7. That is, until the potential difference between the bit line pair BLa, BLb and the data input/output line pair l10a is amplified by the sense amplifier 2.3 and determined to a predetermined value. There is no need to wait for connection to l10b. therefore,
As shown in FIG. 2, the bit line pair BLa, BLb and the data input/output line pair l10a, l10b can be connected immediately after time T3 when sense amplifiers 2 and 3 are activated. More specifically, in the embodiment shown in FIG.
It is also possible to connect it with l10b. [0033] As described above, in the embodiment shown in FIG. 1, the connection timing between the selected bit line pair and the data input/output line pair can be made faster than in the conventional semiconductor memory device, so that the read operation can be performed faster. This makes it possible to speed up access at times. [00341 In the embodiment shown in FIG.
As P-channel type MOS transistor Q31. Q3
Although the potential difference amplifying circuit 7 is configured as shown in FIG. For example, as shown in FIG. 3, two P-channel MOS transistors Q31°Q32 and two N-channel MOS transistors Q3
3 and Q34 may constitute a potential difference amplification circuit. In FIG. 3, transistor Q31. A voltage VIL+Δ■ is applied to each source of Q32. The gate of transistor Q31 is connected to the train of transistor Q32 and the gate of transistor Q33. The gate of transistor Q32 is connected to the drain of transistor Q31 and the gate of transistor Q34. The train of transistor Q31 is connected to the drain of transistor Q33 and the data input/output line l1.
Connected to 0a. The drain of transistor Q32 is connected to the drain of transistor Q34 and data input/output line l10b. Transistor Q33. Q
Each of the 34 sources is grounded. [0035] Next, the operation of the potential difference amplifier circuit of another embodiment shown in FIG. 3 will be described. First, data input/output line l10a
When the potential of transistor Q31. is higher than the potential of data input/output line l10b, transistor Q31. Q34 is turned on, and transistors Q32. Q33 becomes OFF state. As a result, the potential of the data input/output line l10a becomes the voltage ■'I+ΔV
Vypl, and the potential of the data input/output line l10b is lowered to the ground potential. On the contrary, data input/output line■1
0b is higher than the potential of data input/output line l10a, transistor Q32. Q33 is turned on, and transistors Q31. Q34 becomes OFF state. As a result, the potential of the data input/output line l10b becomes the voltage V-a
The potential of the data input/output line l10a is lowered to the ground potential. In this way, the potential difference amplification circuit shown in FIG.
Since the potential of one of the terminals 10a and 10b is increased and the potential of the other is decreased, compared to the potential difference amplifier circuit 7 shown in FIG. Input/output line pair l10a, l10b
It is possible to amplify the potential difference to a greater extent. [0036]

As described above, according to the present invention, since the data input/output line pair is provided with the data input/output line pair potential difference amplifying means, the data input/output line pair is provided with the data input/output line pair potential difference amplifying means. Since the timing for connecting the bit line pair and the data input/output line pair can be made faster than in conventional semiconductor memory devices, high-speed access is possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of main parts of an embodiment of the present invention.

FIG. 2 is a signal waveform diagram during reading in the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram showing another configuration example of a potential difference amplification circuit for amplifying the potential difference between a pair of data input/output lines.

FIG. 4 is a block diagram showing the overall configuration of a conventional semiconductor memory device.

FIG. 5 is a timing chart showing address capture timing in the conventional semiconductor memory device shown in FIG. 4;

FIG. 6 is a circuit diagram showing the configuration of main parts of the conventional semiconductor memory device shown in FIG. 4;

7 is a signal waveform diagram during a read operation of the conventional semiconductor memory device shown in FIGS. 4 and 6; FIG.

[Explanation of symbols]

1 Memory cell 2.3 Sense amplifier WL Word lines BLa, BLb Bit line pair ■/○a, l10b Data input/output line pair QIO,
Qll Transistor 7 for connection between bit line pair and data input/output line pair Potential difference amplifier circuit for data input/output line pair 101 Memory cell array 1O2 address buffer 103 Row decoder 104 Column decoder 105 (sense amplifier +I 10) block

[Figure 5
]

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of bit line pairs arranged intersecting the word lines, and a plurality of memory cells arranged at each intersection of the word lines and the bit line pairs. , a word line selection means for selecting one of the word lines, a bit line pair selection means for selecting one set of the bit line pairs, and a corresponding bit provided for each bit line pair. a plurality of bit line pair potential difference amplifying means for amplifying the potential difference between the line pairs; a data input/output line pair;
provided between each said bit line pair and said data input/output line pair, for coupling a selected bit line pair and said data input/output line pair in response to an output of said bit line pair selection means; a plurality of gate means, and a data input/output line pair potential difference amplifying means provided on the data input/output line pair for amplifying the potential difference of the data input/output line pair, the data input/output line pair potential difference amplifying means In the semiconductor memory device, the means amplifies read data of the memory cell transmitted from the bit line pair via the gate means.