JPH04208880A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make quality judgment simple by providing a plurality of test circuits to supply test data and control signals to a macro cell, and a quality judging circuit to judge the quality from test signals to be output from the plurality of test circuits. CONSTITUTION:Outputs of several BIST circuits 12a, 13a, 17a are connected to a comparator 18 as a quality judging circuit and an address generating element 23 outputs an address stepped by a test enable signal 21. A write data generating element 24 supplies test writing data to RAMs 12, 13, 17 and a write pulse generating element 25 supplies a timing signal to a test writing pulse generating element of the RAMs 12, 13, 17. Data output from the RAMs 12, 13, 17 are supplied to a first output comparator 26 and transmitted to the comparator 18. The comparator 18 compares signals to receive from the BIST circuits 12a, 13a, 17a, judges those qualities, and outputs those results to a pin 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing a semiconductor device, and particularly to a method for testing a gate array type semiconductor device having a plurality of BIST-equipped RAM macro cells.

[Prior Art] Conventionally, as a type of gate array including macro cells such as RAM, there is a RAM having a macro pattern of a specific RAM.
An SOG type gate array has been known that constitutes a RAM macro using a combination of a gate array with a gate array and a gate array and an isher.

In this Shino gate array, RAM macrocell testing is usually performed by sharing data input, data output, write signal input, address input, etc. with other general input, output signal pins, and external terminals. In other words, in the test mode, data etc. are input directly from the outside, and the RAM
I have tested it by running it.

In addition, tests that generate the signals necessary for the test internally (
Even when using RAM with circuits (BIST), each closed test was performed within each individual circuit.

[Problems to be Solved by the Invention] In recent years, SOG gate array configurations have been increasing, and SOG gate arrays that have multiple RAMs with different configurations have also appeared. However, when a plurality of such RAMs are provided, a problem arises in that the number of bins required for the test increases because the test is executed individually.

Even if the test input is a common input and the output signal and the test signal are shared, there is a drawback that the branch circuit provided in association with the shared bin deteriorates the performance.

Furthermore, even if a BIST circuit is used, it is difficult to share test inputs if the RAM configurations are different.

[Means for Solving the Problems] The gist of the present invention is that in a semiconductor device having a plurality of macro cells functioning as a memory circuit, a test enable signal ζ provided in association with each of the plurality of macro cells and supplied from the outside. A plurality of test circuits that supply test data and control signals to the macrocell in response to a test clock that is activated from the outside and is supplied from the outside, and output a test signal representing the function of the memory circuit of each macrocell, and a plurality of test circuits. The present invention includes a pass/fail judgment circuit that judges pass/fail from the test signal output from the test signal and outputs the result to the outside.

[Operation of the Invention] According to the configuration of the present invention, the test circuit manually inputs the test clock signal and the test enable signal, outputs a test signal representing an expected value independent of the configuration of the memory circuit of the macrocell, and the pass/fail judgment circuit performs the test. The quality of the semiconductor device is determined based on the signal.

[Embodiment] FIG. 1 is a block diagram showing a first embodiment, in which a Kate array including a plurality of RAMs 12, 13, and 17 is integrated on a semiconductor chip 11. Each RAM 12.13 has a BIST circuit 12a, 13a, which controls only its operation and outputs the RAM output by a multiplexer.
17a is attached thereto. The output of each BIST circuit 12a, 13a, 17a is connected to a comparator 18 as a pass/fail judgment circuit, and as shown in FIG.
2 and outputs an address that is incremented by the test clock signal 21. The timing generator 27 is also activated by the test enable signal and generates a timing signal for each address, and in synchronization with this timing signal, the write data generator 24 writes test write data to the RAMs 12, 13, and 17 with write pulses. The generating section 25 is R
A timing signal is supplied to the test write pulse generator of 2°13.17 AM]. Data output from the RAMs 12, 13, and 17 is supplied to an output primary comparator 26 and sent to a comparator 18. Comparator 18 is BIST circuit 1
The signals sent from 2a, 13a, and 17a are compared to determine whether they are good or bad, and the result is output to pin 16.

FIG. 3 shows an embodiment of the present invention, and shows an example of a comparator 36 as a pass/fail judgment circuit 3A including flip-flops 35a to 35c for speed measurement in addition to the comparison circuit. In the figure, 31 is a semiconductor chip, 37 is a test clock, and 3
8 is a test enable signal, 32 to 34 are RAM, 32
A to 34a have one BIs circuit. Circuit operation is the first
Since this is similar to the embodiment, the description will be omitted.

[Effects of the Invention] As explained above, the present invention can simplify pass/fail judgment by using a test circuit and a pass/fail judgment circuit that output test output without depending on the word pit configuration, and also has the advantage of reducing the number of test terminals. have an effect. Furthermore, this has the effect of reducing the number of man-hours required for generating test program test patterns.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment, FIG. 2 is a block diagram showing a BIST circuit, and FIG. 3 is a block diagram of the second embodiment. 11... Semiconductor chip, 12.17.13... RAM macro, 14...
...Test clock input signal, 12a, 13a,
17a... ・8181 circuit, 15...
・Test enable signal, 16...Test output, 18...Comparator quality judgment comparator, 21...
...Test clock signal, 22...
・Test enable signal, 23...Address generation section, 24...Write data generation section,
25......Light pulse generation section, 26...
...Output primary comparator, 27...Timing generator, 31...Semiconductor chip, 32.33,34k...BIST (tRAM macro, 3
5.35', 35"...Flip-flop, 36
......Comparator, 37...Test clock signal, 38...
...Test enable signal, 39...Test output signal, 3A...Pass/fail judgment circuit with flip-flop. Patent applicant: NEC Corporation

Claims (1)

[Scope of Claims] In a semiconductor device having a plurality of macro cells functioning as a memory circuit, a test device provided along with each of the plurality of macro cells, activated by a test enable signal supplied from the outside, and supplied from the outside. Multiple test circuits supply test data and control signals to the macrocell in response to a clock, and output test signals representing the functions of the memory circuits of each macrocell, and pass/fail is determined from the test signals output from the multiple test circuits. and a pass/fail determination circuit that outputs the result to the outside.