JPH04208878A - Mixed digital and analog circuit and its testing device - Google Patents

Abstract

PURPOSE:To supply clock signals possible to set up independently a frequency into plural several functional blocks and test efficiently by providing a plurality of clock generating measures possible to set up independently the frequency. CONSTITUTION:An A/D converter 101 and a digital circuit 102 are made an AC test, and a D/A converter 103 a DC test. In these cases, the A/D converter 101 and the digital circuit 102 are operated with the high speed AC test and the D/A converter 103 with the low speed DC test. Thus, several blocks within an LSI can be tested, dividing those into the AC test and the DC test because a test signal f1 and clock signals f2, f3 can freely be set up by frequency transformers 203 and 205. It also is possible that only the A/D converter 101 is operated with the high speed AC test, and the digital circuit 102 and D/A converter 103 are operated with the low speed DC test.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Fields] The present invention is applicable to various digital/analog mixed LSIs used in high-resolution video displays, OA equipment, etc.
The present invention relates to circuit system configurations and test equipment thereof, and in particular to digital and analog mixed circuits including means necessary for testing dynamic characteristics, LSIs, and test equipment thereof.

[Prior art] The conventional digital and analog mixed LSI mentioned above is, for example, I
E E E (TIIE IN5TITUTE OF
ELECTRICALAND ELECTONIC5E
NGINEER3, INC.)'s 1989 IS
S CC (International 5 solid
5tate C1rcuits Conference
Digest of Technical
Papers) pages 26.2-263, and as shown in FIG. The D/A converter 103 converts it into an analog signal and outputs it. Further, a clock signal is inputted from the outside, and each of the above-mentioned conversions and signal processing is operated using this clock signal as a time base.

As described in Japanese Unexamined Patent Publication No. 76462/1983, the above-mentioned test equipment for digital and analog mixed LSIs is equipped with clock pulse generators having various cycles, and the clock pulse signals and clock pulse signals are A test signal is generated using the test pattern information, and the test signal is input to an input terminal of the LSI according to a command from a sequence control section.

In addition, the test device described in Japanese Patent Application Laid-Open No. 58-100761 has a switching circuit for switching and outputting the test result output for each functional block inside the LSI, and a switching circuit for switching and outputting the test result output for each functional block inside the LSI, and an oscillation terminal of the LSI for each functional block. It is equipped with a switching circuit for supplying a test clock signal and a control signal terminal for controlling these circuits.

Furthermore, in the test method described in Japanese Patent Application Laid-Open No. 61-217778, a logic circuit block that operates with clock signals each having a different period in a logic device is connected to a basic clock generation circuit, the basic clock and an external clock. The present invention includes a selection circuit that switches between the two, and a counting circuit that counts the output of the selection circuit, and the counting circuit generates a clock signal required by each of the logic circuit blocks.

[Problems to be Solved by the Invention] In the above conventional technology, each functional block inside the LSI can be tested using a clock signal supplied from the outside, but each clock signal is generated by dividing a single basic clock frequency. Since each clock frequency was determined by the frequency division described above, there was a problem in that each clock frequency could not be set freely.

As is well known, testing of such LSIs includes DC (low frequency) testing to test for internal element failures and wiring failures, and A (low frequency) testing to test propagation delays, inductive coupling, etc.
C (high frequency) test is performed.

For example, when testing I and SI with the configuration shown in FIG. 8, the A/D converter 101 is
A DC (low frequency) test is performed on the PIO 5, the D/A converter 103, etc.

However, if the frequency of one reference clock is divided by a predetermined frequency dividing circuit to generate the clocks for the DC test and AC test as in the past, each clock frequency cannot be changed arbitrarily, and the test conditions There was a problem that there was little freedom in changing the

Furthermore, there is a problem in that it is difficult to identify defective blocks if each block is subjected to a common AC or DC test.

Furthermore, if the frequency relationship of each tarokku is fixed, there is a problem that, for example, an A/D converter cannot be sufficiently tested. For example, if the number of bits of an A/D converter is 8 bits, its resolution is 256 steps. Therefore, in order to test the accuracy and operation of each step, it is necessary to input analog signals with 256 different amplitude values for the full scale. If the input analog signal has a low frequency, changes in its amplitude are sampled sequentially, so this is not a problem. However, when the frequency of the human input signal becomes high, the number of samplings per cycle of the input decreases, making it difficult to sample the 256 amplitude values.

For example, with a sampling frequency of 15 MHz,
When sampling an MHz analog signal, 1 of the signal
The number of samples between periods is 3, and cannot be increased beyond this. In such a case, it is called the Be 1 ~ method, and one of the sampling frequency and the input signal frequency is set to 3 as described above.
For example, a method of reducing the frequency by about IKHz is used due to an integer relationship such as multiplication. This equivalently reduces I KHz to 15M
The same sampling density is obtained when sampling at I-(z).

However, the beat method described above is difficult to employ when the input signal frequency cannot be changed arbitrarily. That is, when the input signal frequency is specified, it is necessary to change the tarock frequency to generate the beat frequency, but in conventional devices, the relationship between each clock frequency was fixed in relation to the system, so This is because it was not possible to change only a specific clock frequency.

For example, in a mixed digital and analog LSI for video, AD conversion at a video subcarrier frequency of 3.58 MHz may be tested. Since the clock frequencies for DSP and DA converters are determined in relation to their respective operations, the clock frequency for the AD converter should be set to the above-mentioned beat to the above-mentioned video subcarrier frequency while maintaining the division relationship with these frequencies. It is generally almost impossible to set up a relationship that occurs.

An object of the present invention is to provide a digital/analog mixed circuit that can supply an arbitrary clock signal to each functional block in the digital/analog mixed circuit and freely set DC test and AC test conditions for each functional block. and its testing equipment.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a testing device for a mixed digital/analog circuit including a plurality of tarock generation means including a clock generation means whose frequency can be set independently. , each functional block in the digital/analog mixed circuit is operated by these tarock signals.

Further, each of the clock signals is generated by transforming the frequency of each clock signal using a frequency transforming means based on a reference frequency.

Furthermore, the frequency of the reference frequency generating means is set as the base 7 (C) to generate test pattern signals, analog signals, etc. of the digital/analog mixed circuit.

Further, based on the frequency of the reference frequency generating means, the output signal is digitally converted to the test 1 of the digital/analog mixed circuit, and is also stored.

The normal clock signal and the test clock signal will be switched manually for each functional block in the digital/analog mixed circuit.

Furthermore, a separation circuit with a test terminal is provided between each functional block in the digital/analog mixed circuit, and the test terminal outputs the test signal that is output to the separation circuit. Make it input.

Furthermore, the plurality of separation circuits are connected by a signal bus.

Further, an external digital circuit device can be connected to each test terminal of the separation circuit.

[Function] The digital/analog mixed circuit testing device of the present invention configured as described above supplies a tarok signal whose frequency can be set independently to each of the plurality of functional blocks in the digital/analog mixed circuit device. I can do it.

Further, each of the above clock signals is generated by frequency-transforming the reference frequency.

Furthermore, a test pattern signal, an analog test signal, etc. for the digital/analog mixed circuit are generated from the reference frequency or the transformed frequency.

Furthermore, the clock signal of the reference frequency or the modified frequency drives the digital conversion circuit and memory device of the test output signal of the digital/analog mixed circuit.

Further, the digital/analog mixed circuit of the present invention can input a normal clock signal and a test clock signal to each functional block within the circuit by switching between the normal clock signal and the test clock signal.

Furthermore, it is possible to output a test i signal that is output between each of the functional blocks, and to input a test signal.

Furthermore, by connecting the plurality of separated circuits with a signal bus, for example, it is possible to skip an intermediate digital circuit and perform a combination test of A/D converters and D/A converters.

Furthermore, by connecting an external digital circuit device to each test terminal of the separation circuit, the functions of the digital/analog mixed circuit can be expanded, and various tests can be executed via the external digital circuit device. .

[Embodiment] FIG. 1 is a diagram showing the configuration of a testing device for a mixed digital and analog circuit according to the present invention.

In FIG. 1, a test signal generator 20 in a test device 2
2 generates a des1- signal of frequency f1 based on the reference frequency of the reference frequency generator 201, and supplies it to the A/D converter 101 in the LSI.

The digital output of the A/D converter 101 is subjected to the necessary signal processing by the next digital circuit 102, and then sent to the D/A converter 10.
3 converts it into an analog signal and sends it to the A/D in the test equipment 2.
It is digitally converted by converter 207 and temporarily stored in memory 208 . A computer 209 calculates a test result from the contents stored in the memory 208 and outputs the result.

A clock signal of frequency f is supplied to the A/D converter 101 and the digital circuit 102 in the LSI, and the D/A
Converter 103 is supplied with a clock signal of frequency f.

These clock frequencies are converted from the reference frequency of the reference frequency generator 201 in the test equipment 2 to the frequency transformers 203 and 2.
05, clock generators 204 and 206
It is generated by shaping the waveform.

Frequency transformers 203 and 205, etc. are for example phase l
Since it is configured as a lock 1 to loop, the above frequencies f and f can be set with the required detail based on the above reference frequency.
You can win 3rd place by an adult cow.

Therefore, the sampling frequency of the A/D converter 101 is set to f for the test signal of frequency f.

can be set by shifting the beat frequency by the required beat frequency, and furthermore, the digital circuit 102 can be set by shifting the sampling frequency f2.
It is possible to operate in synchronization with the

FIG. 2 is a waveform diagram explaining the operation inside the LSII, in which the A/D converter 101 and the digital circuit 102
2 shows a situation where the D/A converter 103 is being DC tested. (1) is the A/D converter 101
is the test signal waveform of frequency f1 input to (2
) is a clock signal of frequency f. (3) is a waveform in which the test signal f1 is sampled and held by the clock f, and (4) is a waveform in which each flat part of the waveform in (3) has been digitally processed by the digital circuit 102.For easier understanding, the waveform is expressed in analog highs and lows. This is what I did. (5) is the waveform of the taro clock f3, and the height of each part of the waveform (4) is sequentially converted into an analog value by the D/A converter 103 as shown in (6).

In FIG. 2, five points are sampled per cycle of the test signal f1, and the D/A converter 103 operates once for every six sample points.

The number of such points is for convenience of illustration, but +A
The /D converter 101 and the digital circuit 102 are not working in the high-speed AC test, and the D/A converter 103 has a low-speed
This shows how the C test is being performed.

The reason why each block in an LSI can be tested separately into AC and DC tests is that the test signal f1, clocks f2, f3, etc. can be freely set using the frequency synthesizers 203 and 205 shown in FIG. This is because it is possible.

Therefore, it is possible to freely set fl and f2 in a relationship that allows the beat frequency to be generated.

It is also possible to perform a high-speed AC test only on the A/D converter 101 and perform a low-speed DC test I- on the digital circuit 102 and the D/A converter 1.03.

FIG. 3 is a diagram illustrating the structure of an LSI according to the present invention that enables various tests using the tarok signal shown in FIG. 1.

A/D converter 101 and digital circuit 102 in LSII
, and the D/A converter 103, etc., operate according to the normal clock during normal operation, and during testing, each switch SWI~
SW3 supplies test clocks (1) to (3), respectively. In addition, a test mode switching signal is input from the outside for switching each of the switches, and each test according to the present invention similar to that shown in FIG. 1 can be performed.

FIG. 4 shows a case where separation circuits 104, 105, etc. are provided between each block in the LSI according to the present invention shown in FIG. 3 above. These separation circuits allow test digital signals to be input and output between the blocks, so that independent test signals can be input to each block and test results for each block can be independently retrieved. In the present invention, the clocks supplied to each block can be set independently, so by providing each of the separation circuits between the stages, it is possible to effectively perform an independent test of each block.

FIG. 5 shows that the test results of the A/D converter 101 are connected from the separation circuit 104 to the separation circuit 105 by a signal bus, so that the test can be performed by directly connecting the A/D converter 101 and D/A converters 1 and 03. 2 is a diagram showing the configuration of an LSI according to the present invention, in which a test signal is inputted to the digital circuit 102 from a separating circuit 104 independently from these, and a test result is outputted from the digital circuit 105. FIG.

L and SI may be used to connect an external digital additional circuit to the digital circuit 102.

In such a case, the digital circuit 10 as shown in FIG.
If the separation circuits 104 and 105 are provided at the input and output sections of 2, the external digital addition circuit can be easily connected.

It is also possible to test by completely replacing the digital circuit 102 with an external digital addition circuit.

FIG. 6 shows a case where a digital test device 3 is connected as the external digital addition circuit.

FIG. 7 generally shows the embodiments of the present invention shown in FIG. 1 and FIGS. 3 to 6.

Pattern generator 2 for digital/analog mixed LSII
Test patterns for Digimol circuit tests 1 to 1 are supplied from 10, and analog signals for testing are input from an arbitrary waveform generator 211 to the A/D converter and other analog circuits.

These are operated by clock signals from clock transformers 213 and 214 which are referenced to reference frequency generator 201. Further, similar clock signals from clock transformers 215 to 217 are input to the mixed digital/analog LSII. The resulting digital signals are stored in the memory 208, and the analog signals are digitally processed by the waveform digitizer 212, each of which has a clock transformer 21.
Each clock signal is supplied from 8.219. Processing of the above test results, setting of each test signal, setting of each tarok frequency, etc. are performed by the computer 209.

Further, each of the clock transformers 213 to 219 and the like is provided with a frequency synthesizer circuit as necessary, so that the required frequency can be changed based on the reference clock frequency.

[Effects of the Invention] According to the present invention, it is possible to simultaneously perform a DC test on a part of each functional block in a digital/analog mixed circuit device and an AC test on other functional blocks. You should be able to effectively isolate each functional block and test it efficiently.

Further, since each clock signal frequency for the DC test and AC test can be arbitrarily set, the test speed of each functional block can be appropriately set.

In addition, since the sampling frequency of the A/D converter can be set arbitrarily relative to the frequency of the analog test signal, the
A beat frequency test of the /D converter can be performed.

Furthermore, since the test result signal can be digitally converted and stored in synchronization with the clock signal frequency of each of the functional blocks, the entire test equipment system can be operated synchronously.

Moreover, since each functional block therein is equipped with a circuit for switching between a normal clock signal and a test clock signal, it can be easily connected to the test apparatus of the present invention.

In addition, the digital/analog mixed circuit of the present invention can output test signals from between each of the functional blocks mentioned above, and can also input test signals, so an external digital circuit device can be connected to each functional block to perform its functions. extend or
Various tests can be performed via the external digital circuit device.

Further, by connecting the plurality of separated circuits with a signal bus, for example, it is possible to skip an intermediate digital circuit and perform a combination test of an A/D converter and a D/A converter.

[Brief explanation of the drawing]

1 and 7 are diagrams each showing an embodiment of a test device according to the present invention, FIG. 2 is an example of an operation waveform diagram of a digital-analog mixed circuit, and FIGS. 3 to 6 are diagrams showing an example of a digital-analog mixed circuit according to the present invention. FIG. 1...LSI, 101...A/D converter, 102...
...Digital circuit, 103...D/A converter, 104
... Separation circuit, 2 ... Test device, 201 ... Reference frequency generator, 202 ... Test signal generator, 203
...Frequency transformer, 204...Clock generator, 2
13-219...Each clock transformer, 208...Memory, 209...R+calculator, 210...No (turn generator), 211...Arbitrary waveform generator, 212...Waveform digitizer , 3...Digital testing device.

Claims (1)

[Claims] 1. In a testing device for a digital/analog mixed circuit,
The digital clock is characterized by comprising at least a plurality of clock generation means whose frequencies can be set independently, and which supplies the clock signals whose frequencies can be set independently to the functional blocks in the digital/analog mixed circuit. Analog mixed circuit test equipment. 2. The digital device according to claim 1, further comprising a reference frequency generation means and a frequency transformation means, wherein the frequency of the reference frequency generation means is transformed by the frequency transformation means to generate the clock signal.・Test equipment for analog mixed circuits. 3. According to claims 1 and 2, a test pattern signal of the digital/analog mixed circuit based on the frequency of the reference frequency generation means or the frequency transformation means;
A testing device for a mixed digital/analog circuit, characterized by being equipped with means for generating an analog test signal, etc. 4. In claims 1 to 3, the frequency of the reference frequency generation means or the frequency transformation means is used as a reference.
A test device for a mixed digital/analog circuit, comprising means for digitally converting the test output signal of the digital/analog mixed circuit, and means for storing the digitally converted signal of the test output. 5. In a digital/analog mixed circuit including a digital/analog converter circuit block, a digital signal circuit block, etc. that operate in synchronization with each clock signal, the above-mentioned A mixed digital/analog circuit, characterized in that at least some of the plurality of circuit blocks are provided with clock signal switching means for switching between the normal clock signal and the test clock signal. 6. In claim 5, a separation circuit having a test terminal is provided in at least a part of an intermediate portion of the plurality of circuit blocks, and the test terminal outputs a test signal to be output to the separation circuit, and A mixed digital/analog circuit, characterized in that a test signal is input to the separation circuit. 7. The digital/analog mixed circuit according to claim 6, further comprising a signal bus connecting the plurality of separation circuits. 8. The digital/analog mixed circuit according to claim 6, wherein an external digital circuit device is connected to each test terminal of the plurality of separation circuits.