JPH04208788A - Logical comb filter - Google Patents

Abstract

PURPOSE:To reduce the size of a circuit by fixing one input of an adder on a main signal and determined the other input in accordance with the level relation of three signals, i.e., an input signal, the main signal and a presignal. CONSTITUTION:The main signal is impressed to one input of the adder 41 and a signal selected by the following condition is impressed to the other input. Namely when the level relation of main signal (d) > input signal (c) > the output signal (presignal) (e) of the 2nd circuit or presignal (e) > input signal (c) > main signal (d) is formed, the input signal (c) is selected, and when the level relation of main signal (d) > presignal (e) > input signal (c) or input signal (c) > presignal (e) > main signal (d) id formed, the presignal (e) is selected. When the level relation of presignal (e) > main signal (d) > input signal (c) or input signal (c) >main signal (d) > presignal (e) is formed, the main signal (d) is selected and added. Thus the circuit size is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logical comb filter used mainly for Y/C separation in video equipment such as VTRs and TVs, and in particular to a logical comb filter used for Y/C separation in video equipment such as VTRs and TVs. The present invention relates to a logical comb filter that can be constructed economically in processing.

[Conventional technology]

Conventionally, this type of filter has been constructed using a maximum value circuit and a minimum value circuit. FIG. 4 shows an example of its block configuration. The following description will be made with reference to this drawing. The input signal a passes through the delay circuit 11 and then further passes through the delay circuit 12.
pass through. The input signal and the output of delay circuit 11 are also connected to maximum value circuit 21 and minimum value circuit 31. Also,
The output of delay circuit 1.1.12 is also connected to maximum value circuit 22 and minimum value circuit 32. Maximum value circuit 21°22
The output of minimum value circuit 33 is inputted to minimum value circuit 31 .
The output of 32 is input to the maximum value circuit 23. The outputs of the maximum value circuit 23 and the minimum value circuit 33 are input to an adder circuit 41, and the addition result becomes an output signal. Here, the maximum value circuit outputs the higher level of two inputs, and the minimum value circuit outputs the lower level of the two inputs.

With the above configuration, a comb filter can be realized by setting the delay time of the delay circuits 11 and 12 to one scanning line period of the video signal. In the configuration shown in FIG. 4, by inputting a composite video signal as an input signal, a luminance signal can be obtained as an output. Further, if the polarity of the signal is inverted when inputting the output of the delay circuit 11 to the maximum value circuit or the minimum value circuit, a chroma signal can be obtained as an output.

When FIG. 4 is constructed from an analog circuit, both the maximum value circuit and the minimum value circuit can be constructed from a simple circuit of about 152 toranons. However, when configuring with Teshital, there is generally no maximum value circuit and minimum value circuit, so NAN
It is constructed by combining D circuits and NOR circuits, or by using comparison circuits and selectors. Usually, a comparison circuit and a selector are used. An example of the configuration in this case is shown in FIG.

FIG. 5 is an example of a logical comb filter block diagram for separating a chroma signal from a composite video signal. Both the input signal a and the output signal are binary digital codes. First, the input signal a passes through the bandpass filter 81, and then sequentially passes through the one-line delay circuits 11 and 12. The output of the bandpass filter 81 (hereinafter input signal C
) is also connected to the + side of the comparison circuit 51, the L side of the selector 61, and the H side of the selector 62. The output of the one-line delay circuit 11 is connected to an inverting amplifier 71. The output of the inverting amplifier 71 (hereinafter referred to as main signal d) is sent to one side of the comparison circuit 51, the + side of the comparison circuit 52, and the selector 61.6.
4 and the L side of selectors 62 and 63. 1
The output of the line delay circuit 12 (hereinafter referred to as the previous signal e) is
One side of the comparison circuit 52, the H side of the selector 63, the selector 6
Connected to the L side of 4. The output of comparison circuit 51 is connected to the selection control of selectors 61.62, and the output of comparison circuit 52 is connected to the selection control of selectors 63.64. The output of the selector 61 is connected to the + side of the comparison circuit 54 and the H side of the selector 66, and the output of the selector 63 is connected to one side of the comparison circuit 54 and the L side of the selector 66. The output of the selector 62 is the + side of the comparison circuit 53 and the L side of the selector 65.
The output of the selector 64 is connected to one side of the comparison circuit 53 and the H side of the selector 65. Selector 65.
The output of 66 is connected to an adder circuit 41, and the addition result passes through an inverting amplifier 72 once and becomes an output signal.

Next, the operation shown in FIG. 5 will be explained. First, input signal a
A bandpass filter 81 extracts the high frequency components of the luminance signal and the chroma signal. This filtering process is logical
This is preliminary processing to stabilize the operation of the com. The preprocessed input signal C and the main signal d are compared in magnitude by a comparison circuit 51. If the input signal C is larger, the output of the comparator circuit 51 becomes H; if it is smaller, the output becomes L. The output of the comparison circuit 51 controls the selectors 61 and 62.
1 selects the smaller signal, and selector 62 is connected to select the larger signal.

That is, they correspond to the minimum value circuit 31 and maximum value circuit 21 in FIG. Similarly, the comparison circuit 52 and the selector 63
corresponds to the minimum value circuit 32, and the comparison circuit 52 and selector 6
4 corresponds to the maximum value circuit 22. Next, selector 61.
The output of the selector 62 and 63 is inputted to a maximum value circuit made up of a comparison circuit 54 and a selector 66, and the output of the selectors 62 and 64 is inputted to a minimum value circuit made up of a comparison circuit 53 and a selector 65. The respective results are added by an adder circuit 41. Unlike in FIG. 4, the inverting amplifier 72 is included after the addition to correct the phase and gain. Further, the inverting amplifier included on the output side of the one-line delay circuit 11 is also used for phase matching.

[Problem to be solved by the invention]

Among the above-mentioned configurations, the number of transistors may be small if the analog transistor is used, but the number of transistors is considerably increased if the transistor is configured digitally. For example, if the sign bit length of the signal is 8 hits, which is common, there will be 60 gates for the comparator circuit and 22 gates for the selector, resulting in a total of 432 gates including the adder circuit (1 gate and 4 transistors in the case of CMOS gates). .

In recent years, logical comb filters have been used in consumer VTRs, but digital filters are increasingly used for mass production (no adjustment) and stability over time. However, as mentioned above, a digital configuration has the disadvantage of increasing the circuit scale and increasing the price.

[Differences between the invention and the prior art]

In contrast to the conventional logical comb filter described above, the present invention fixes one input of the adder circuit to the main signal, and fixes the other input to the magnitude relationship of the three signals, input signal C1, main signal d, and previous signal e. The difference is that it is determined by

[Means to solve the problem]

The logical comb filter of the present invention includes a circuit 1 that delays an input signal by one scanning line period, a circuit 2 that delays an output signal of the circuit 1 (hereinafter referred to as the main signal) by one scanning line period, and an adder circuit. A main signal is added to one input of the adder circuit, and a signal selected under the following conditions is added to the other input of the adder circuit.

Conditions: Main signal>Input signal>The magnitude relationship of the output signal of the second circuit (hereinafter referred to as the previous signal) or the previous signal>Input signal>
If the magnitude relationship of the main signals is the same, select the input signal, or if the magnitude relationship of the main signal > previous signal > the input signal or input signal > the previous signal > the main signal, select the previous signal, and select the previous signal. If the magnitude relationship between the main signal and the input signal or the magnitude relationship between the input signal and the main signal is the same as the previous signal, select the main signal.

Another method has a circuit that takes the average value of the input signal and the previous signal, and calculates the average value of the input signal and the previous signal.
It is characterized in that the output of the average value circuit is selected when the magnitude relationship of the main signal>input signal or the magnitude relationship of the input signal>main signal>previous signal has passed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an example implementation of the present invention.

Similar to FIG. 5, this is a configuration for separating chroma signals. Input signal a is connected to bandpass filter 81 and l-line delay circuit 11. The output of the bandpass filter 81 (hereinafter referred to as input signal C) is the + of the comparison circuit 51.55.
side and the H side of the selector 67. The output of the 1-line delay circuit 11 passes through a bandpass filter 82 and is connected to the inverting amplifier 71 and the 1-line delay circuit 12.

The output of the inverting amplifier 71 (hereinafter referred to as main signal d) is connected to one side of the comparison circuit 51, the + side of the comparison circuit 52, the L side of the selector 68, and one input of the addition circuit 41. The output of the l-line delay circuit 12 (hereinafter referred to as the previous signal e) is connected to one side of the comparison circuits 52 and 55 and to the L side of the selector 67. The output of the selector 67 is connected to the H side of the selector 68, and the output of the selector 68 is connected to the other input of the adder circuit 41. The output of the adder circuit 41 passes through an inverting amplifier 72 and becomes an output signal. Also, the comparison circuit 51.
The output of 55 is connected to the exclusive OR 91, and the output of the exclusive OR 9
The output of 1 is connected to the select control of selector 67.

Similarly, the outputs of the comparison circuits 51 and 52 are connected to the exclusive OR 92, and the output of the exclusive OR 92 is connected to the selection control of the selector 68.

In the above configuration, the bandpass filters 81 and 82 are placed before and after the 1-line delay circuit 11 in order to use the output of the 1-line delay circuit 11 in brightness processing (not shown). If only for separating chroma signals, one bandpass filter as shown in FIG. 5 is sufficient.

Next, the operation of the circuit shown in FIG. 1 will be explained in terms of the magnitude relationship between the input signal C2, the main signal d, and the previous signal e.

■Main signal d〉Input signal C〉Previous signal e or previous signal e〉
Input signal C> main signal d In this case, the output of the comparison circuit 51 is L and the output of the comparison circuit 55 is H, or the output of the comparison circuit 51 is H and the output of the comparison circuit 55 is L. . In either case, the output of the exclusive OR 91 becomes H, and the output of the selector 67 is compared to the H side, that is, the input signal C. Further, the outputs of the comparison circuits 51 and 52 are also L, H or H, L, and the output of the exclusive OR 92 is H. As a result, the output of the selector 68 becomes the output of the selector 67, that is, the input signal C. In the end, the adder circuit 41 adds the input signal C and the main signal d.

■Main signal d〉Previous signal e〉Input signal C or input signal C
〉Previous signal e〉Main signal d In this case, are the outputs of the comparator circuits 51 and 55 both L?
Alternatively, both become H, and the output of the exclusive OR 91 becomes L. The output of the exclusive OR 92 becomes H, which is the same as in the above-mentioned case (2). Therefore, the output of the selector 68 becomes the L side of the selector 67, that is, the previous signal e. In the end, adder circuit 4
1, the main signal d and the previous signal e are added.

■Input signal C〉Main signal d〉Previous signal e or previous signal e〉
When main signal d>input signal C In this case, are the outputs of the comparator circuits 51 and 52 both H?
Or both become L. As a result, the exclusive OR 92
The output of the selector 68 becomes L, and the output of the selector 68 becomes the L side, that is, the main signal d. Eventually, both inputs of the adder circuit 41 become the main signal d.

I will clarify. Table 1 shows the outputs of the comparison circuits 51, 52, and 55, the magnitude patterns of the signals c, d, and e, and the inputs of the addition circuit of the conventional logical comb filter. Among the inputs of the adder circuit, the MIN-MAX column shows the output signal of the minimum value circuit 33 in FIG. 4. MAX-MIN
The column shows the pressure signal of the maximum value circuit 23 in FIG. Looking at the inputs of these adder circuits, one of the inputs becomes the main signal d even in the case of the pattern.

Therefore, one input of the adder circuit can be fixed to the main signal d as in the present invention. Further, the other input of the adder circuit can be selected from among the input signals C1, main signal d2, and previous signal e, depending on the signal magnitude pattern.

[Example 2] FIG. 2 is a block diagram of a second embodiment of the present invention.

Hereinafter, parts different in configuration from FIG. 1 will be explained. First, delay circuits 13, 14, and 15 are inserted into each output of the bandpass filter 812, inverting amplifier 71, and line delay circuit 12. In addition, the delay circuit 16
is connected. The output of the delay circuit 16 and the output of the inverting amplifier 71 are added in an adder circuit 42 and connected to the L side of the selector 68 through an inverting amplifier 73. Delay circuit 13,1
4°15.16 both delay the phase of the chroma signal by 180 degrees, and in the case of an NTSC video signal, the delay time is 140 nanoseconds.

Next, the differences in operation from FIG. 1 will be explained. The operation differs when the output of the selector 68 is on the L side. In this case, the main signal d was selected in the circuit of FIG. 1, but in the second embodiment, the average value of a signal whose phase of the main signal d is advanced by 180 degrees and a signal whose phase is delayed by 180 degrees is selected. Adding the average value and the main signal d using the adding circuit 41 is an operation equivalent to performing band pass filter processing.

The purpose of the bandpass filter 82 is to remove low-frequency components of luminance from the input signal a, and the main signal d includes high-frequency components of luminance. When the selector 68 is on the L side, the main signal d becomes the output signal d in the circuit shown in FIG. 1, so that the output includes a luminance component. In the case of the second embodiment, since a band pass filter is added when the selector 68 is on the L side, the luminance component leaking due to pressure can be reduced.

[Example 3] FIG. 3 is a block diagram of a third embodiment of the present invention.

The difference in configuration from FIG. 1 is that L inputs of the selector 68 are connected to the output of the average value circuit 43.

Signals c and e are input to the average value circuit 43. The characteristics when the output of the selector 68 is on the L side are those of a comb-shaped filter expressed by the following equation.

Kay7 = I CO3 (2K f/fH) 1
lfH: If the horizontal scanning frequency input signal is an integral multiple of fH, the gain is zero.

Since the spectrum of the luminance component of the video signal is located at an integral multiple of f8, this filter is useful for reducing the luminance component. That is, compared to the configuration shown in FIG. 1, the luminance component leaking into the output can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, one comparator circuit and four selectors can be reduced to configure a circuit with characteristics equivalent to those of the conventional circuit. The increase in circuits is only 2 exclusive ORs, and the difference is 14
This is a reduction of 2 gates. That is, there is an effect that a logical comb filter can be constructed at a lower cost than before. Also,
When adding a band-pass filter or comb-shaped filter to improve characteristics, conventionally it was necessary to add a separate band-pass filter or comb-shaped filter, but in the present invention, one adder circuit can be shared.

That is, there is an effect that one adder circuit (60 gates) can be constructed at a low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of Embodiment 1 of the present invention, FIG. 2 is a block diagram of Embodiment 2 of the present invention, and FIG. 3 is a block diagram of Embodiment 3 of the present invention.
4 is a block diagram of a conventional embodiment, and FIG. 5 is a conventional digital configuration 15.16...180
Degree delay circuit, 21, 22° 23...Maximum value circuit, 31, 32.33...Minimum value circuit, 41.4
2... Addition circuit, 43... Average value circuit, 51, 52, 53, 54.55... Comparison circuit,
61, 62, 63, 65, 65, 66.67°68...
... Selector, 71, 72.73 ... Inverter 7', 81.82 ... Band pass filter, 91°92 ... Exclusive OR circuit, a, c ... Input Signal, b... Output signal, d... Main signal, e
...Previous signal. Agent: Patent attorney Shinkon Uchihara

Claims (2)

[Claims] (1) a first circuit that delays an input signal by one scanning line period;
a second circuit that delays the output signal of the first circuit (hereinafter referred to as the main signal) by one scanning line period; and an adder circuit; the main signal is added to one input of the adder circuit; If the other input of the adding circuit has a magnitude relationship of main signal > input signal > output signal of the second circuit (hereinafter referred to as the previous signal) or a magnitude relationship of previous signal > input signal > main signal, the input signal If the magnitude relationship of main signal > previous signal > input signal or input signal > previous signal > main signal is true, select the previous signal, and select the previous signal > main signal > magnitude relationship of input signal or input signal > A logical comb filter that selects and adds the main signal when the magnitude relationship between the main signal and the previous signal holds true. (2) It has a circuit that takes the average value of the input signal and the previous signal, and when the magnitude relationship of the previous signal > main signal > input signal or the magnitude relationship of input signal > main signal > previous signal holds, the average value circuit A logical comb filter according to claim 1, characterized in that the output is selected.