JPH0250578A - Vertical contour emphasizing circuit - Google Patents

Vertical contour emphasizing circuit

Info

Publication number
JPH0250578A
JPH0250578A JP63201389A JP20138988A JPH0250578A JP H0250578 A JPH0250578 A JP H0250578A JP 63201389 A JP63201389 A JP 63201389A JP 20138988 A JP20138988 A JP 20138988A JP H0250578 A JPH0250578 A JP H0250578A
Authority
JP
Japan
Prior art keywords
vertical contour
vertical
signal
circuit
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63201389A
Other languages
Japanese (ja)
Inventor
Takuji Kurashita
蔵下 拓二
Noriyuki Yamaguchi
山口 典之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63201389A priority Critical patent/JPH0250578A/en
Publication of JPH0250578A publication Critical patent/JPH0250578A/en
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To obtain the effect of a contour emphasis even in an enlarged picture by providing a first vertical contour correcting means to extract a high frequency component in a vertical direction and a second vertical contour correcting means to have a filtering characteristics to extract the 1/2 frequency component, and suitably using the characteristic of the vertical contour emphasizing means between the enlarged picture and the other picture. CONSTITUTION:A/C-converted input digital video signals pass through one-line delay circuits 4a to 4d, obtain sampling values at five sampling points on a longitudinal straight line on a screen, and constitute vertical contour correcting circuits 5a and 5b in two systems. The second vertical contour correcting circuit 5b has the filtering characteristic to extract the 1/2 frequency component of the frequencies to be emphasized at the time of the normal picture. Contour correcting signals 106 and 107 are sent to a switching circuit 7 together with a control signal 108, the switching circuit 7 switches the first or second vertical contour correcting signal by the control signal 108, and a vertical correcting signal 109 is added to an original signal 103 to be outputted as a vertical contour emphasis signal 101. Thus, even in the enlarged picture, the effect of the contour emphasis can be obtained in the same way as the normal picture.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は垂直輪郭強調回路に関し、特に拡大機能を持
つテレビジョン受像機において、水平走査周波数に同期
標本化したテレビジョン信号の垂直輪郭強調回路に関す
るものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a vertical contour emphasizing circuit, and particularly to a vertical contour emphasizing circuit for a television signal sampled in synchronization with a horizontal scanning frequency in a television receiver having an enlargement function. It is related to.

〔従来の技術〕[Conventional technology]

第2図は従来の垂直輪郭強調回路の構成の一例を示すブ
ロック図である0図において、入力端子1にはディジタ
ル映像信号が入力される。入力されたディジタル映像信
号201は1ライン遅延回路4e、4fに順次与えられ
る。入力ディジタル映像信号201及び1ライン遅延回
路4e、4fの出力202.203は垂直輪郭補正回路
5Cに与えられる。垂直輪郭補正回路5Cの出力204
は加算回路6bの一方入力に与えられ、加算回路6bの
他方入力には、1ライン遅延回路4eの出力202が与
えられる。加算回路6bの出力205は垂直輪郭強調信
号として出力端子3に与えられる。
FIG. 2 is a block diagram showing an example of the configuration of a conventional vertical edge enhancement circuit. In FIG. 0, a digital video signal is input to an input terminal 1. In FIG. The input digital video signal 201 is sequentially applied to one-line delay circuits 4e and 4f. The input digital video signal 201 and the outputs 202 and 203 of the 1-line delay circuits 4e and 4f are applied to the vertical contour correction circuit 5C. Output 204 of vertical contour correction circuit 5C
is applied to one input of the adder circuit 6b, and the output 202 of the one-line delay circuit 4e is applied to the other input of the adder circuit 6b. The output 205 of the adder circuit 6b is applied to the output terminal 3 as a vertical contour emphasis signal.

次に上記垂直輪郭強調回路の動作について説明する。Next, the operation of the vertical contour emphasizing circuit will be explained.

入力ディジタル映像信号201は1ライン遅延回路4e
、4fに順次与えられ、画面上線−直線の3つの標本点
の標本値が同時に得られ、垂直輪郭補正回路5Cに与え
られる。垂直輪郭補正回路5cは、2変換を用いて以下
の伝達関数で表されるフィルタ特性を持つ。
The input digital video signal 201 is sent to a 1-line delay circuit 4e.
. The vertical contour correction circuit 5c has filter characteristics expressed by the following transfer function using 2 transformation.

G (2)= (−1/4)(1−z−’ )”ここで
、z −Lは1ライン遅延を表す。
G(2)=(-1/4)(1-z-')''where z-L represents one line delay.

上記フィルタ特性は垂直方向の高域成分、部ち垂直方向
の輪郭信号を抽出する特性となっている。
The above-mentioned filter characteristic is a characteristic for extracting a vertical high-frequency component, that is, a contour signal in a vertical direction.

垂直輪郭補正回路5Cの出力204は原信号202と加
算されて垂直輪郭強調信号205として出力される。
The output 204 of the vertical contour correction circuit 5C is added to the original signal 202 and output as a vertical contour enhancement signal 205.

(発明が解決しようとする課題〕 上記従来技術では、通常の画像では問題はないが拡大処
理が行われた画像の場合、周波数が低くなったにもかか
わらず、通常時と同じ周波数成分をフィルタ処理するた
め、正常な輪郭強調の効果が得られないという問題点が
あった。
(Problems to be Solved by the Invention) In the above conventional technology, there is no problem with normal images, but in the case of enlarged images, the same frequency components as normal are filtered out, even though the frequency has become lower. There was a problem in that the normal contour enhancement effect could not be obtained because of the processing.

本発明は上記のような問題点を解消するためになされた
もので、拡大された画像に対しても最適な輪郭強調を行
うことのできる垂直輪郭強調回路を得ることを目的とす
る。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a vertical contour enhancement circuit that can perform optimal contour enhancement even on enlarged images.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る垂直輪郭強調回路は、入力ディジタル映
像信号を遅延して、輪郭強調しようとする注目標本点及
びこれと画面上線−直線となる標本点を同時に得る手段
と、これらの標本点の値から、従来と同じ構成で垂直方
向の高域周波数成分を抽出して出力する第1の垂直輪郭
補正手段と、この第1の垂直輪郭補正手段に対し、1/
2の周波数成分を抽出するフィルタ特性を持つ第2の垂
直輪郭補正手段とを設け、拡大画像に対しては第2の垂
直輪郭補正手段の出力を、それ以外の画像に対しては第
1の垂直輪郭補正手段の出力を選択し、垂直輪郭強調を
行うようにしたものである。
The vertical contour enhancement circuit according to the present invention includes a means for delaying an input digital video signal to simultaneously obtain a sample point of interest to be contour-enhanced and a sample point that forms a line-straight line on the screen, and the values of these sample points. , the first vertical contour correction means extracts and outputs high frequency components in the vertical direction with the same configuration as the conventional one, and the first vertical contour correction means has a ratio of 1/
A second vertical contour correction means having a filter characteristic for extracting two frequency components is provided. The output of the vertical contour correction means is selected to perform vertical contour enhancement.

〔作用〕[Effect]

この発明においては、拡大画像とそれ以外の画像とで垂
直輪郭強調回路の特性を使い分けるようにしたため、拡
大画像においても通常画像と同様に輪郭強調の効果を得
ることができる。
In the present invention, the characteristics of the vertical edge enhancement circuit are used differently for enlarged images and other images, so that the effect of edge enhancement can be obtained in enlarged images as well as in normal images.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例による垂直輪郭強調回路を示
す概略ブロック図である0図において、1はディジタル
映像信号が与えられる入力端子である。入力されたディ
ジタル映像信号101は、1ライン遅延回路4a、4b
、4c、4dに順次与えられる。第1の垂直輪郭補正回
路5aには、上記1ライン遅延回路の出力のうち1ライ
ン遅延回路4a、4b、4cの出力102,103,1
04が与えられる。また、第2の垂直輪郭補正回路5b
には入力信号101及び1ライン遅延回路4b、4dの
出力103.105が与えられる。
FIG. 1 is a schematic block diagram showing a vertical edge enhancement circuit according to an embodiment of the present invention. In FIG. 0, 1 is an input terminal to which a digital video signal is applied. The input digital video signal 101 is sent to one-line delay circuits 4a and 4b.
, 4c, and 4d sequentially. The first vertical contour correction circuit 5a includes outputs 102, 103, 1 of the one-line delay circuits 4a, 4b, 4c among the outputs of the one-line delay circuit.
04 is given. In addition, a second vertical contour correction circuit 5b
is given an input signal 101 and outputs 103 and 105 of the one-line delay circuits 4b and 4d.

垂直輪郭補正回路5a、5bの出力106.107は、
入力端子3より入力された制御信号108とともにスイ
ッチ回路7に与えられる。制御信号108は入力映像信
号が拡大処理された信号であるかないかによってスイッ
チ回路7を制御する信号である。スイッチ回路7の出力
109は、垂直輪郭補正信号として加算回路6aの一方
入力に与えられ、加算回路6aの他方入力には、1ライ
ン遅延回路4bの出力103が与えられる。加算回路6
aの出力1)0は垂直輪郭強調信号として出力端子2に
送出される。
The outputs 106 and 107 of the vertical contour correction circuits 5a and 5b are:
It is applied to the switch circuit 7 together with the control signal 108 input from the input terminal 3. The control signal 108 is a signal that controls the switch circuit 7 depending on whether the input video signal is an enlarged signal or not. The output 109 of the switch circuit 7 is applied as a vertical contour correction signal to one input of the adder circuit 6a, and the output 103 of the one-line delay circuit 4b is applied to the other input of the adder circuit 6a. Addition circuit 6
The output 1)0 of a is sent to the output terminal 2 as a vertical contour emphasis signal.

次に動作について説明する。Next, the operation will be explained.

入力端子への入力映像信号が拡大画像(ここでは2倍拡
大とする)の場合、第3図に示すように拡大前の各ライ
ンは2度ずつ走査される。従って拡大画像の信号が入力
された場合は、拡大されていない通常の信号が入力され
た時と同様の輪郭強調の効果を上げるためには、2ライ
ン間隔の標本点を使った輪郭強調、即ち通常画像の時強
調する周波数の1/2の周波数成分を抽出するフィルタ
処理が必要となる。以下第1図を用いて説明する。
When the input video signal to the input terminal is an enlarged image (here, it is assumed to be 2 times enlarged), each line before enlargement is scanned twice as shown in FIG. Therefore, when an enlarged image signal is input, in order to achieve the same contour enhancement effect as when a normal signal that has not been enlarged is input, it is necessary to enhance the contour using sample points spaced two lines apart. Filter processing is required to extract a frequency component that is half the frequency that is emphasized in the case of a normal image. This will be explained below using FIG.

A/D変換された入力ディジタル映像信号は、1ライン
遅延回路4a、4b、4c、4dを通り、画面上線−直
線の5つの標本点における標本値が得られる。これらの
標本点をもとに2系統の垂直輪郭補正回路を構成する。
The A/D-converted input digital video signal passes through one-line delay circuits 4a, 4b, 4c, and 4d, and sample values at five sample points between lines on the screen are obtained. Two systems of vertical contour correction circuits are constructed based on these sample points.

第1の垂直輪郭補正回路5aは、1ライン遅延回路4a
、4b、4cの出力102,103.104により、以
下の伝達関数で表されるフィルタ特性を持つ。
The first vertical contour correction circuit 5a includes a one-line delay circuit 4a.
, 4b, 4c have filter characteristics expressed by the following transfer function.

F、  (z)= (−1/4)(1−z−’)”第2
の垂直輪郭補正回路5bは、入力ディジタル映像信号1
01と、1ライン遅延回路4b、4dの出力103,1
05により、以下の伝達関数で表されるフィルタ特性を
持つ。
F, (z) = (-1/4) (1-z-')"2nd
The vertical contour correction circuit 5b receives the input digital video signal 1.
01 and the outputs 103, 1 of the 1-line delay circuits 4b and 4d.
05, it has filter characteristics expressed by the following transfer function.

Ft  (2)=  (−1/4)  (1z−”)”
上記輪郭補正信号106,107は制御信号108と共
にスイッチ回路7に送出される。制御信号108は入力
ディジタル映像信号が拡大映像信号であるかないかによ
ってスイッチ回路7を制御する信号である。制御信号1
08により、スイッチ回路7は第1あるいは第2の垂直
輪郭補正信号を以下のように切り換える。
Ft (2)= (-1/4) (1z-")"
The contour correction signals 106 and 107 are sent to the switch circuit 7 together with the control signal 108. The control signal 108 is a signal that controls the switch circuit 7 depending on whether the input digital video signal is an enlarged video signal or not. Control signal 1
08, the switch circuit 7 switches the first or second vertical contour correction signal as follows.

拡大画像:第2の垂直輪郭補正信号を選択上記以外:第
1の垂直輪郭補正信号を選択スイッチ回路7で選択出力
された垂直輪郭補正信号109は、原信号103と加算
されて垂直輪郭強調信号101として出力される。
Enlarged image: Select the second vertical contour correction signal Other than the above: Select the first vertical contour correction signal The vertical contour correction signal 109 selected and output by the switch circuit 7 is added to the original signal 103 to produce a vertical contour emphasis signal. It is output as 101.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明にかかる垂直輪郭強調回路によ
れば、拡大画像とそれ以外の画像とで、垂直輪郭強調回
路の特性を切り換えるようにしたので、拡大画像におい
ても通常画像と同様に輪郭強調の効果をあげることがで
きる効果がある。
As described above, according to the vertical contour emphasizing circuit according to the present invention, the characteristics of the vertical contour emphasizing circuit are switched between enlarged images and other images. It has the effect of increasing emphasis.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による垂直輪郭強調回路の
一例を示す概略ブロック図、第2図は従来の垂直輪郭強
調回路の一例を示す概略ブロフク図、第3図は通常画像
から拡大画像への走査変更を行った場合の標本点の配列
を示す図である。 1.3は入力端子、2は出力端子、4a〜4dは1ライ
ン遅延回路、5a、5bは第1.第2の垂直輪郭補正回
路、6aは加算回路、7はスイッチ回路である。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a schematic block diagram showing an example of a vertical edge enhancement circuit according to an embodiment of the present invention, FIG. 2 is a schematic block diagram showing an example of a conventional vertical edge enhancement circuit, and FIG. 3 is an enlarged image from a normal image. FIG. 6 is a diagram showing an arrangement of sample points when scanning is changed to . 1.3 is an input terminal, 2 is an output terminal, 4a to 4d are one-line delay circuits, 5a and 5b are first . In the second vertical contour correction circuit, 6a is an adder circuit, and 7 is a switch circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)各標本点が画面上で格子状に配列するよう水平走
査周波数に同期した所定の周波数で標本化されたディジ
タル映像信号を入力とし、該ディジタル映像信号から垂
直方向の高域成分を強調する垂直輪郭強調回路において
、 前記ディジタル映像信号を遅延して、画面上垂直方向に
一直線上に並ぶような5ラインにわたる5つの標本点の
標本値を同時に得るための遅延手段と、 前記5つの標本点を上から第1、第2、第3、第4、第
5の標本点としたとき、前記第2、第3及び第4の標本
点の標本値を入力とし、垂直方向の高域周波数成分を抽
出して出力する第1の垂直輪郭補正手段と、 前記第1、第3、第5の標本点の標本値を入力とし、垂
直方向の高域周波数成分を抽出して出力する第2の垂直
輪郭補正手段と、 前記ディジタル映像信号が拡大画像であるかないかによ
って、前記第1及び第2の垂直輪郭補正手段の出力を切
換えて出力するスイッチ回路と、前記スイッチ回路の出
力を前記ディジタル映像信号と加算して垂直輪郭強調信
号を出力する加算回路とを備えたことを特徴とする垂直
輪郭強調回路。
(1) Input a digital video signal sampled at a predetermined frequency synchronized with the horizontal scanning frequency so that each sampling point is arranged in a grid on the screen, and emphasize the vertical high frequency components from the digital video signal. A vertical contour enhancement circuit comprising: a delay means for delaying the digital video signal to simultaneously obtain sample values of five sample points across five lines arranged vertically on the screen; and the five samples. When the points are the first, second, third, fourth, and fifth sample points from the top, the sample values of the second, third, and fourth sample points are input, and the high frequency in the vertical direction is a first vertical contour correction means that extracts and outputs a component; and a second vertical contour correction means that receives the sample values of the first, third, and fifth sample points as input, and extracts and outputs a high frequency component in the vertical direction. vertical contour correction means; a switch circuit that switches and outputs the outputs of the first and second vertical contour correction means depending on whether the digital video signal is an enlarged image; 1. A vertical contour emphasizing circuit comprising: an adding circuit that adds a video signal and outputs a vertical contour emphasizing signal.
JP63201389A 1988-08-11 1988-08-11 Vertical contour emphasizing circuit Pending JPH0250578A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63201389A JPH0250578A (en) 1988-08-11 1988-08-11 Vertical contour emphasizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63201389A JPH0250578A (en) 1988-08-11 1988-08-11 Vertical contour emphasizing circuit

Publications (1)

Publication Number Publication Date
JPH0250578A true JPH0250578A (en) 1990-02-20

Family

ID=16440273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63201389A Pending JPH0250578A (en) 1988-08-11 1988-08-11 Vertical contour emphasizing circuit

Country Status (1)

Country Link
JP (1) JPH0250578A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05153439A (en) * 1991-11-29 1993-06-18 Victor Co Of Japan Ltd Contour correction circuit and picture signal processing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05153439A (en) * 1991-11-29 1993-06-18 Victor Co Of Japan Ltd Contour correction circuit and picture signal processing circuit

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