JPH01109813A - Integrated circuit for digital signal processing - Google Patents

Abstract

PURPOSE:To reduce the scale of the hardware of a digital signal processing integrated circuit by providing a delay adjusting circuit before and after a sampling frequency rate conversion circuit, applying coarse adjustment in the pre-stage delay adjusting circuit and applying fine adjustment at the post-stage. CONSTITUTION:A delay adjustment circuit 4 whose operating frequency is given from a 1st frequency (f) is connected between a sampling frequency rate conversion circuit 3 and an input terminal group 7 and a delay adjusting circuit 5 whose operating frequency is given by 2nd frequency nf being an integral number of multiple of the 1st frequency is connected between the sampling frequency rate conversion circuit 3 and an output terminal group 8. Since the unit delay in the delay adjusting circuit 4 is a multiple of (n) of the unit delay of the output signal, the scale of the hardware is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a digital signal processing integrated circuit, and more particularly to a digital signal processing integrated circuit having an internal delay adjustment function.

[Conventional technology]

In recent years, digitalization of image processing etc. has progressed rapidly.
Accordingly, the integration of digital signal processing circuits into integrated circuits is becoming more active. At this time, various conditions are imposed on the sampling frequency related to digital signal processing, and configurations as shown in FIGS. 4 and 5 have been used to optimize the sampling frequency. A conventional example will be described below with reference to FIGS. 4 and 5.

FIG. 4 shows an example of a television signal processing circuit using digital signal processing. The digitized luminance signal (hereinafter simply referred to as luminance signal) is processed by a luminance signal processing circuit system 13 composed of a signal processing circuit 10 whose operating frequency is given by a sampling frequency nf, such as aperture correction, noise reduction, etc. Contrast control etc. are performed. The output of the signal processing circuit 10 is input to a post-processing circuit 16. On the other hand, the digitized color signal (hereinafter simply referred to as color signal) is processed by a signal processing circuit 11 whose operating frequency is given by the sampling frequency f and a signal processing circuit 12 which converts the sampling frequency rate. The circuit system 14 performs, for example, color demodulation, hue control, and the like. The output of the signal processing circuit 12 is input to the post-processing circuit 16 like the luminance signal. In the post-processing circuit 16, for example, a luminance signal and color signal mixing circuit outputs the signal as a video composite signal. In such a television signal processing circuit, the signal processing circuits 10 to 12 and the post-processing circuit 16 are constructed of digital integrated circuits.

At this time, the sampling frequency in each signal processing is
It is set based on the frequency bands of the luminance signal and color signal, etc. In the color signal processing circuit system 14, the frequency is set to 3 to 4 times the MHz (MHz) at which three primary colors are transmitted simultaneously in a color television, but in the luminance signal processing circuit system 13, the frequency is
In the case of this method, the frequency band is 4.5 MHz, so there is no problem in setting it to the same sampling frequency as the color signal processing circuit system 14, but in order to obtain high-definition image quality, the frequency band of the luminance signal Expand the luminance signal processing circuit system 13
It is necessary to set the sampling frequency of the color signal processing circuit system 14 higher than that of the color signal processing circuit system 14. In addition, in the circuit for mixing the luminance signal and the chrominance signal in the post-processing circuit 16, it is necessary to set the sampling frequency of both signals to the same condition, so as shown in FIG. A sampling frequency rate conversion circuit 18 that converts the rate of the frequency multiplier into the sampling frequency nf of the luminance signal processing system 13
is provided. In general, in a sampling frequency rate conversion circuit, it is easier to implement than when converting only the frequency rate of the sampled digital signal, and the hardware is also simple, so the sampling frequency ratio can be changed before and after conversion, for example f and It is set to an integer multiple like nf.

In addition, a signal processing circuit 1 composed of a digital integrated circuit
2, when converting the sampling frequency rate, as shown in FIG. is rate-converted and output via the output terminal group 8.

[Problems with conventional technology]

In conventional digital signal processing for images, for example, when the sampling frequency of the output section of the color signal processing circuit system 14 is rate converted to the sampling frequency of the luminance signal processing circuit system 13, the rate of the sampling frequency of the luminance signal processing circuit system 13 is usually The number of processing steps is greater than that of the color signal processing circuit system 14, and in addition, in order to achieve high image quality, image movement information is extracted from the luminance signal, which further increases the number of processing steps.

Therefore, the processing time of the color signal processing circuit system 14 is relatively faster than that of the luminance signal processing circuit system 13, so in order to finish the aging timing of the output signals from these signal processing systems, the processing time shown in FIG. As shown, a delay adjustment circuit 15 is provided at the output section of the color signal processing circuit system 14.

Conventionally, such a delay adjustment port, path 15, has been provided outside the semiconductor substrate on which the signal processing circuit is mounted, requiring a general-purpose logic integrated circuit such as a shift register circuit.

Furthermore, when a delay adjustment circuit is incorporated into a digital signal processing integrated circuit after converting the sampling frequency rate, the high sampling frequency increases power consumption, limits the amount of delay adjustment, and reduces the degree of freedom. Only small adjustments could be made.

[Purpose of the invention]

The present invention aims to reduce hardware related to signal processing in a digital signal processing integrated circuit, enable integration on the same semiconductor substrate, and reduce power consumption.

[Structure of the invention]

The digital signal processing integrated circuit of the present invention includes a group of input terminals for inputting digital signals sampled at a first sampling frequency, a signal processing circuit whose operating frequency is set at the first sampling frequency, and the signal processing circuit. a sampling frequency rate conversion circuit that receives the output of the input signal and converts the sampling frequency of the signal sampled at the first sampling frequency to a second sampling frequency higher than the first sampling frequency; and the second sampling frequency. In the digital signal processing integrated circuit, the digital signal processing integrated circuit is provided with a group of output terminals for outputting digital signals sampled by the above on the same semiconductor integrated circuit board, wherein the first a first delay adjustment circuit whose operating frequency is set according to the sampling frequency, and a first delay adjustment circuit whose operating frequency is set according to the second sampling frequency between the sampling frequency rate conversion circuit and the output terminal group; It is characterized by having two delay adjustment circuits.

That is, the present invention provides two delay adjustment circuits with different operating frequency characteristics before and after a sampling frequency rate conversion circuit in a digital signal processing integrated circuit, and provides a delay adjustment circuit with a low operating frequency before and after the sampling frequency rate conversion circuit. The circuit adjusts the digital signal to a value close to the desired delay amount, and in the subsequent stage, a delay adjustment circuit with a high operating frequency finely adjusts the delay amount.

〔Example〕

An embodiment of the present invention is shown in FIG. In a digital signal processing integrated circuit l, an input terminal group 7 and an output terminal group 8
A signal processing circuit 2 and a sampling frequency rate conversion circuit 3, which perform signal processing and sampling frequency conversion during this period, are connected in series. Further, between the sampling frequency rate conversion circuit 3 and the input terminal group 7, there is a delay adjustment circuit 4 which is provided with an operating frequency at a first frequency f.
and sampling frequency rate conversion circuit 3'l! A delay adjustment circuit 5 whose operating frequency is given at a second frequency nf which is an integral multiple of the first frequency is connected to the output terminal group 8 , and the delay adjustment circuits 4 and 5 are connected to the control circuit 6 . For example, the first sampling frequency f is set to the second sampling frequency nf (
(where n is an integer of 2 or more), the operating frequency of the delay adjustment circuit 4 is given by f, and the operating frequency of the delay adjustment circuit 5 is given by nf, /. At this time, the desired delay adjustment range Then, by setting each delay adjustment range to the following conditions, it becomes possible to adjust the amount of delay within the desired delay adjustment range X. Therefore, when the delay adjustment of the signal output im-embroidered at the sampling frequency nf is performed by a delay adjustment circuit operating at the sampling frequency nf as in the conventional case, the required delay adjustment range D'' is 0≦D''≦M -(4) At this time, if the maximum delay adjustment amount of the delay adjustment circuit 5 is DX, Ax, and the maximum delay adjustment amount in the conventional case is I)'xAx, (2
) From equation (4), D″NlANlA = −(6
) (5), (6) and (1), D U(A
xkukuD″＞ux (7)(
From equation 7), according to the present invention, the delay adjustment circuit 5 operates at the frequency nf necessary to obtain the desired delay adjustment range.
The delay adjustment range can be significantly reduced. here,
In the present invention, a delay adjustment circuit 4 is required in front of the sampling frequency rate conversion circuit 3, which operates at a frequency f and whose delay adjustment range is set according to the condition expressed by equation (3). Since the delay amount is n times the unit delay amount in the delay adjustment circuit 5, that is, the unit delay amount of the output signal, it is possible to reduce the scale of the hardware as described above. Further, in the present invention, since delay adjustment is performed at a low frequency of ÷ times the sampling rate of the output signal, it is possible to reduce power consumption and is suitable for integration into an integrated circuit.

FIG. 2 is an example in which the digital signal processing integrated circuit of the present invention is applied to the conventional television signal processing circuit using digital signal processing shown in FIG.

FIG. 2 shows a signal processing circuit 12 constituting a color signal processing circuit system 14 of a television signal processing circuit using conventional digital signal processing, to which the digital signal processing integrated circuit 1 of the present invention is applied. Since the output signal from the color signal processing circuit system 24 has already undergone timing adjustment with the output signal from the luminance signal processing circuit system 13, both output signals are input directly to the post-processing circuit 16. Therefore, there is no need to provide a special delay adjustment means such as the delay adjustment circuit 15 shown in FIG. 4 as a conventional example.

Next, FIG. 3 shows an example of a specific configuration means of the delay adjustment circuit in the digital signal processing integrated circuit of the present invention. It is composed of a group of cascade-connected latches 31 to 35 and a multiplexer channel 36 into which output signals from each of these latch output points are input.The control circuit 6 controls the multiplexer channel 36 and determines which latch output is delayed. Delay adjustment is performed by selecting whether to take out the signal as the output of the adjustment circuit 30. With this configuration, there is no need for a delay adjustment means such as a logic integrated circuit, which was conventionally provided separately outside the semiconductor substrate on which the digital signal processing integrated circuit is mounted, and the delay adjustment circuit can be combined with the digital signal processing integrated circuit. They can be formed on the same semiconductor substrate.

〔Effect of the invention〕

In a digital signal processing integrated circuit, the present invention provides delay adjustment circuits before and after a sampling frequency rate conversion circuit that converts the sampling frequency for sampling a digital signal, and coarsely adjusts the amount of delay in the preceding stage delay adjustment circuit. By performing fine adjustment at a later stage, it is possible to reduce the hardware scale of the digital signal processing integrated circuit and to reduce the power consumption required for signal processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a digital signal processing integrated circuit according to the present invention, FIG. 2 is a block diagram showing an example of application of the present invention to a television signal processing circuit, and FIG. FIG. 4 is a block diagram showing a specific example of a delay adjustment circuit, FIG. 4 is a block diagram showing an example of a conventional television signal processing circuit, and FIG. 5 is a block diagram showing the configuration of a conventional signal processing circuit. 1...Digital signal processing integrated circuit, 2゜lO
~12.17.22・River・・Signal processing circuit, 3゜18・
...Sampling frequency rate conversion circuit, 4.5
, 15.30...delay adjustment circuit, 6...
・Control circuit, 14.24... Color signal processing circuit system, 7... Input terminal group, 16... Post-processing circuit, 8... Output terminal Group, 31-35...
... Latch circuit, 9 ... Control input terminal group, 36
...Multiplexer channel, 13...
・Luminance signal processing circuit system. Agent Patent Attorney Shinkyo Uchihara 2 Paintings 3m

Claims (1)

[Claims] a group of input terminals into which digital signals sampled at a first sampling frequency are input; a signal processing circuit whose operating frequency is set according to the first sampling frequency; a sampling frequency rate conversion circuit that converts the sampling frequency of a signal sampled at a sampling frequency to a second sampling frequency; an output terminal group that outputs a digital signal sampled at the second sampling frequency; a first delay adjustment circuit whose operating frequency is set according to the first sampling frequency, which is connected between the rate conversion circuit and the input terminal group, and between the first sampling frequency and the output terminal group; 1. A digital signal processing integrated circuit comprising, on the same semiconductor integrated circuit board, a second delay adjustment circuit whose operating frequency is set according to the second sampling frequency and which is connected to the second delay adjustment circuit.