JPH04207060A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04207060A JPH04207060A JP34013890A JP34013890A JPH04207060A JP H04207060 A JPH04207060 A JP H04207060A JP 34013890 A JP34013890 A JP 34013890A JP 34013890 A JP34013890 A JP 34013890A JP H04207060 A JPH04207060 A JP H04207060A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- substrate
- sealing frame
- thin film
- metal thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000007789 sealing Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 239000000853 adhesive Substances 0.000 claims description 23
- 230000001070 adhesive effect Effects 0.000 claims description 23
- 230000017525 heat dissipation Effects 0.000 abstract description 11
- 239000010408 film Substances 0.000 abstract description 9
- 239000004925 Acrylic resin Substances 0.000 abstract description 4
- 229920000178 Acrylic resin Polymers 0.000 abstract description 4
- 239000007767 bonding agent Substances 0.000 abstract 4
- 238000009413 insulation Methods 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 46
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〔概要〕
放熱機構を備えた半導体装置、特に基板に搭載される素
子がウェハであるウェハスケールメモリモジュールに関
し、
半導体装置内に発生した熱を効率良く外部に放熱するこ
とのできる半導体装置を提供することを目的とし、
半導体素子を搭載するパッケージにおいて、該半導体素
子が搭載される素子搭載基板の素子搭載面の端部周囲に
設けた放熱フィンを兼ねる封止枠と、少な（とも前記素
子搭載基板の素子搭載面の端部周囲に該基板と前記封止
枠の両方に接するように設けた金属薄膜と、前記素子搭
載基板と前記封止枠を接着するように、前記素子搭載基
板及び前記封止枠の前記素子収容部の内部に位置する面
に塗布した接着剤とを有することを特徴とした構成であ
る。[Detailed Description of the Invention] [Summary] To efficiently radiate heat generated within the semiconductor device to the outside regarding a semiconductor device equipped with a heat dissipation mechanism, particularly a wafer scale memory module in which an element mounted on a substrate is a wafer. The present invention aims to provide a semiconductor device in which a semiconductor element is mounted, and a sealing frame that also serves as a heat dissipation fin provided around an end of an element mounting surface of an element mounting board on which the semiconductor element is mounted; a metal thin film provided around the edge of the element mounting surface of the element mounting substrate so as to be in contact with both the substrate and the sealing frame, and bonding the element mounting substrate and the sealing frame; This configuration is characterized by comprising the element mounting substrate and an adhesive applied to a surface of the sealing frame located inside the element housing section.
本発明は半導体装置に関し、
更に詳しく言えば、半導体素子を搭載する半導体パッケ
ージの放熱性を高め、半導体内部に発生する熱を効率良
く外部へ放熱する半導体装置に関する。The present invention relates to a semiconductor device, and more specifically, to a semiconductor device that improves the heat dissipation performance of a semiconductor package in which a semiconductor element is mounted, and efficiently dissipates heat generated inside the semiconductor to the outside.
近年の半導体装置においては、半導体素子の大規模化、
高集積化が進むと共に素子からの発熱量が大幅に増加し
ている。特にウェハスケールメモリモジュールは、ウェ
ハ上に非常に多くの素子が形成されているため発熱量が
大きい。In recent years, in semiconductor devices, the scale of semiconductor elements has increased,
As the degree of integration progresses, the amount of heat generated from elements is increasing significantly. In particular, wafer-scale memory modules generate a large amount of heat because a large number of elements are formed on a wafer.
そのため、特にウェハスケールメモリモジュールを搭載
するＰＫＧにおいては、半導体装置内部で発生した熱を
効率良く外部へ放熱することが望まれている。Therefore, especially in a PKG equipped with a wafer-scale memory module, it is desired to efficiently radiate heat generated inside the semiconductor device to the outside.
第４図は、従来のウェハスケールメモリモジュールを示
す断面図である。FIG. 4 is a cross-sectional view showing a conventional wafer scale memory module.
図中、１はウェハ上に多数のＤＲＡＭを形成させ、ウェ
ハ形状のまま大容量ＤＲＡＭとして機能するウェハメモ
リ、２はガラスエポキシ樹脂からなるウェハ搭載基板、
３はアクリル系樹脂からなる接着剤、４はウェハの各チ
ップと配線層とを結ぶ金属細線であり、パッケージ外部
との接続はコネクタにより接続される。In the figure, 1 is a wafer memory in which a large number of DRAMs are formed on a wafer and functions as a large-capacity DRAM in the wafer shape, 2 is a wafer mounting substrate made of glass epoxy resin,
3 is an adhesive made of acrylic resin, 4 is a thin metal wire connecting each chip of the wafer to the wiring layer, and connection to the outside of the package is made by a connector.
５はアルミニウムからなり放熱フィンを兼ねた封止枠、
６はシリコンラバーよりなる接着剤、７はステンレス製
のキャップをそれぞれ示す。5 is a sealing frame made of aluminum that also serves as a heat dissipation fin;
6 indicates an adhesive made of silicone rubber, and 7 indicates a cap made of stainless steel.
従来のウェハスケールメモリモジュールは次の様なもの
である。Conventional wafer scale memory modules are as follows.
ウェハ搭載基板２上にアクリル系樹脂からなる接着剤３
を介してウェハ１が搭載されている。An adhesive 3 made of acrylic resin is placed on the wafer mounting substrate 2.
The wafer 1 is mounted via the wafer 1.
前記基板２のウェハ１搭載部周囲に予め配線層を形成し
ておき、該ウェハ１の各チップと該配線層とを金属細線
４でボンディングし、前記基板２上面の端部周囲に接着
剤６を塗布して封止枠５が接着されている。A wiring layer is formed in advance around the wafer 1 mounting portion of the substrate 2, each chip of the wafer 1 and the wiring layer are bonded with a thin metal wire 4, and an adhesive 6 is applied around the edge of the upper surface of the substrate 2. The sealing frame 5 is bonded by applying .
なお、該封止枠５と前記基板２との接着強度を高めるた
めに前記封止枠５直下の前記基板２底面からネジ穴を設
は前記基板２と前記封止枠５とをネジ止めしてもよい。In addition, in order to increase the adhesive strength between the sealing frame 5 and the substrate 2, screw holes are provided from the bottom surface of the substrate 2 directly below the sealing frame 5, so that the substrate 2 and the sealing frame 5 are screwed together. It's okay.
封止キャップ７は接着剤６を介して前記封止枠５と接着
した構成を有している。The sealing cap 7 has a structure in which it is adhered to the sealing frame 5 via an adhesive 6.
上記の構成により、前記ウェハスケールメモリモジエー
ル内に生じた熱は、基板２から接着剤６を介して封止枠
５に伝わり外部へ放熱される。With the above configuration, the heat generated in the wafer scale memory module is transmitted from the substrate 2 to the sealing frame 5 via the adhesive 6 and is radiated to the outside.
上記した従来技術で形成されたウェハスケールメモリモ
ジュールでは、ウェハ１内に形成された多数の半導体チ
ップから発生した熱が、金属細線４と基板２上の配線層
を通り、基板２と、放熱フィンを兼ねる封止枠５間の接
着剤６を介して該封止枠５から放熱していた。In the wafer-scale memory module formed using the above-mentioned conventional technology, heat generated from a large number of semiconductor chips formed in the wafer 1 passes through the thin metal wires 4 and the wiring layer on the substrate 2, and then passes through the substrate 2 and the heat dissipation fin. Heat was radiated from the sealing frames 5 through the adhesive 6 between the sealing frames 5, which also served as the sealing frame 5.
しかしながら、接着剤６の熱伝導率は金属に比べ大幅に
劣るために充分な放熱をすることができず、半導体素子
の性質上、温度が上がると次第に素子の特性が悪くなっ
ていき、誤動作などの問題が生じ、信顛性に問題が残っ
ていた。However, the thermal conductivity of the adhesive 6 is significantly lower than that of metals, so it cannot dissipate sufficient heat, and due to the nature of semiconductor devices, as the temperature rises, the characteristics of the device gradually deteriorate, leading to malfunctions and other problems. Problems arose, and problems with credibility remained.
本発明は、このような問題点に鑑み、半導体装置内に発
生した熱を効率良く外部に放熱することのできる半導体
装置を提供することを目的としている。SUMMARY OF THE INVENTION In view of these problems, it is an object of the present invention to provide a semiconductor device that can efficiently radiate heat generated within the semiconductor device to the outside.
本発明では上記目的を達成するために、半導体素子を搭
載するパッケージにおいて、該半導体素子の搭載される
素子搭載基板２の素子搭載面の端部周囲に設けた放熱フ
ィンを兼ねる封止枠５と、少なくとも前記素子搭載基板
２の素子搭載面の端部周囲に該基板２と前記封止枠５の
両方に接するように設けた金属薄膜８と、前記素子搭載
基板２と前記封止枠５を接着するように、前記素子搭載
基板２及び前記封止枠５の前記素子収容部の内部に位置
する面に塗布した接着剤６とを有することを特徴とする
半導体装置を提供する。In order to achieve the above object, in the present invention, in a package on which a semiconductor element is mounted, a sealing frame 5 which also serves as a heat dissipation fin is provided around the edge of the element mounting surface of the element mounting substrate 2 on which the semiconductor element is mounted. , a metal thin film 8 provided at least around the edge of the element mounting surface of the element mounting substrate 2 so as to be in contact with both the substrate 2 and the sealing frame 5; There is provided a semiconductor device characterized in that it has an adhesive 6 applied to the element mounting substrate 2 and the surface of the sealing frame 5 located inside the element accommodating portion so as to adhere to each other.
〔作用］
第１図は、本発明に係るウェハスケールメモリモジュー
ルの原理図を示す。図中、第４図と同じ箇所には同一の
番号を付している。[Operation] FIG. 1 shows a principle diagram of a wafer scale memory module according to the present invention. In the figure, the same parts as in FIG. 4 are given the same numbers.
また、８は銅からなる金属薄膜を示す。Further, 8 indicates a metal thin film made of copper.
ウェハを搭載した基板２上面の端部周囲に銅からなる金
属薄膜８を介し、封止枠５を配置した後、該封止枠５の
ウェハ収容部の内部に位置する面にのみ接着剤６を塗布
することによって、前記ウェハ搭載基板２と前記封止枠
５とを接着する。After placing the sealing frame 5 around the edge of the upper surface of the substrate 2 on which the wafer is mounted, with a metal thin film 8 made of copper interposed therebetween, an adhesive 6 is applied only to the surface of the sealing frame 5 located inside the wafer accommodating part. The wafer mounting substrate 2 and the sealing frame 5 are bonded together by applying .
これにより、前記基板２上に形成された前記金属薄膜８
と前記封止枠５を直接接触させることができる。As a result, the metal thin film 8 formed on the substrate 2
The sealing frame 5 can be brought into direct contact with the sealing frame 5.
従って、従来技術では接着剤６を介して前記封止枠５と
前記基板２を結合して、前記ウェハスケールメモリモジ
ュール内に発生した熱を外部に放熱していたのに比べ、
本願のように熱伝導率の良い前記金属薄膜８を直接に、
封止枠５と前記基板２の間に挟み込むことによって、前
記ウェハスケールメモリモジュール内部から効率良く熱
を該ウェハスケールメモリモジュールの外部へ放熱する
ことができる。Therefore, in contrast to the prior art, in which the sealing frame 5 and the substrate 2 are bonded via an adhesive 6 to radiate the heat generated within the wafer scale memory module to the outside.
As in the present application, the metal thin film 8 having good thermal conductivity is directly applied.
By sandwiching it between the sealing frame 5 and the substrate 2, heat can be efficiently radiated from inside the wafer scale memory module to the outside of the wafer scale memory module.
第２図は、本発明の第１の実施例のウェハスケールメモ
リモジュールを示す断面図である。FIG. 2 is a cross-sectional view showing a wafer scale memory module according to a first embodiment of the present invention.
図中、第１図と同じ箇所には同一の番号を付している。In the figure, the same parts as in FIG. 1 are given the same numbers.
９はポリイミドからなる絶縁膜を示す。9 indicates an insulating film made of polyimide.
基板２上に銅からなり、３５μｍ程度の厚さをもつ金属
薄膜８を全面に形成し、該金属薄膜８表面のウェハ搭載
部に、アクリル系樹脂からなる接着剤３を介してウェハ
１が搭載されている。A metal thin film 8 made of copper and having a thickness of about 35 μm is formed on the entire surface of the substrate 2, and the wafer 1 is mounted on the wafer mounting portion on the surface of the metal thin film 8 via an adhesive 3 made of acrylic resin. has been done.
前記ウェハ搭載部周囲に絶縁膜９が接着剤を介して配置
されていて、その表面に前記ウェハ１と基板２とを接続
する金属細線４のボンディング部が形成されている。An insulating film 9 is disposed around the wafer mounting portion via an adhesive, and a bonding portion of a thin metal wire 4 connecting the wafer 1 and the substrate 2 is formed on the surface of the insulating film 9.
また、前記ボンディング部と基板２に形成された配線層
とは、前記絶縁膜９と前記金属薄膜８に予め形成された
スルーホールにより接続されている。Further, the bonding portion and the wiring layer formed on the substrate 2 are connected through a through hole formed in the insulating film 9 and the metal thin film 8 in advance.
封止枠５は、前記絶縁膜９の外周に配置され、該封止枠
５のウェハ収容部の内部に位置する面にのみ接着剤６を
塗布することによって、前記ウェハ搭載基板２と前記封
止枠５とを接着すると共に、前記基板２上に形成された
前記金属薄膜８と前記封止枠５を直接接触させることが
できる。The sealing frame 5 is disposed around the outer periphery of the insulating film 9, and is bonded to the wafer mounting substrate 2 by applying adhesive 6 only to the surface of the sealing frame 5 located inside the wafer accommodating portion. In addition to adhering the sealing frame 5, the metal thin film 8 formed on the substrate 2 and the sealing frame 5 can be brought into direct contact.
本実施例では、前記金属薄膜８として熱伝導率が良く安
価な銅を用いたが、これに限定されるものではなく、金
、白金などの熱伝導率の良い金属を用いてもよい。In this embodiment, copper, which has good thermal conductivity and is inexpensive, is used as the metal thin film 8, but the present invention is not limited to this, and metals with good thermal conductivity such as gold and platinum may also be used.
なお、前記封止枠５と前記基板２との接着強度を高める
ために封止枠５直下の基板２下面からネジ穴を設は前記
基板２と前記封止枠５をネジ止めしてもよい。Incidentally, in order to increase the adhesive strength between the sealing frame 5 and the substrate 2, screw holes may be provided from the bottom surface of the substrate 2 directly below the sealing frame 5, and the substrate 2 and the sealing frame 5 may be screwed together. .
第３図は、本発明の第２の実施例のウェハスケールメモ
リモジュールを示す断面図である。FIG. 3 is a cross-sectional view showing a wafer scale memory module according to a second embodiment of the present invention.
図中、第１図、第２図と同じ箇所には同一の番号を付し
ている。In the figure, the same parts as in FIGS. 1 and 2 are given the same numbers.
本実施例では、本発明のウェハスケールメモリモジュー
ルをウェハ１が対向するように上下一対にしてシリコン
ラバーよりなる接着剤６により接着したものである。In this embodiment, the wafer scale memory modules of the present invention are arranged in a pair of upper and lower parts with the wafers 1 facing each other and are bonded together using an adhesive 6 made of silicone rubber.
更に、第１の実施例同様に、封止枠５と基板２との接着
強度を高めるために封止枠５直下の基板２下面からネジ
穴を設は前記基板２と前記封止枠５をネジ止めしてもよ
い。Further, as in the first embodiment, in order to increase the adhesive strength between the sealing frame 5 and the substrate 2, screw holes are provided from the bottom surface of the substrate 2 directly below the sealing frame 5. It may be fixed with screws.
また本実施例では、ウェハを搭載したウェハスケールメ
モリモジュールに関して説明したが、これに限定される
ものではなく半導体チップを搭載した半導体装置などに
も適用することができる。Furthermore, although this embodiment has been described with respect to a wafer-scale memory module mounted with a wafer, the present invention is not limited to this, and can be applied to a semiconductor device mounted with a semiconductor chip.
以上説明したように本発明のウェハスケールメモリモジ
ュールによれば、ウェハからの発熱をウェハ搭載基板上
に形成された金属薄膜により、接着剤を介さずに直接に
放熱フィンを兼ねた封止枠に伝えられるため、ウェハス
ケールメモリモジュール内の温度上昇を効率的に抑える
ことができ、高い放熱特性を得ることができる。As explained above, according to the wafer scale memory module of the present invention, heat generated from the wafer is transferred directly to the sealing frame that also serves as a heat dissipation fin, without using an adhesive, by means of a metal thin film formed on the wafer mounting substrate. As a result, temperature rise within the wafer-scale memory module can be effectively suppressed, and high heat dissipation characteristics can be obtained.
従って、ウェハの発熱が原因で起こる誤動作等の発生率
をかなり低く抑えることができ、素子の大規模化、高集
積化に伴う素子の放熱対策に有効である。Therefore, the incidence of malfunctions caused by heat generation in the wafer can be suppressed to a considerably low level, and this is effective as a measure against heat dissipation from devices as devices become larger and more highly integrated.
さらに、ウェハスケールメモリモジュールに限定されず
、半導体チップを搭載した半導体装置の性能向上、耐久
性向上にもたいへん有効である。Furthermore, it is very effective not only for wafer scale memory modules but also for improving the performance and durability of semiconductor devices equipped with semiconductor chips.
第１図は本発明の原理図であり、ウェハスケールメモリ
モジュールを示している。
第２図は本発明の第１の実施例のウェハスケールメモリ
モジュールを示す断面図である。
第３図は本発明の第２の実施例のウェハスケールメモリ
モジュールを示す断面図である。
第４図は従来のウェハスケールメモリモジュールを示す
断面図である。
また、図中１はウェハ、
２はウェハ搭載基板、３は接着剤、
４は金属細線、５は封止枠、６は接着剤、７は封止キャ
ンプ、８は金属薄膜、
９は絶縁膜
をそれぞれ示す。
本宛唱ｎ勺月＼スケールヌ乞り七ジュールｎ尻理図隼
１ 凹
ｉ＞妃帆ハ手１ｒ光例乞示４ウユハスケールメ七り七シ
゛ニールＯ餌［ｆｌ医
賂 ２ ｍFIG. 1 is a principle diagram of the present invention, showing a wafer scale memory module. FIG. 2 is a sectional view showing a wafer scale memory module according to a first embodiment of the present invention. FIG. 3 is a sectional view showing a wafer scale memory module according to a second embodiment of the present invention. FIG. 4 is a sectional view showing a conventional wafer scale memory module. In addition, in the figure, 1 is a wafer, 2 is a wafer mounting substrate, 3 is an adhesive, 4 is a thin metal wire, 5 is a sealing frame, 6 is an adhesive, 7 is a sealing camp, 8 is a metal thin film, 9 is an insulating film are shown respectively. Singing to the book n Tsuzuki \ scale n beggars seven joules n Shiri Zu Hayabusa
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Claims (2)
、 該半導体素子（１）が搭載される素子搭載基板（２）の
素子搭載面の端部周囲に設けた放熱フィンを兼ねる封止
枠（５）と、 少なくとも前記素子搭載基板（２）の素子搭載面の端部
周囲に該基板（２）と前記封止枠（５）に挟まれるよう
に設けた金属薄膜（８）と、 前記素子搭載基板（２）と前記封止枠（５）を接着する
ように、前記素子搭載基板（２）及び前記封止枠（５）
の前記素子（１）収容部の内部に位置する面に塗布した
接着剤（６）とを有することを特徴とする半導体装置。(1) In a package on which a semiconductor element (1) is mounted, a sealing frame (5 ), a metal thin film (8) provided at least around the edge of the element mounting surface of the element mounting substrate (2) so as to be sandwiched between the substrate (2) and the sealing frame (5), and the element mounting surface. The element mounting substrate (2) and the sealing frame (5) are bonded together so that the substrate (2) and the sealing frame (5) are bonded together.
and an adhesive (6) applied to a surface of the element (1) located inside the accommodating portion.
記金属薄膜（８）を設けたことを特徴とする請求項（１
）記載の半導体装置。(2) Claim (1) characterized in that the metal thin film (8) is provided on the entire surface of the element mounting surface of the element mounting substrate (2).
).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34013890A JPH04207060A (en) | 1990-11-30 | 1990-11-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34013890A JPH04207060A (en) | 1990-11-30 | 1990-11-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04207060A true JPH04207060A (en) | 1992-07-29 |
Family
ID=18334092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34013890A Pending JPH04207060A (en) | 1990-11-30 | 1990-11-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04207060A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001073843A1 (en) * | 2000-03-29 | 2001-10-04 | Rohm Co., Ltd. | Semiconductor device |
| JP2013507760A (en) * | 2009-10-07 | 2013-03-04 | バレオ・エチユード・エレクトロニク | Power module for automobile |
| JP2013243341A (en) * | 2012-04-27 | 2013-12-05 | Canon Inc | Electronic component and electronic apparatus |
-
1990
- 1990-11-30 JP JP34013890A patent/JPH04207060A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001073843A1 (en) * | 2000-03-29 | 2001-10-04 | Rohm Co., Ltd. | Semiconductor device |
| US6815829B2 (en) | 2000-03-29 | 2004-11-09 | Rohm Co., Ltd. | Semiconductor device with compact package |
| KR100736000B1 (en) * | 2000-03-29 | 2007-07-06 | 로무 가부시키가이샤 | Semiconductor device |
| JP2013507760A (en) * | 2009-10-07 | 2013-03-04 | バレオ・エチユード・エレクトロニク | Power module for automobile |
| JP2013243341A (en) * | 2012-04-27 | 2013-12-05 | Canon Inc | Electronic component and electronic apparatus |
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