JPH04206565A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a semiconductor integrated circuit device to be enhanced in operation speed and to be lessened in number of processes by a method wherein complementary MISFETs, an NPN bipolar transistor, and a PNP bipolar transistor are formed on the same semiconductor substrate, where specific electrodes of them are formed of specific laminated layers. CONSTITUTION:A first process where an electrode connected to the source region and the drain region of a first conductivity type MISFET Qp, the gate electrode of a second conductivity type MISFET Qn, the emitter lead-out electrode of a first bipolar transistor(Tr), and the base lead-out electrode of a second bipolar Tr are formed of a first laminated film 24 composed of a first conductivity type silicon film and a high melting point metal film or a high melting point metal silicide laminated thereon and a second process in which the electrodes of the above MISFETs and the Trs where the first ones are replaced with the second ones and vice versa are formed of a second laminated film 28 composed of a second conductivity type silicon film and the above metal film formed thereon are provided. These metal films are lower than a polycrystalline silicon film in resistance, so that a semiconductor device of this design can operate at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a complementary MI
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device in which SFETs, npn bipolar transistors, and pnp bipolar transistors are provided on the same semiconductor substrate.

[Conventional technology]

A semiconductor integrated circuit device has been proposed that includes a complementary MISFET, an npn bipolar transistor, and a pnp bipolar transistor on the same semiconductor substrate.

Regarding this type of semiconductor integrated circuit device, for example, IEDM 88, Transactions of
Technical, Digest (1988), pp. 760-763 (I E DM 88 Transac
tion of Technical Digest
pp760-763 (1988)).

In the semiconductor integrated circuit device described in the above document, the gate electrode of the p-channel MISFET, the electrode connected to the source region and the drain region, the base lead electrode of the npn bipolar transistor, and the emitter lead electrode of the pnp bipolar transistor. Each of them is composed of a polycrystalline silicon film into which n-type impurities are introduced. Also,
The gate electrode of the n-channel MISFET, the electrode connected to the source region and the drain region, the emitter extraction @m of the npn bipolar transistor, and the base extraction electrode of the pnp bipolar transistor are made of polycrystalline silicon doped with n-type impurities. It is composed of a membrane.

[Problem to be solved by the invention]

However, as a result of studying the above-mentioned prior art, the inventor found the following problems.

In the semiconductor integrated circuit device, each of the gate electrode of the complementary tIsFET, the electrode connected to the source region and the drain region, the emitter extraction electrode and the base extraction electrode of the npn bipolar transistor and the pnp bipolar transistor has a high resistance value. Since it is composed of a polycrystalline silicon film, there is a problem in that the operating speed of the semiconductor integrated circuit device cannot be increased.

To solve this problem, for example, the polycrystalline silicon film can be constructed as a multilayer film in which a refractory metal silicide film, such as a tungsten silicide (WSi) film, is laminated on a polycrystalline silicon film. It is possible to increase the operating speed.

However, when a polycrystalline silicon film is formed, n-type and p-type impurities are introduced into the polycrystalline silicon film, and a high melting point metal silicide film is formed and annealed on the polycrystalline silicon film. Since the n-type impurity introduced into the polycrystalline silicon film diffuses through the high melting point metal silicide film, a pn junction is formed in the portion of the polycrystalline silicon film where the n-type impurity is introduced. There's a problem. In order to avoid this problem, it is necessary to introduce n-type impurities after forming a polycrystalline silicon film, form a high melting point metal silicide film on this polycrystalline silicon film, annealing it, and form the polycrystalline silicon film. After that, it is necessary to separately perform the steps of introducing n-type impurities, forming a refractory metal silicide film on this polycrystalline silicon film, and annealing. Therefore, in the case of the semiconductor integrated circuit device, at least three steps are required to form a laminated film in which a high-melting point metal silicide film is laminated on the polycrystalline silicon film, which reduces the number of manufacturing steps. The problem was that it was not possible to

An object of the present invention is to provide a technology that can increase the speed in a method of manufacturing a semiconductor integrated circuit device in which complementary MISFET-npn bipolar transistors and pnp bipolar transistors are provided on the same semiconductor substrate. It is in.

Another object of the present invention is to provide a technique capable of speeding up the manufacturing method of the semiconductor integrated circuit device and reducing the number of manufacturing steps.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) First conductivity type and second conductivity type MISFET, first
an emitter region of a conductivity type, a base region of a second conductivity type, a first conductivity type emitter region;
A first bipolar transistor consisting of a collector region of each conductivity type, and a second bipolar transistor consisting of an emitter region of a second conductivity type, a base region of a first conductivity type, and a collector region of a second conductivity type, respectively. In a method of manufacturing a semiconductor integrated circuit device including bipolar transistors on the same semiconductor substrate, an ill pole connected to a source region and a train region of the first conductivity type MISFET, and a gate electrode of the second conductivity type MISFET. , the emitter lead-out electrode of the first bipolar transistor and the base lead-out electrode of the second bipolar transistor are each covered with a silicon film of the first conductivity type and a refractory metal film or a refractory metal silicide film. A step of forming a first stacked film, a gate electrode of the first conductivity type MISFET, an electrode connected to the source region and a drain region of the second conductivity type MISFET, and the first bipolar (helangister) The base extraction electrode of the second bipolar transistor and the emitter extraction electrode of the second bipolar transistor are each formed by a second laminated film in which a silicon film of a second conductivity type, a high melting point metal film or a high melting point metal silicide film are laminated. and a step of forming.

[For production]

A laminated film in which a refractory metal film or a refractory metal silicide film is laminated on the polycrystalline silicon film of the first conductivity type or the second conductivity type has a lower resistance value than the polycrystalline silicon film. ．． The current and drive capabilities of the MISFETs of the conductivity type and the second conductivity R type are improved, and the delay due to the resistance of the gate electrode portion is reduced. As a result, MI of the first conductivity type and the second conductivity type
The operating speed of the SFET can be increased.

Similarly, since the respective resistance values of the emitter lead-out electrode 7 and the base lead-out electrode of the first and second bipolar transistors are reduced compared to a single layer polycrystalline silicon film, these bipolar transistors The base resistance of the transistor is reduced and the cut-off frequency is improved. Therefore, the operating speed of the first and second bipolar transistors can be increased.

Thus, according to the above-mentioned means, the first conductivity type and the second conductivity type
In a method of manufacturing a semiconductor integrated circuit device including a conductive type MISFET and first and second bipolar transistors, the operating speed can be increased.

At the same time, the gate electrodes of the MISFETs of the first conductivity type and the second conductivity type, the electrodes connected to the source region and the drain region, and the first and second Since the emitter lead-out electrode and the base lead-out electrode of the second bipolar transistor are formed respectively, the number of manufacturing steps for the semiconductor integrated circuit device can be reduced.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

It should be noted that throughout the explanation of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

The configuration of the semiconductor integrated circuit device according to the embodiment of the present invention is described in the first section.
This will be explained using figures (cross-sectional views of main parts).

As shown in FIG. 1, the semiconductor integrated circuit device of this embodiment includes a P-channel MISFETQp, an n-channel MISFE
TQn, npn bipolar transistor Tr1, pnp
Five bipolar transistors Tr2 are provided on the same semiconductor substrate 50, respectively. This semiconductor substrate 50 has p-
It is formed by growing an epitaxial layer 10 on a type semiconductor substrate 1. This semiconductor substrate 50 is made of, for example, single crystal silicon. The p'' type semiconductor substrate 1 is provided with a buried n type semiconductor region 6, a P type semiconductor region 9, and an n type semiconductor region 3 for isolation between elements. is, n
2 and a p-type well region 13 are provided.

Each element is mainly insulated by an inter-element isolation insulating film 15. This inter-element isolation insulating film] 5 is made of, for example, a silicon oxide film.

The p-channel MISFET QP is surrounded by an element isolation insulating film 15 and is provided on the main surface of the n'' type well region 12.
E T Q p is mainly composed of a gate insulating film 27, a gate electrode 28, and a p' type semiconductor region 30 forming a source region and a drain region.

The gate insulating film 27 is provided on the main surface of the square well region 12 . This gate insulating film 27 is made of, for example, a silicon oxide film.

The gate electrode 28 is provided on the gate insulating film 22. This gate electrode 28 is made of, for example, a high melting point metal silicide film 28B on a polycrystalline silicon 111128A.
For example, it is composed of a laminated film of laminated tungsten silicide (WSi) films.

Further, an n-type impurity is introduced into the polycrystalline silicon@281. Therefore, the conductivity type of this polycrystalline silicon film 28A is n type.

Furthermore, a p-type semiconductor region 20 is provided in the channel region of this p-channel MISFETQp. By providing this p-type semiconductor region 20, this p-channel M
ISFETQp is a buried channel type.

An electrode 24 is connected to the p' type semiconductor region 3o constituting the source region and drain region. This electrode 24, like the gate electrode 28, is made of a polycrystalline silicon film 2.
It is composed of a laminated film in which a high melting point metal silicide film 24B is laminated on 4A.

A p-type impurity is introduced into the polycrystalline silicon film 24A. Therefore, the conductivity type of this electrode 24 is p-type.

An insulating film 25 is provided on this electrode 24. This absolute #ll! 25 is made of, for example, a silicon oxide film. Additionally, a sidewall spacer 26 is provided on the sidewall of the electrode 24. This sidewall spacer 26 is made of, for example, a silicon oxide film. The electrode 24 and the gate electrode 28 are insulated by the sidewall spacer 26 and the insulating film 25, respectively.

On one side of the electrode 24, an insulation@25 and an interlayer insulation film 3 are provided.
Wiring 34 is connected through the connection hole provided in 2. The interlayer insulating film 32 is, for example, B PSG
(Baron Phospho 5ilicate G
lass) membrane. The wiring 34 is made of, for example, an aluminum film.

The n-channel M I S F E T Q n is inter-element layer insulation! 115 and is provided on the main surface of the p-type well region 13. This n-channel MISFETQn mainly has gate #! l# membrane 22,
It is composed of a gate electrode 24, and n° type semiconductor regions 29 that constitute a source region and a drain region.

The gate insulating film 22 is provided on the main surface of the p-type well region 13. This gate insulating film 22 is made of, for example, a silicon oxide film.

The gate electrode 24 is provided on the gate insulating film 22. This gate electrode 24 is connected to the p-channel M
It has the same configuration as the electrode 24 of ISFETQP.

An insulating film 25 is provided on this gate electrode 24 . Furthermore, sidewall spacers 26 are provided on the sidewalls of this gate electrode 24. Electrode 2 to be described later
8 and this gate electrode 24, these insulating films 25
and are insulated by sidewall spacers 26.

Also, this n-channel M I S F E T Q n
An n-type semiconductor region 19 is provided in the channel region of. By providing this n-type semiconductor region 19, this n-channel MISFETQn is of a buried channel type.

An electrode 28 is connected to the i'-type semiconductor region 29 constituting the source region and drain region. This electrode 28 has the same structure as the gate electrode 28 of the p-channel MISFETQp. Further, this electrode 28 is connected to a wire through a connection hole provided in the glabella insulating film 32.
134 is connected.

This bipolar transistor Tri mainly consists of an n-type semiconductor region 31 constituting an emitter region, a p-type semiconductor region 20 constituting a base region, and an n-type semiconductor region 20 constituting a collector region.
Each of the mold well regions 12 is made up of a mold well region 12.

In the n-type semiconductor region 31 constituting the emitter region,
An emitter extraction electrode 28 is connected. This emitter extraction electrode 28 is connected to the p-channel MISFET.
Gate electrode of Qp, the n-channel MI 5FETQn
The structure is similar to that of the electrode 28. Further, a wiring 34 is connected to this emitter lead-out electrode 28 through a connection hole provided in a one-layer insulating film 32.

The p-type semiconductor region 20 constituting the base region contains P.
The ゛-type semiconductor region 30 is connected and appears. In other words, the n-type semiconductor region 2o constitutes an intrinsic base region, and the second p-type semiconductor region 2o constitutes an intrinsic base region.
The ゛-type semiconductor region 30 constitutes a graft base region.

This p-type semiconductor region 3o has a base extraction electrode 2.
4 are connected.

This base extraction electrode 24 is connected to the n-channel MIS.
Electrode 24 of FETQp, the n-channel MrsFETQ
It has the same structure as each of the n gate electrodes 24.

There is insulation on this base extraction electrode 24! 25 are provided. Furthermore, a side wall spacer 26 is provided on the side wall of the base extraction electrode 24. The emitter extraction electrode 28 and the base extraction electrode 24 are insulated by the insulating film 25 and the sidewall spacer 26. Further, on one side of this base extraction electrode 24, an insulating film 25 and an interlayer insulation @@3 are provided.
Wiring 34 is connected through the connection hole provided in 2.

A buried n-type semiconductor region 6 is provided below the n-type well region ]-2 constituting the collector region. This n° type semiconductor region 6 reduces the series resistance of the collector region. Furthermore, an n° type semiconductor region 17 for raising the collector potential is connected to this n° type semiconductor region 6. This n-type semiconductor region 17 has an interlayer insulating film 3.
Wiring 34 is connected through the connection hole provided in 2.

The pnp bipolar transistor Tr2 is surrounded by an element isolation mill film 15 and is provided on the main surface of the p-type well region 13. This bipolar transistor Tr2 mainly consists of P constituting an emitter region.
type semiconductor region 32, an n-type semiconductor region 19 forming a base region, and a p'' type well region 13 forming a collector region.
It is composed of each of the following.

In the n-type semiconductor region 33 constituting the emitter region,
An emitter extraction electrode 24 is connected. This emitter extraction electrode 24 is connected to the n-channel MISFET.
QP electrode 24, the gate electrode 24 of the n-channel MISFET Qn, the npn bipolar transistor Tr
It has the same structure as each of the base extraction electrodes 24 of No.1.

An insulator 1i film 25 is provided on this emitter extraction electrode 247. In addition, this emitter extraction electrode 24
A side wall spacer 26 is provided on the side wall portion of the frame. The emitter lead-out electrode 24 and the base lead-out electrode 28, which will be described later, are insulated by these insulating films 25 and sidewall spacers 26. Also,
A wiring 34 is connected to this emitter lead-out electrode 24 through a connection hole provided in an insulating film 25 and an interlayer insulating film 32 in a region not shown.

In the n-type semiconductor region 19 constituting the base region, n
A type semiconductor region 29 is connected. In other words, the n
The type semiconductor region 19 constitutes an intrinsic base region, and this n°
The type semiconductor region 29 constitutes a graft base region. In this n° type semiconductor region 29, a base extraction electrode 28 is provided.
is connected.

This base extraction electrode 28 is connected to the P-channel MIS.
Goo 1-electrode 28 of FETQp, the n-channel MIS
The structure is similar to that of the electrode 28 of the FETQn and the emitter extraction electrode 28 of the npn bipolar transistor Trl. In addition, this base extraction electrode 28
A wiring 34 is connected to one side of the interlayer insulating film 32 through a connection hole provided in the interlayer insulating film 32 .

p” type well region forming the collector region].

3, a buried p° type semiconductor region 9 is provided. This p° type semiconductor region 9 reduces the series resistance of the collector region. Note that, around this p° type semiconductor region 9, this p° type semiconductor region 9 and the p− type semiconductor substrate 1 are formed.
An n-type semiconductor region 3 is provided to form an M edge between the two. Furthermore, a p° type semiconductor region 18 for collector potential E is connected to the p type semiconductor region 9. A wiring 34 is connected to this p° type semiconductor region J8 through a connection hole provided in an interlayer insulating film 32.

Note that the pnp bipolar transistor Tr2 requires an IIA#h region (n-type semiconductor region) 3 when used for general purposes, but this pnp bipolar IN transistor Tr2 is limited to an emitter follower. In some cases, a short circuit may occur between the p'-type semiconductor region 9 and the p-type half-substrate 1. Therefore, in this case, the n-type semiconductor region 3 and the piborate transistor Tr 1 ,
Semiconductor regions 9, 13, 12 that connect Mil& between T r 2
becomes unnecessary.

As explained above, according to the configuration of this embodiment, the p
Since the electrode 24 of the channel MISFET QP is formed of a multilayer film in which a high melting point metal silicide film 24B is stacked on a p-type polycrystalline silicon film 24A, the resistance value of the electrode 24 is higher than that of a single layer of polycrystalline silicon film. Therefore, the current drive capability of p-channel MISFETQp can be improved. Furthermore, since the gate electrode 28 of the p-channel MISFET QP is formed of a multilayer film in which a high-melting point metal silicide film 28B is stacked on an n-type polycrystalline silicon 1l128A, delays due to capacitance and resistance of the gate portion are reduced. , the operating speed of a p-channel MISFET with a long gate width can be increased.

Furthermore, since the electrode 28 of the n-channel M I S F E T Q n is formed of a laminated film in which a refractory metal silicide film 28B is laminated on an n-type polycrystalline silicon film 28A, the resistance value of the electrode 28 is Since it is lower than that of a single-layer polycrystalline silicon film, the current drive capability of the n-channel MISFETQn can be improved.

Furthermore, by forming the gate electrode 24 of the n-channel M r S F E T Q n with a laminated film in which a high melting point metal silicide film 24B is laminated on a p-type polycrystalline silicon film 24A, the capacitance of the gate portion and Resistor delays are reduced. Furthermore, by making this n-channel MISFETQn a buried channel, element deterioration due to hot carriers can be reduced even when the channel length is reduced.

In addition, the base resistance (rbb') is reduced by forming the base extraction electrode 24 of the npn bipolar transistor Tri with a laminated film in which a high melting point metal silicide film 24B is laminated on a p-type polycrystalline silicon film 24A. Therefore, the cutoff frequency (fT) can be increased.

Furthermore, the base resistance (rbb') is reduced by forming the base extraction electrode 28 of the pnp bipolar transistor Tr2 with a laminated film in which a high melting point metal silicide film 29B is laminated on the p-type polycrystalline silicon film 24A. be able to.

In addition, the emitter lead-out electrode 24 of the pnp bipolar transistor Tr2 is formed of a laminated film in which a high melting point metal silicide film 24B is laminated on a p-type polycrystalline silicon film 24A, so that the p-type semiconductor region constituting the emitter region 32 can be formed by impurity diffusion from this emitter extraction electrode 24, so the emitter junction can be made shallow. Thereby, the cutoff frequency (ft) of the pnp bipolar transistor T r 2 can be increased.

In addition, by providing on the inter-element isolation insulating film 15 the positions where the base extraction electrodes 24 and 28 of the npn bipolar transistor Tri and the pnp bipolar transistor Tr2 are connected to the wiring 34, the base region and the collector region can be connected to each other. The collector capacitance can be reduced because the junction area can be reduced.

As described above, according to the configuration of this embodiment, complementary type M I
S F E T Q P * Q n -n P In a semiconductor integrated circuit device including each of the n bipolar transistor Tri and the pnp bipolar transistor Tr2 on the same semiconductor substrate 50, the operating speed can be increased.

Next, the method for manufacturing the semiconductor integrated circuit device of this embodiment will be explained using FIGS. 2 to 9 (cross-sectional views of main parts shown for each manufacturing process).

First, a silicon oxide film 2 is formed on the main surface of a p-type semiconductor substrate 1. Thereafter, this silicon oxide film 2 is patterned using photolithography technology, and the n-type semiconductor region (
3) Form an opening in the formation region.

Next, an n-type impurity is introduced into the main surface of the p-type semiconductor substrate 1 using the silicon oxide film 2 as a mask to form an n-type semiconductor region 3 as shown in FIG.

Next, the silicon oxide film 2 is removed. After this, the p-
A silicon nitride film 5 is formed on the main surface of the semiconductor substrate 1 .

Thereafter, this silicon nitride film 5 is patterned using a photolithography technique to form an opening []@* in a region where a buried n° type semiconductor region (6) is to be formed.

Next, an n-type impurity is introduced into the main surface of the p-type semiconductor substrate 1 using the silicon nitride film 5 as a mask.

As shown in FIG. 3, a go-type semiconductor region 6 is formed.

Next, the silicon nitride III! A silicon oxide film 8 is formed by thermal oxidation using 5 as an oxidation-resistant mask. After this, the silicon nitride film 5 is removed.

Next, the p-type semiconductor substrate 1. Using the silicon oxide film 8 as a mask, an n-type impurity is introduced into the main surface of the silicon oxide film 8 to form a buried P' type semiconductor region 9, as shown in FIG. After that, the silicon oxide film 8 is removed.

Next, an epitaxial layer]0 is formed on the main surface of the p" type semiconductor substrate. Thereafter, an n-type well region 12 is formed using the silicon nitride film 5 as a mask, and the silicon nitride layer Silicon oxide film 8 formed using film 5 as an oxidation-resistant mask
P-type well region] and 3 are formed using the mask as a mask. Thereafter, by selective oxidation, the inter-element isolation insulating film 15 is
form. Through the steps up to this point, a substrate on which elements are to be formed is formed. Hereinafter, the substrate that has undergone the steps up to this point will be referred to as a semiconductor substrate 50.

Next, in the formation region of the npn bipolar transistor Tri, n-type impurities are introduced into the main surface of the n-type well region 12 to form an n-type semiconductor region 17 for raising the collector potential. Thereafter, in the formation region of the pnp bipolar transistor Tr2, n-type impurities are similarly introduced into the main surface of the p'' type well region]3, as shown in FIG.

A P° type semiconductor region 18 for raising the collector potential is formed.

Next, in the formation of the n-channel MISFETQn-pnp bipolar transistor Tr2.

An n-type impurity 19 is selectively introduced into the main surface of the p"-type well region 13. After that, similarly, the p-channel MIS
P-type impurity 20 is selectively introduced into the main surface of the n-type well region 12 in the formation region of FETQp and npn bipolar transistor Tri.

Next, thermal oxidation is performed as shown in FIG.

A gate insulating film 22 is formed on the main surface of the semiconductor substrate 50 .

Next, the glue insulating film 22 is removed in the region excluding the region where the n-channel MFTQn is formed.

Next, on the main surface of the semiconductor substrate 50, a layer of polycrystalline silicon 1l is placed.
Form l124A. After this, this polycrystalline silicon film 24
An n-type impurity is introduced into A.

Next, a high melting point metal silicide film 24B is formed on the polycrystalline silicon 11124A. Thereafter, a silicon oxide film 25 of, for example, C
Formed by VD method. After that, annealing is performed to anneal the n-type impurity introduced into the polycrystalline silicon film 24A, thereby improving the film quality of the high-melting point metal silicide film 24B, and to remove the introduced n-type impurity]9 and n-type Impurity 2
Activate 0.

Next, the silicon oxide film 2 is formed using photolithography technology.
5. High melting point metal silicide film 24B, polycrystalline silicon film 24
Each of A is patterned, as shown in FIG.
The electric current [i 24. .

The gate electrode 11i24 of the n-channel MISFETQn, the base lead-out electrode 24 of the npn bipolar transistor Tri, and the emitter lead-out mold 4]1i24 of the pnp bipolar transistor Tr2 are formed.

Next, a silicon oxide film is deposited on the main surface of the semiconductor substrate 50. Thereafter, this silicon oxide film is etched by an amount corresponding to the thickness of the deposited film to form sidewall spacers 26. After this, n-type impurities are selectively added to the formation regions of the source region and drain region (29) of the n-channel MISFETQn, the emitter region (31) of the npn bipolar transistor Trl, and the graft base region (29) of the pnp bipolar transistor Tr2. It may also be introduced by ion implantation.

Next, the main surface of the semiconductor substrate 50 is thermally oxidized to form a gate insulating film 27. After this, as shown in Figure 8,
The gate insulating film 27 is removed in a region other than the formation region of the n-channel MISFETQn.

Next, a polycrystalline silicon film 2 is formed on the main surface of the semiconductor substrate 50.
Form 8A. After this, on this polycrystalline silicon film 28A,
Introduce n-type impurities.

Next, a high melting point metal silicide film 28B is formed on the polycrystalline silicon film 28A. After this, annealing is performed,
While annealing the impurities introduced into the polycrystalline silicon film 28A, the high melting point metal silicide film 28B
Improves film quality.

Next, the high melting point metal silicide film 28B and the polycrystalline silicon film 28A are each patterned using photolithography, as shown in FIG. n-channel MIS
Electrode 28 connected to the source region and drain region of FETQn, emitter extraction electrode 28 of npn bipolar transistor Tri, pnp bipolar transistor T
Each of the base extraction electrodes 28 of r2 is formed.

Next, on the main surface of the semiconductor substrate 50, a glabella insulating film 32 is formed.
form. This interlayer insulating film 32 is made of, for example, BPSG.
Formed by a membrane. Thereafter, this interlayer [11 film 32] is reflowed. In this reflow process, the electrode 24
The n-type impurities and the n-type impurities introduced into the p-type semiconductor regions 30 and 28 diffuse into the main surface of the semiconductor substrate 50, and form the p-type semiconductor regions 30 and n-type semiconductor regions forming the source and drain regions of the p-channel MISFET QP, respectively. Channel MISFE
An n-type semiconductor region 29 that constitutes the source region and drain region of TQn, and a p-type semiconductor region 30 that constitutes the graft base region of the npn bipolar transistor Tri.
and an n-type semiconductor region 31. which constitutes an emitter region. pnp
An n° type semiconductor region 29 constituting a graft base region of bipolar transistor Tr2 and a p type semiconductor region 32 constituting an emitter region are formed. After that, connection holes are formed in this interlayer insulating film.

Next, an aluminum film is formed on the main surface of the semiconductor substrate 50. Thereafter, this aluminum film is patterned using photolithography technology to form the wiring 34, and a surface protection film (not shown) is further formed on the semiconductor substrate 50 including the wiring 134. The semiconductor integrated circuit device of this embodiment shown in FIG. 1 is completed.

As can be seen from the above description, according to the manufacturing method of the present example, the first laminated film (24) and the second laminated film (24)
8), electrodes (24, 28) connected to the gate electrodes (28, 24) and the source and drain regions of the p-channel MISFETQp and n-channel MISFETQn, respectively.
), as well as npn bipolar transistors Tri and pn
P bipolar transistor, emitter extraction electrode (28, 24) and base extraction electrode (24, 2) of Tr2
8), complementary MISFET
, the number of manufacturing steps can be reduced in a semiconductor integrated circuit device having an npn bipolar transistor and a pnp bipolar transistor.

Furthermore, at the same time, the operating speed of the semiconductor integrated circuit device can be increased, and the number of manufacturing steps can be reduced.

The five present inventions have been specifically explained based on the examples above, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in this embodiment, an example was shown in which the npn bipolar transistor Tri and the pnp bipolar transistor Tr2 are insulated from each other and each is used alone, but the present invention provides the bipolar transistor Tri,
It is also possible to insulate each of the Tr2s from each other and use them only as emitter followers. In this case, a buried p-type semiconductor region 9 and a p-type well region 4 are provided between the pnp bipolar transistor Tr2 and other elements, and an insulating M region and an n-type semiconductor region 3 are provided. becomes unnecessary.

Furthermore, the gate electrode 2 of the p-channel MISFETQp
The conductivity type of 4 is set to n type, and this p channel MISFETQ
P can also be of surface channel type. In this case, after the step of forming the gate electrode 24, the source region and the drain region may be formed by ion implantation.

Similarly, the conductivity type of the gate electrode 28 of the n-channel MISFETQn is set to p type, and this n-channel MISFET
FETQn can also be of the surface channel type. In this case, after the step of forming the gate electrode 28, the source region and drain region may be formed by ion implantation.

Further, the first laminated film (24) and the second laminated film (28)
) can also be reversed.

〔Effect of the invention〕

To briefly explain the effects obtained by typical inventions disclosed in this application, manufacturing of a semiconductor integrated circuit device equipped with each of a complementary MISFET, a pnp bipolar transistor, and an npn bipolar transistor is as follows. In this method, the operating speed can be increased.

In the method for manufacturing a semiconductor integrated circuit device, it is possible to increase the operating speed and reduce the number of manufacturing steps.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention. FIGS. 2 to 9 are sectional views of essential parts showing each manufacturing process of the semiconductor integrated circuit device. In the figure, 1... p° type semiconductor substrate, 3.19... n type semiconductor region, 6, 17, 29... n° type semiconductor region, 9
゜18.30... p type semiconductor region, 12... square well region, 13... p- type well region, 15...
Inter-element isolation insulating film, 22, 27... gate insulation film, 2
4A, 28A...polycrystalline silicon film, 24B, 28B...
・High melting focus "group silicide film, 24.28... laminated film.

Claims (1)

[Claims] 1. A first bipolar transistor consisting of a MISFET of a first conductivity type and a second conductivity type, an emitter region of a first conductivity type, a base region of a second conductivity type, and a collector region of a first conductivity type, and an emitter region of a second conductivity type;
In the method of manufacturing a semiconductor integrated circuit device including second bipolar transistors each comprising a base region of a first conductivity type and a collector region of a second conductivity type on the same semiconductor substrate, the first conductivity type an electrode connected to the source region and drain region of the MISFET, a gate electrode of the second conductivity type MISFET, an emitter lead-out electrode of the first bipolar transistor, and a base lead-out electrode of the second bipolar transistor, respectively. , a step of forming a first stacked film in which a high melting point metal film or a high melting point silicide film is stacked on a silicon film of a first conductivity type; a gate electrode of the MISFET of the first conductivity type; MI of
Each of the electrodes connected to the source region and drain region of the SFET, the base extraction electrode of the first bipolar transistor, and the emitter extraction electrode of the second bipolar transistor is formed on a silicon film of the second conductivity type. A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming a second laminated film in which a melting point metal film or a high melting point silicided metal film is laminated.