JPH04205875A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To appropriately adjust the operating timing of a sense amplifier after a word line rises in each array so as to improve the soft error resisting property of a semiconductor storage device by providing a dummy word line which is necessarily selected in each array and using the dummy word lines as the control signals of a sense amplifier drive circuit. CONSTITUTION:When the main clock, the inverse of RAS, of a DRAM becomes 'low' active, the basic signal RX of a word line becomes 'high'. When the signal RX becomes the high level, word lines WL1-WL4 corresponding to external addresses simultaneously rise. In addition, dummy word lines DWL1-DWL4 provided in each array also simultaneously rise. When the word lines WL1-WL4 rise, the data of each memory cell are read out onto each bit line, but the simultaneously risen dummy word lines DWL1-DWL4 become the control signals of a sense amplifier circuit 1. Therefore, the operating timing of a sense amplifier is appropriately adjusted after the word lines rise in each array and the soft error resisting property can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device such as a DRAM, and relates to a drive method for a sense amplifier.

[Conventional technology]

Generally, in a semiconductor memory device such as a DRAM, one word line is provided for each row of memory cells in a memory cell array arranged in a matrix, and two word lines are provided for each column of memory cells. A bit line is provided.

In addition, the above memory cell array is divided into several parts,
At the same time, multiple word lines are often selected.

FIG. 3 is a block diagram showing a part of a general semiconductor memory device.

In the figure, (1) is a sense drive circuit, which is controlled by (2), an output signal φ, of the WL simulator.

The WL in each array becomes "High" after the external clock RAS becomes active, and the basic signal of this WL is the RX generation circuit (3). The output signal RX of this RX generation circuit is input to all the Row Decoders, and WL of the address equivalent to the external address is selected. The aforementioned WL emulator is controlled by the output RXD of this RX generation circuit. This WL simulator is configured to have the same capacitance and resistance as the word line in the array, that is, to have a value close to the same time constant, and the period for driving the sense amplifier after the word line rises. This is to determine.

Now, as explained at the beginning, it is assumed that a plurality of WLs are selected at the same time. That is, WL in the figure, ~
It is assumed that four of WL and WL are selected at the same time.

The operation in this case will be explained using the timing chart of FIG.

First, the main clock of DRAM, RA100 or “R”
ow” becomes active, the basic signal RX of WL rises, and WL1 to WL4 according to the external address rise simultaneously.

Each word line usually has a certain time constant, so Row
If it is far from the decoder side, it will take a certain amount of time for it to start up completely. That is, it takes time for the word line to rise and transmit the potential of the memory cell onto the bit line.

At this time, if the sense amplifier is operated before a sufficient potential is transmitted to the human line, there is a sufficiently high possibility that it will malfunction. At this point, the aforementioned WL simulator waits for WL to rise before driving the sense amplifier.

This is the control signal for φ.

By the way, in recent years, with the increase in capacity, the chip area has also increased.
Due to the layout of the RAGenWL simulator and the like, it has become quite difficult to adjust the appropriate sense amplifier drive timing. That is, in FIG. 3, RX, RXD, φ
, etc. can no longer be ignored, and the sense amplifier drive timing must be matched to the array whose word line rise is delayed the most among each array.

That is, there are arrays in which the sense amplifier operates with a considerable delay after the word line rises (after the memory cell data is transmitted onto the bit line). In such a case, a problem arises in that the period in which the bit line is in a floating state with a minute potential remaining there is long (as a result, the resistance to soft errors caused by alpha rays is also weakened).

[Invention or problem to be solved]

Conventional semiconductor memory devices are configured as described above, but it is difficult to adjust the timing from the rise of the word line in each array to the operation of the sense amplifier, and the resistance to soft errors caused by alpha rays is also weakened. There was a problem.

This invention was made in order to solve the above-mentioned problems, and aims to appropriately adjust the operation timing of the sense amplifier after WL rises in each array, and to strengthen soft error resistance. shall be.

[Means to solve the problem]

The semiconductor memory device according to the present invention has a dummy word line that is necessarily selected in each array, and this dummy word line is used as a control signal for a sense amplifier drive circuit.

[Effect]

In this invention, the sense amplifiers are driven after the dummy word line in each array has completely risen.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention. In the figure, the difference from the conventional example is that the dummy word line DWL, ~4, which is always selected in each array, is used, and the conventional word line simulator is eliminated.

The dummy word lines in each array are the original word lines WL, ~
4, and the wiring capacitance and resistance are the same, that is, the time constant is also the same. This dummy word line serves as a control signal for the sense amplifier drive circuit (1).

FIG. 2 is a timing chart showing the operation of this embodiment. The present invention will be explained in detail using this figure.

As previously explained, the main clock R of DRAM
When AS becomes low active, the basic signal R of WL
It becomes X or “High”.

At this time, word lines WL1 to .
or stand up at the same time.

At this time, the dummy word line DW used in each array
L, to 4 are also selected at the same time. When word line WL~4 rises, each memory cell data is read out on each line, or at this time Dwh rises at the same time.
Since nt serves as a control signal for the sense amplifier drive circuit, the sense amplifier operates as soon as memory cell data is read onto the bit line for each array.

〔Effect of the invention〕

As described above, according to the present invention, since the chip area increases due to the increase in capacity, depending on the position of the conventional WL nomulator and the wiring resistance/capacitance, the sense amplifier is Drive timing adjustment becomes easy. That is, the timing for driving the sense amplifiers from the word line is appropriate for each array, and the problem of soft error resistance due to alpha rays differing from array to array can be achieved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing chart showing the operation timing of Fig. 1, Fig. 3 is a block diagram showing a conventional example, and Fig. 4 is a timing chart showing the operation. It is a chart diagram. (1) ... sense amplifier drive circuit, (2)
... WL simulator, (3) -RX G
Enerctos. α0) ... Memory cell, WL, ~4 ... Word line, B, L, B, L
, ・・・ Bit line, Dwhnt ・・
- Dummy word line. In the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa $2 Figure 4

Claims (1)

[Scope of Claims] A plurality of word lines that select memory cells in a specific row in a memory cell array, and a plurality of bit lines that are connected to each of the memory cells and bit lines related to the bit lines. and simultaneously select one or more plural word lines, in a cell array including one word line and one column of sense amplifiers,
A semiconductor memory device comprising one dummy word line that is always selected, and wherein the one column of sense amplifiers is controlled by the dummy word line.