JPH04205350A - Record tabulation circuit - Google Patents

Abstract

PURPOSE:To tabulate record tabulation data classified by every category record only by adding simple circuit configuration by reading out the record tabulation data classified by every category tabulated in an accumulative register by an adder circuit and erasing the content of the accumulative register when noncoincidence between both data is obtained by a comparator. CONSTITUTION:The comparator 4-8 compares the category data taken out newly from a category masking circuit 4-7 with the one of preceding record stored in a holding register 4-9. When the noncoincidence is obtained between them by the comparator 4-8 as a result, a clear signal is supplied to the accumulative register 4-2, and a write signal to a storage part 4-5 for output. In such a case, the value of the accumulative register 4-2 is cleared after the value of the accumulative register 4-2 is written on the storage part 4-5 for output. Thereby, it is possible to tabulate the data targeted to tabulate in each record classified by every category by intercepting CPU processing only by adding the simple circuit configuration.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to office computers, etc. (7) l/ :I
- Add to the code aggregation circuit.

[Summary of the Invention J This invention provides a record aggregation circuit equipped with an adder that adds data in an aggregation target field included in each record to data in an accumulation register. is extracted using hardware, and the data in the field to be aggregated in each record is aggregated for each category code.

[Conventional technology]

2. Description of the Related Art Conventionally, as a record aggregation device for an office computer or the like, the one shown in FIG. 3 is known.

That is, this type of record aggregation device has a CPUI, a main memory device N2, a DMA controller 3, and a record aggregation circuit 4, and the record aggregation circuit 4 temporarily stores data transferred from the main memory device 2 by the DMA controller 3. An input register 4-1 for storing, an adder 4-3 for adding the data in the input register 4-1 to the data in the accumulation register 4-2, and an adder 4-3 for adding the data in the accumulation register 4-2 to the data in the accumulation register 4-2 at a predetermined timing. The data in this output register 4-5 is taken into the CPUI as a total result.

Figure 4 shows the record structure stored in the main storage device 2. Each record is variable length data and consists of arbitrary fields. At the beginning of each record is a delimiter indicating a record break, that is, a record start code. “(′
is added, and a delimiter indicating the end of the field, that is, a field end code "," is added at the end of each field. Here, the first field of each record is a 5-digit product code, the second field is the product name, the third field is the unit price, the fourth field is the quantity, and the fifth field is the amount. They are arranged in ascending order based on the size of the product code in the field. Note that categories are classified according to values from the most significant digit to an arbitrary digit in the first field. That is, as shown in FIG. 5, records with the same three-digit data from the most significant digit belong to the same category. For example, "000J" is department "1," roolJ is department "2," and ro10J is department "3." ) is supported.

The record aggregation device configured as described above operates as follows.

First, the CPU searches for a record start code added to the beginning of each record stored in the main storage device 2, and creates a table in which the beginning addresses of each record are categorized.

Next, refer to this table, search for the field end code from the beginning of each record, and create a table that extracts the data in the fields to be aggregated.

In this way, when each record in the main memory $122 is transferred to the record aggregation circuit 4, the above-mentioned preprocessing is performed beforehand.

After that, when the DMA controller 3 is started, the DMA
The controller 3 transfers the data of the fields to be aggregated from the main storage device 2 to the record aggregation circuit 4 in category units. As a result, in the record aggregation circuit 4, the data transferred from the main storage device 12 is transferred from the input registers 4 to
After being stored in I, the adder 4-3 adds the value to the accumulation register 4-2, and the addition result is stored in the accumulation register 4-2.

Therefore, when the above-mentioned aggregation operation is executed for l categories, the data in the cumulative register 4-2 is transferred to the output register 4-2.
At the same time, the contents of the accumulation register 4-2 are cleared. Then, the CPU 1 takes in the value of the output register 4-4 as the aggregation result for l categories. After that, aggregation for the next category is started, and the DMA controller 3 is the main memory that belongs to that category! The data in 2 is transferred to the record aggregation circuit 4. Thereafter, the above-described operation is repeated until all categories are completed.

[Section B to be solved by the invention] In this way, when the data of the aggregation target field included in each record is aggregated by category, the CPU 1
This requires complicated processing, which places a burden on the CPU and hinders high-speed aggregation.

An object of the present invention is to perform complex CPU processing by simply adding a simple circuit configuration, thereby making it possible to aggregate data in fields to be aggregated in each record by category code.

[F stage J to solve 8 problems The means of this invention are as follows.

(1) The extraction circuit sequentially extracts only the category codes containing the name code r each time a plurality of records are sequentially transferred.

(2) Store and hold the category code of the previous code extracted by this extraction circuit.

(3) The comparison circuit a compares the category code of the current record newly started by the extraction circuit with the category code of the previous record stored in the holding register.

(4) When the comparison circuit detects a match between the two, the addition circuit adds the data in the aggregation target field included in the current record to the data in the accumulation register.

(5) Record collection J by cumulative register date category code
Store data.

[Work] The first operation of this invention is as follows.

Now, when a plurality of records are sequentially transferred, the extraction circuit sequentially extracts the category codes included in each record.

In this case, the holding register stores the category code of the previous record extracted by the extraction circuit, so the comparison circuit stores the category code of the current record newly extracted by the extraction circuit and the holding register. Compare the category code of the previous record.

As a result, when the comparison circuit detects a match between the two, the addition circuit adds the data in the aggregation target field included in the current record to the data in the accumulation register. In this way, the value of the cumulative register is updated every time a match of category codes is detected by the comparison circuit, so the value of the cumulative register becomes record total data for each category code.

When the comparison circuit detects a mismatch in the category codes, the record total data for each category accumulated in the accumulation register is read out and transferred to output memory #1, etc. The contents of are cleared.

Therefore, by performing complex CPU processing by simply adding a simple circuit configuration, the data in the field to be counted in each record can be totaled by category code.

[Example J Hereinafter, an example will be described with reference to FIGS. 1 and 2.

Figure 1 shows a record aggregation device (office combination).

- Fig. 2 is a circuit configuration diagram of the In FIG. 1, parts with the same names as those in FIG. 3 are indicated by the same reference numerals.

Is this record aggregation device CPUI or main memory? , DM
A controller 3. The record aggregation circuit 4 of this embodiment has the following configuration.

In the record aggregation circuit 4, the part A surrounded by the broken line in Figure 1
is a part corresponding to a conventional l/code aggregation circuit, and in addition to an input register 4-1, an accumulation register 4-2, and an adder 4-3, in this embodiment, output storage devices 4 to 5 are provided. ing.

In addition, part B surrounded by a broken line in the figure indicates the category recognition part,
This category recognition unit B includes a category designation register 4-6,
Category mask circuit 4-7. Comparator 4-8. The configuration is such that the holding registers 4-9 are held in place. The category designation register 4-6 stores the number of digits for designating the number of digits from the beginning of the first field of each record to be recognized as a category code, and its value can be set arbitrarily. Category mask circuit 4-7 is input register 4-1
The category code is extracted by extracting the code for the number of digits set in the category specification register 4-6 from the beginning of the record written in the record, and the category code thus extracted is sent to the comparator 4-8. and is compared with the contents of holding registers 4-9. The holding register 4-9 holds the category code of the record read last time, and the comparator 4-8 stores the newly extracted category code from the category mask circuit 4-7 in the holding register 4-9. Compare the category code of the previous record. As a result, comparator 4
-8 detects a mismatch between the two, the cumulative register 4-2
A clear signal is given to the memory section 4-5, and a write signal is given to the output storage section 4-5. In this case, the value of the cumulative register 4-2 is written to the output storage section 4-5, and then the value of the cumulative register 4-2 is cleared.

The delimiter detection section 4-1O detects a delimiter (record start code or file end code) from the input register 4-1.

Upon detection, a category code write signal of the previous record is sent to the holding register 4-9, a comparison operation signal is sent to the comparator 4-8, and a field number counter 4-1 is sent.
For 1, a clear signal and a count up signal are given.

The field number counter 4-11 is cleared by a clear signal output from the delimiter detector 4-1O when a record start is detected, and the field number counter 4-11 is cleared by a clear signal output from the delimiter detector 4-10 every time a field end code is detected. In accordance with the up signal, the value of the field number counter 4-11 is counted up by plus rlJ.

The comparator 4-12 uses this field number counter 4-11.
The value is compared with the value arbitrarily set in the aggregation target field number register 4-13 in advance, and the current field number counted by the field number counter 4-11 is the value in the aggregation target field number register 4-13. When the values match, a comparison operation signal is given to the adder 4-3.

Next, the operation of this embodiment will be explained.

First, in the first field of each record.

In order to specify the number of digits from the beginning to be recognized as the category code, set an arbitrary number of digits in the category specification register 4-6, and also specify which field in the record is to be updated. An arbitrary number is set in the aggregation target field number register 4-13 in order to specify the field number.

After performing such initial settings, when a record update instruction is given, the CPUI starts up the DMA controller 3. Then, the DMA controller 3 sequentially reads out the data in the main storage device 2 in predetermined units and transfers it to the record aggregation circuit 4.

Here, in the record aggregation circuit 4, the main memory M2
The data from is written to input register 4-1. Here, the delimiter detection section 4-10 is connected to the input register 4-1.
If the data within is a delimiter, various signals are output as the delimiter is detected, as shown in FIG.

T! Figure s2 shows the output timing of various signals output from the delimiter detection section 4-10 upon detection of the record start code and field end code, and each signal is all low active.

Here, when the delimiter detection section 4-10 detects a record start code, it outputs a clear signal to the field number counter 4-11 in synchronization with it, and when it detects a field end code, it outputs a clear signal to the field number counter 4-11 in synchronization with it. -11, a count up signal is output. Further, the delimiter detection unit 4-10 outputs a comparison control signal to the comparator 4-8 from the time when the record start code is detected until the first field end code is detected, and also outputs a comparison control signal to the comparator 4-8. Every time the end code of the first field is detected, a write signal is output to the holding register 4-9.

Now, when the delimiter detection section 4-10 detects a record start code, it outputs a comparison control signal to operate the comparator 4-8 until it detects the first field end code in the record. As a result, the comparator 4-8 compares the category code of the previous record stored in the holding register 4-9 with the category code newly detected this time. Here, the newly detected category code is created by masking the data in the input register 4-1 through the category mask circuit 4-7 according to the number of digits set in the category specification register 4-6. It is what was done.

Now, when a match is detected, the cumulative registers 4 to 2 are
The 1 NOR signal and the old input signal to the output storage section 4-5 are not output, and the count of the accumulation register 4-2 is held as is.

On the other hand, the field number counter 4-11 is cleared by the clear signal output from the prime/event detector 4-10 when the 1/coat star) code is detected, and thereafter, every time the field end code is detected, the field number counter 4-11 is cleared. Delimiter detection section 4. The value of the field number counter 4-11 is counted up in accordance with the count-up signal output from -10. Here, the comparator 4-12 compares the values of the field number counter 4-IJ and the aggregation target field number registers 4-13. and when the data of the aggregation target field is stored in the input register 4-1,
When the comparator 4-12 detects a match, the adder 4-3 operates, and the adder 4-3 adds the value of the input register 4-1 and the value of the accumulation register 4, -2, and calculates the addition result. is stored in the accumulation register 4-2.

Furthermore, when the prime and evening detection units 4 to 10 detect the Jent code in the first field, they give a write signal to the holding register 4-9, so that the category code from the category mask circuit 4-7 is the category of the city 7th record. It is written to the holding register 4-9 as a code.

Therefore, every time a match of category codes is detected by the comparator 4-8, the adder 4-3 operates and adds the value of the input register 4-1 to the value of the cumulative register 4-2.
The contents of each record belonging to the same category are totaled in the cumulative register 4-2.

On the other hand, when a mismatch of category codes is detected by the comparator 4-8, the contents of the cumulative register 4-2 are written to the output storage section 4-5 and then cleared. As a result, the record total data for each category is sequentially stored in the output storage section 4-5.

In the above embodiment, the category code is included in the key code in the name record, but a special field for the power category code may be provided in the record.

[Effects of the Invention] According to the present invention, by performing complex CPU processing by simply adding a simple circuit configuration, it is possible to aggregate the data of each field to be collected in z-F by category code. Therefore, high-speed aggregation is possible without putting a burden on CP (J).

[Brief explanation of the drawing]

1 and 2 show one embodiment, FIG. 1 is a circuit configuration diagram of a record aggregation device, and FIG. 2 is an output waveform of various signals for explaining the operation of the prime data detector 4-10. figure,
Figures 3 to 5 are diagrams for explaining the conventional example. Figure 3 is a circuit configuration diagram of a record tabulation device, Figure 4 is a record configuration diagram, and Figure 5 is a diagram for explaining the same category. It is a diagram. 4...Record aggregation circuit, 4-2...
Accumulation register, 4-3... Adder, 4-6...
...Category specification register, 4-7...Category mask circuit, 4-8...Jl; Comparator, 4
-9...Holding register, B...Category recognition unit. Patent applicant Casio Computer Co., Ltd. Figures 2 and 3

Claims (1)

[Scope of Claims] An extraction circuit that sequentially extracts category codes included in each record each time a plurality of records are sequentially transferred; and a storage and storage of the category code of the previous record extracted by this extraction circuit. a comparison circuit that compares the category code of the current record newly extracted by the extraction circuit with the category code of the previous record stored in the holding register; and the comparison circuit detects a match between the two. an addition circuit that adds the data in the aggregation target field included in the current record to the data in the cumulative register when the comparison circuit detects a mismatch between the two; A record totaling circuit, characterized in that the record totaling data for each category compiled in the cumulative register is read out and the contents of the cumulative register are erased.