JPH04204891A - Driving circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE:To decrease a capacitor capacity and to reduce the size of the device by placing an amplifier behind the capacitor for holding sampled image signals. CONSTITUTION:A transfer section is provided between a sampling section and a holding section and an operational amplifier 34 of the transfer section transfers the signal voltage held in a sampling capacitor 32 to a hold capacitor 35. The capacity C1 of the sampling capacitor 32 is, therefore, not required to be a so much large value. The size of the sample-hold circuit is reduced and the size over the entire part of the driving circuit and the liquid crystal display device is reduced. Since the smaller capacity C1 of the sampling capacitor 35 is necessitated, the sampling time is shortened and the charging time of the hold capacitor 35 is shortened as well by the operational amplifier 34. The fine liquid crystal display device is thus obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a drive circuit for a matrix type display device, and more particularly to a drive circuit for a matrix type display device with an improved column electrode drive section.

(Prior Art) A schematic structure of a conventional active matrix liquid crystal display device is shown in FIG. 3(a), and signal waveforms at various parts of the liquid crystal display device are shown in FIG. 3(b). The present liquid crystal display device includes a liquid crystal display panel 11, a row electrode driver 12, a column electrode driver 14, a signal control section 13, for driving the liquid crystal panel 11,
It is composed of a drive circuit including a data control section 15 and the like.

The liquid crystal panel 11 is composed of picture elements arranged in M rows and N columns having a structure as shown in the enlarged view on the right side of FIG. 3(a). As shown in the figure, each picture element is provided with a switching transistor 11-c made of TPT.
The gate has a row electrode 11-8, and the drain has a column electrode 1-8.
1-b, and a picture element liquid crystal is connected to the source. M
All of the row electrodes 11-8 of the book are connected to the row electrode driver 12, and all of the N column electrodes 11-b are connected to the column electrode driver 14.

The row electrode driver 12 is mainly composed of a shift register, and as shown in FIG. 3(b), shifts the scanning pulse S according to the clock pulse φ1 from the control signal section 13.
It sequentially outputs to each row electrode 11-a. The column electrode driver 14 consists of a shift register, a sample hold circuit, etc., and samples the image signal sent in series from the data control section 15 at a timing corresponding to each column in synchronization with the clock pulse φ2 from the control signal section 13. Then, the signal value is held for one horizontal scanning period (F in the scanning waveform in FIG. 3(b)) and output to each column electrode.

The column electrode driver 14 is equipped with a sampling and holding circuit as shown in FIG. 4(a) for each column electrode 11-b. As shown in the figure, this circuit is composed of a sampling section, a hold section, and a cover sofa section.The sampling section includes a first switch 21 and a sampling capacitor 23 (capacitance C11), and the hold section includes a second switch 22. and hold cow Yabashita 24 (capacity Cl2), and output cover, third and fourth switches 26.27 in the fa part.
and an operational amplifier 25. First switch 21
The sampling pulse Pa is input to the second switch 22, the output pulse Pb is input to the third and fourth switches 26, 27, and the reset pulse Pc is input to the third and fourth switches 26, 27 as switching control signals.

When the switching control signal pulse reaches level 7, each switch 21, 22, 26, 27 becomes conductive.

Clock pulse φl and these switching control signals Pa
, Pb, and Pc are shown in FIG. 4(b). First, the switch 21 becomes conductive due to the sampling pulse Pa, and the voltage of the input image signal at that point is applied to the sampling capacitor 23. Since the sampling capacitor 23 is charged to the signal voltage potential by applying this signal voltage, even after the sampling pulse Pa falls to a low level and the sui-nochi 21 becomes non-conductive, the value of this signal voltage remains at the sampling capacitor 23. is maintained.

In this way, N column electrodes 11 within l horizontal scanning period.
After the image signal voltages are sequentially sampled for all of -b, the output pulses pb input to the second switches 22 of all column electrodes become high level, and the switches 22 become conductive. As a result, the signal voltage held in the sampling capacitor 23 is applied to the hold capacitor 24, and the hold capacitor 24 is similarly charged to the signal voltage level. The signal voltage held in the hold capacitor 24 is held for the next one horizontal scanning period, during which the signal voltage is applied to the corresponding column electrode 11-b through the operational amplifier 25.
continues to be output.

When one horizontal scanning period ends, the third and fourth switches 26
．． The reset pulse Pc input to the switch 27 becomes high level, and the voltage held in the hold capacitor 24 is discharged through these switches 26 and 27 and disappears. After these switches 26 and 27 return to non-conduction, the signal charge sampled during the previous horizontal scanning period and held in the sampling capacitor 23 is transferred to the hold capacitor 24.

(Problem H to be Solved by the Invention) In the configuration of the conventional column electrode driver described above, sampling is required in order to faithfully transfer the signal voltage sampled from the input image signal and held in the sampling capacitor 23 to the hold capacitor 24. Capacitance C of capacitor 23
It is necessary to make 1l sufficiently larger than the capacitance C12 of the hold capacitor 24. The reason is as follows.

The voltage between both electrodes of the sampling capacitor 23 is set to V1%.
Assuming that the voltage between both electrodes of the hold capacitor 24 is Vg, the voltage between them is Vg" (C1l/ (C11+Cl2) l ・V
There is a relationship called i. The right side of this equation shows that as the value of C12 increases, Vg becomes smaller than Vi, and therefore, in order to make Vg=Vf, it is necessary to set CID>C12. Moreover, both capacitors 23.
Since there is also a resistance component in the switch 22 between 24 and 24,
From this point of view, the capacitance C1l of the sampling capacitor 23
needs to be a sufficiently large value. On the other hand, there is a limit to reducing the value of CI2 because if the capacitance C12 of the hold capacitor 24 is made too small, the signal voltage will not be sufficiently output to the data signal line.

For these reasons, in the conventional column electrode driver, it is necessary to set the capacitance C1l of the sampling capacitor 23 to a certain or larger value, but as the value of C1l increases, the element area of the capacitor increases. However, this is contrary to the recent demands for higher definition of liquid crystal display devices and higher integration of drive circuits.

Further, since it becomes necessary to take a long time to sample the signal voltage to the sampling capacitor 23, it is contrary to the request for improving the horizontal resolution.

The present invention was made in view of the current situation, and
The purpose of this invention is to provide a highly integrated drive circuit that can eliminate the above-mentioned drawbacks, can respond to higher definition of liquid crystal display devices, and can accommodate higher definitions of liquid crystal display devices.

(Means for Solving the Problems) A drive circuit for a display device according to the present invention is a drive circuit that outputs a signal voltage to the column electrodes of a matrix type liquid crystal display device having a plurality of column electrodes parallel to each other. For each column electrode, signal holding means holds the image signal voltage sampled within one horizontal scanning period during the horizontal scanning period, is non-conductive during one horizontal scanning period, and is non-conductive after the horizontal scanning period ends. A switch means for outputting the image signal voltage held in the signal holding means to the next stage by becoming conductive, and a buffer means provided between the signal holding means and the switch means. This achieves the above objective.

(Function) When the switch means becomes conductive after the horizontal scanning period,
The image signal voltage held in the signal holding means is output to the next stage through the buffer means (to the column electrodes via a hold capacitor for holding the voltage output to the column electrodes during the output period, or directly to the column electrodes). Ru. By interposing the buffer means between the signal holding means and the column electrode, the amount of discharge of the signal holding means can be reduced, and the capacity of the signal holding means can be reduced.

(Example) The invention will now be described with reference to examples.

FIG. 1 shows a circuit according to an embodiment of the present invention. This circuit corresponds to the sampling and hold circuit of FIG. 4(a) in the conventional column electrode driver, and is provided for each column electrode 11-b in the column electrode driver 14 of FIG. 3. In addition to the sampling section, hold section, and output buffer section of the conventional circuit shown in FIG. 4(a), this circuit has a transfer section between the sampling section and the hold section.

A first switch 31 and a sampling capacitor 32 in the sampling section, a second switch 33 and a hold capacitor 35 in the hold section, and an operational amplifier 36 in the output buffer section.
The third and fourth switches 37 and 38 each have a similar function to the corresponding elements in the conventional circuit of FIG. Also, like the conventional circuit, the first to fourth switches 31, 33 .
37 and 38 respectively have sampling pulses Pa and
An output pulse Pb and a reset pulse Pc are input.

In this embodiment, the transfer section inserted between the sampling section and the holding section is constituted by a second operational amplifier 34, and this second operational amplifier is adjusted to output a voltage of the same value as its input.

The operation of the circuit of this embodiment will be explained next. An image signal Vin amplified by the preceding image signal amplification circuit and periodically inverted is input to the input terminal of this circuit. 1 At a predetermined time during the horizontal period, the sampling pulse Pa input to the first switch 31 of this circuit becomes a high level, and the image signal voltage Vi at that time is applied to the sampling capacitor 32 (
is applied to the capacitor C1). As a result, the potential difference between both ends of the sampling capacitor 32 becomes Vi. When such sampling is completed for all column electrodes within one horizontal period, the output pulse pb input to the second switch 33 of all column electrodes goes high before returning to sampling the first column of the next row. level, and the second switch 33 becomes conductive. As a result, the voltage Vi held in the sampling capacitor 32 is input to the second operational amplifier 34, and the second operational amplifier 34 outputs the same voltage vi as described above. The output of the second operational amplifier 34 rapidly charges the hold capacitor 735 to the same voltage Vi. after that,
The operation until the signal voltage is output from the column electrode is similar to the conventional circuit shown in FIG.

In this embodiment, a transfer section is provided between the sampling section and the hold section, and since the operational amplifier 34 in the transfer section transfers the signal voltage held in the sampling capacitor 32 to the hold capacitor 35, the capacitance C1 of the sampling capacitor 32 is It doesn't need to be such a large value. Therefore, the sampling and hold circuit shown in FIG. 1 can be downsized, and the driving circuit and the entire liquid crystal display device can be downsized. In addition, since the capacitance C1 of the sampling capacitor 32 can be small, the sampling time can be shortened, and the operational amplifier 34 can also shorten the charging time of the hold capacitor 35, making it suitable for high-definition liquid crystal display devices. can do.

Next, a second embodiment of the present invention will be described with reference to FIG. In the column electrode driver of this example, 2 m is provided for one column electrode.
A sampling halt circuit connected in parallel is provided. The configuration of each sampling hold circuit is the same, including a first switch 41.42, a capacitor 43.44
, operational amplifier 45.46, and second switch 47.48
It consists of During one horizontal scanning period, one of the first switches 41 (in this case, the upper sampling and hold circuit in FIG. 2) becomes conductive at the time corresponding to that column electrode due to the sampling pulse Pd. The image signal at that point in time is sampled and the signal voltage is held in the capacitor 43. During this time, the upper second switch 47
is always non-conductive (the output pulse Pf is at a low level), and the signal voltage remains held in the capacitor 43. Further, the lower first switch is also always non-conductive (the sampling pulse pe is at a low level), and the image signal during this horizontal scanning period is sampled only in the upper circuit.

However, since the output pulse Pf is inverted (at high level) by the inverter 49 and inputted, the lower second switch 48 is always conductive during this horizontal scanning period, and as will be described later, The signal voltage sampled during the period and held in the lower capacitor 44 is output to the column electrode 5o.

In the next horizontal scanning period, on the contrary, the output pulse Pf becomes high level, and the lower second switch 48 becomes non-conductive. At the same time, the lower first switch 42 becomes conductive at the same time due to the sampling pulse Pe, samples the image signal, and holds the signal voltage in the capacitor 44. In the upper sampling and hold circuit,
Since the output pulse Pf is at a high level, the second switch 47 is always conductive, and the image signal voltage sampled during the previous horizontal scanning period, which is held in the capacitor 43, is input to the operational amplifier 45, and the same voltage is input to the operational amplifier 45. Column electrode 5
Output to 0.

In any of these horizontal scanning periods, when the second switch 47 or 48 becomes conductive and a signal voltage is output from the capacitor 43 or 44 to the column electrode 5o, there is a gap between the capacitor 43 or 44 and the column electrode 50. An operational amplifier 45 is involved. Therefore, the discharge amount of the capacitor 43 can be made very small, and the capacitance of the capacitor 43 can be made small.

(Effects of the Invention) According to the present invention, in a column electrode drive circuit of a liquid crystal display device, since an amplifier is placed after a capacitor that holds a sampled image signal, the capacitance of the capacitor can be reduced. Therefore, the degree of integration of the column electrode drive circuit can be increased, and the size of the drive circuit or a liquid crystal display device incorporating the same can be reduced. Furthermore, since the charging time of the sampling capacitor can be shortened, it is possible to respond to higher definition of liquid crystal display devices.

Figure 1 is a circuit diagram of one sampling bold circuit in a column drive circuit of a liquid crystal display device as an embodiment of the present invention.
FIG. 2 is a circuit diagram of another embodiment of the present invention, FIG. 3 is a schematic configuration diagram of the entire liquid crystal display device, and FIG. 4 is a circuit diagram of a conventional drive circuit.

11...Liquid crystal panel, 12...Row electrode driver, 1
3... Scanning pulse control section, 14... Column electrode driver, 15... Data control section, 31.33.37.38.
41.42.47.48...Switch, 34.36.
45.46... operational amplifier, 32... sampling capacitor, 35... hold capacitor, 43.4
4... Sampling and hold common capacitor, 49.
...Inverter gate, 50...column electrode amount upper

Claims (1)

[Claims] 1. A drive circuit that outputs a signal voltage to the column electrodes of a matrix type liquid crystal display device having a plurality of column electrodes parallel to each other, the drive circuit outputting a signal voltage to the column electrodes of a matrix type liquid crystal display device having a plurality of column electrodes parallel to each other, the drive circuit outputs a signal voltage to the column electrodes of each column electrode within one horizontal scanning period. a signal holding means for holding an image signal voltage sampled during the horizontal scanning period; the signal holding means is non-conductive during one horizontal scanning period, becomes conductive after the horizontal scanning period ends, and is held in the signal holding means; 1. A driving circuit for a liquid crystal display device, comprising: a switch means for outputting an image signal voltage to a next stage; and a buffer means provided between the signal holding means and the switch means.