JPH0420274B2 - - Google Patents

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Publication number
JPH0420274B2
JPH0420274B2 JP56156282A JP15628281A JPH0420274B2 JP H0420274 B2 JPH0420274 B2 JP H0420274B2 JP 56156282 A JP56156282 A JP 56156282A JP 15628281 A JP15628281 A JP 15628281A JP H0420274 B2 JPH0420274 B2 JP H0420274B2
Authority
JP
Japan
Prior art keywords
region
layer
junction
impurity concentration
electric field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56156282A
Other languages
Japanese (ja)
Other versions
JPS5857760A (en
Inventor
Hirobumi Oochi
Hiroshi Matsuda
Makoto Morioka
Masahiko Kawada
Kazuhiro Kurata
Yasushi Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56156282A priority Critical patent/JPS5857760A/en
Priority to KR8204346A priority patent/KR900000074B1/en
Priority to EP82109103A priority patent/EP0076495B1/en
Priority to DE8282109103T priority patent/DE3277353D1/en
Publication of JPS5857760A publication Critical patent/JPS5857760A/en
Priority to US06/880,118 priority patent/US4740819A/en
Publication of JPH0420274B2 publication Critical patent/JPH0420274B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • H01L31/1075Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】 本発明は半導体検出器に係り、特に高感度、低
暗電流高速性の実現に好適な受光素子に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor detector, and particularly to a light receiving element suitable for realizing high sensitivity, low dark current, and high speed performance.

従来は、第1図aおよびbに示すようにメサ型
あるいはプレーナ型構造の受光素子が提案されて
いる。半導体基板01上に第1の導電型の半導体
層02および第2の導電型の半導体層03が形成
され、更に電極08,09が設けられている。第
1図aの様なメサ型構造では、高い電界が接合端
面に露出することになるため、表面保護膜の性質
によつて素子特性が左右されることになり、実用
上望ましくない。一方、第1図bのプレーナ構造
(公開特許公報昭55−132079号)では、メサ型構
造に比べて安定な動作が得られると期待される。
第1図bの構造では、InP半導体基板1上にn+
InP層2,InGaAsP層3,およびn型InP層4が
形成されている。6はたとえばCd拡散層でこの
拡散端面でPn接合が形成されている。7は絶縁
層、8,9は電極である。しかしながら、次に述
べる様な欠点がある。
Conventionally, a light receiving element having a mesa type or planar type structure as shown in FIGS. 1a and 1b has been proposed. A first conductivity type semiconductor layer 02 and a second conductivity type semiconductor layer 03 are formed on a semiconductor substrate 01, and electrodes 08 and 09 are further provided. In a mesa-type structure as shown in FIG. 1a, a high electric field is exposed at the junction end face, and the device characteristics are influenced by the properties of the surface protective film, which is not practically desirable. On the other hand, the planar structure shown in FIG. 1B (Japanese Unexamined Patent Publication No. 132079/1986) is expected to provide more stable operation than the mesa structure.
In the structure shown in Fig. 1b, an n + type
An InP layer 2, an InGaAsP layer 3, and an n-type InP layer 4 are formed. 6 is, for example, a Cd diffusion layer, and a Pn junction is formed at the end face of this diffusion layer. 7 is an insulating layer, and 8 and 9 are electrodes. However, there are drawbacks as described below.

禁止帯幅の大きい物質としてInP結晶を適用す
る場合、蒸気圧の高いPが結晶成長後の素子作成
プロセスの熱処理工程に於て解離し、表面層は変
質することが考えられる。それ故に、表面保護膜
形成後の界面特性は不安定となり、暗電流が大き
くなる原因になる。
When an InP crystal is used as a material with a large forbidden band width, it is conceivable that P, which has a high vapor pressure, dissociates during the heat treatment step of the device fabrication process after crystal growth, and the surface layer changes in quality. Therefore, the interfacial properties after the surface protective film is formed become unstable, causing an increase in dark current.

また、一般に半導体物質では、有効質量や禁止
帯幅が小さくなる程、及び不純物濃度が高い程、
トンネル効果によつて降伏を起す電界強度は低下
するため、禁止帯幅の大きい領域(例InP)中に
形成されるPn接合面と禁止帯幅の小さい領域
(例、InGaAsP)間の距離lが小さい場合には禁
止帯幅の大きい領域に形成されたPn接合がアバ
ランシエ増倍作用を起す前に、禁止帯幅の小さい
物質の電界がトンネル効果を起すに充分な電界に
到達してしまい、トンネル降伏を起してしまう。
In general, in semiconductor materials, the smaller the effective mass and forbidden band width, and the higher the impurity concentration, the more
Since the electric field strength that causes breakdown decreases due to the tunnel effect, the distance l between the Pn junction surface formed in a region with a large bandgap width (e.g. InP) and a region with a small bandgap width (e.g. InGaAsP) increases. If the bandgap is small, the electric field of the material with a small bandgap reaches an electric field sufficient to cause a tunnel effect before the Pn junction formed in the region with a large bandgap causes avalanche multiplication, and the tunneling occurs. It causes surrender.

本発明の目的はpn接合と禁止帯幅の小さい層
(光吸収領域)との距離、各層の不純物濃度、各
層の厚さをアバランシエ増倍作用が効果的に生起
するように設定することにより高感度で暗電流が
小さく、高速性を有する受光素子を提供すること
にある。一般に、トンネル電流は次式で表わすこ
とができる。
The purpose of the present invention is to increase the avalanche multiplication effect by setting the distance between the pn junction and the layer with a small forbidden band width (light absorption region), the impurity concentration of each layer, and the thickness of each layer so that avalanche multiplication effect occurs effectively. The object of the present invention is to provide a light receiving element having high sensitivity, low dark current, and high speed. Generally, tunnel current can be expressed by the following equation.

J=(m*1/2q2ε・E3n/4√2π2h-2NE1/2exp(
−π(m*1/2E3/2/2√2qhEn) (1) m*:有効質量、q:電子電荷素量、 h=h/2π:hはプランク定数、 N:不純物濃度 Eg=:禁止帯幅、ε:誘電率、En電界強度 接合が階段型であると仮定すると、電界強度と動
作電圧(トンネル降伏電圧VT)との関係は次式
で与えられる。
J = (m * ) 1/2 q 2 ε・E 3 / n /4√2π 2 h -2 NE 1/2 exp (
−π (m * ) 1/2 E 3/2 /2√2qhE n ) (1) m * : effective mass, q: elementary charge of electrons, h=h/2π: h is Planck's constant, N: impurity concentration E g =: forbidden band width, ε: dielectric constant, E n field strength Assuming that the junction is of a stepped type, the relationship between the electric field strength and the operating voltage (tunnel breakdown voltage V T ) is given by the following equation.

VT=ε/2qNE2 n (2) 一方、アバランシエ降伏電圧VAは次式で与えら
れる。
V T =ε/2qNE 2 n (2) On the other hand, the avalanche breakdown voltage V A is given by the following equation.

VA=60(Eg/1.1)3/2・(N/1016-3/4 (3) いま、lnGaAsPからなるpn接合を例にとつて
VT=VAなる不純物濃度を求めると、下記の様に
なる。
V A =60 (E g /1.1) 3/2・(N/10 16 ) -3/4 (3) Now, taking a pn junction made of lnGaAsP as an example.
The impurity concentration, V T =V A , is determined as follows.

InP (Eg対応λ1.35μm):〜3×1017cm-3 In0.79Ga0.21As0.47P0.53(Eg対応λ1.2μm): 〜2×1016cm-3 In0.75Ga0.25As0.56P0.44(Eg対応λ1.3μm) 〜7×1015cm-3 In0.61Ga0.39As0.83P0.17(Eg対応λ1.55μm) 8×1014cm-3 アバランシエ増倍作用が有効に起るためには、
VT>VAであることが必要となるため、不純物濃
度は上記値よりも低くすることが必要となる。従
つて第1図bに示すような構造にすれば、禁止帯
幅の大きい物質の不純物濃度とlによつては禁止
帯幅の小さい物質の不純物濃度に対する制限はや
や緩和されるが、アバランシエ増倍作用を期待す
るためには、禁止帯幅の大きい物質ではVT〉VA
なる関係が成立すると共に、禁止帯幅の小さい領
域での最大電界Ensは、トンネル降伏時の電界強
度ET(不純物濃度によつては、アバランシエ降伏
時の電界強度EA)よりも小さくなるように素子
設計を行なうことが重要である。距離lと禁止帯
幅の大きい物質と小さい物質の不純物濃度を各々
NL,Nsとすれば、上述した条件を満たすために
は、それらの間には少なくとも次の関係を満たす
ことが必要になる。以下、第4図を使用して、こ
の満たすべき関係について詳細に説明する。アバ
ランシエ型フオトダイオードのpn接合の近傍は
模式的に第4図aに示す断面図のように、第1の
導電型(例えば、n-)を示す禁止帯幅の小さい
第1の領域20と、この第1の領域よりも禁止帯
幅が広く第1の導電型を示す第2の領域21と、
第2の領域内に選択的に設けられpn接合を形成
するための第2の導電型(例えば、P+)を示す
領域22とからなる。pn接合面23を原点を含
む面として第1の領域の方向にx軸をとり、Pn
接合面と第1の領域間の距離lとする。第4図b
は第4図aに示すA−A′断面における電界強度
を模式的に示している。通常は拡散でPn接合を
形成するため階段型接合となり、n-へのP+拡散
の例を考えると、P+側へ空乏層の拡がりは無視
できる。EnLを禁止帯の幅の大きい物質の最大電
界強度、εL、εSを禁止帯幅の大きい物質と小さい
物質の誘電率とする。第4図bにおいて、第2の
領域での最大電界はB点における、Pn接合の電
界E1であり、E1=EnLとなる。また、第1の領域
での最大電界はC点における、第2の領域との境
界の電界E2であり、これがEnsに相当する。
InP (corresponding to E g λ1.35μm): ~3×10 17 cm -3 In 0.79 Ga 0.21 As 0.47 P 0.53 (corresponding to E g λ1.2μm): ~2×10 16 cm -3 In 0.75 Ga 0.25 As 0.56 P 0.44 (λ1.3μm corresponding to E g ) ~7×10 15 cm -3 In 0.61 Ga 0.39 As 0.83 P 0.17 (λ1.55μm corresponding to E g ) 8×10 14 cm -3 Because avalanche multiplication effect occurs effectively for,
Since it is necessary that V T >V A , the impurity concentration needs to be lower than the above value. Therefore, if the structure shown in Fig. 1b is adopted, depending on the impurity concentration of the material with a large bandgap width and 1, the restrictions on the impurity concentration of the material with a small bandgap width will be somewhat relaxed, but the avalanche increase will increase. In order to expect a double effect, for a substance with a large forbidden band width, V T 〉V A
The following relationship is established, and the maximum electric field E ns in the region with a small forbidden band width becomes smaller than the electric field strength E T at the time of tunnel breakdown (Depending on the impurity concentration, the electric field strength E A at the time of avalanche breakdown). It is important to design the device accordingly. The distance l and the impurity concentration of substances with large and small bandgap widths are respectively
If N L and N s are used, in order to satisfy the above-mentioned conditions, it is necessary to satisfy at least the following relationship between them. Hereinafter, this relationship to be satisfied will be explained in detail using FIG. 4. The vicinity of the pn junction of the avalanche photodiode, as schematically shown in the cross - sectional view in FIG. a second region 21 exhibiting the first conductivity type and having a wider forbidden band width than the first region;
A region 22 is selectively provided in the second region and exhibits a second conductivity type (for example, P + ) for forming a pn junction. The x-axis is taken in the direction of the first region with the pn junction surface 23 as the plane containing the origin, and Pn
Let the distance between the joint surface and the first region be l. Figure 4b
4 schematically shows the electric field strength in the section A-A' shown in FIG. 4a. Normally, a Pn junction is formed by diffusion, resulting in a stepped junction, and if we consider the example of P + diffusion to n - , the expansion of the depletion layer to the P + side can be ignored. Let E nL be the maximum electric field strength of a material with a wide forbidden band width, and ε L and ε S be the dielectric constants of a material with a large band gap and a material with a small band gap width. In FIG. 4b, the maximum electric field in the second region is the electric field E 1 of the Pn junction at point B, and E 1 =E nL . Further, the maximum electric field in the first region is the electric field E 2 at the boundary with the second region at point C, and this corresponds to E ns .

アバランシエ増倍作用が有効に生じるために
は、上述のようにEnsがトンネル降伏時の電界強
度ETより小さいことが必要で、Ens≦ETである。
電界E2は第4図bから、 E2=E1−qlNL/εL E2=EnL−qlNL/εL となる。ここで、εL≠εsの場合εLとεsとの差が小
さければ実用上近似的にE2=Ensとして取り扱え
るが、厳密には電磁気学の基礎から、境界におけ
る電界Eの値自身は不連続であり、E2=Ensとは
ならず、電束、D=εEが連続となる。従つて、上
式をEnsで表すと、 εsEns=εL{EnL−qlNL/εL} となり、Ens≦ETの条件を用いて表わすと、 εL{EnL−qlNL/εL}≦εsQT この式を変形して、 l≧εL/qNL{EnL−εs/εLET} (4) が得らる。
In order for the avalanche multiplication effect to occur effectively, E ns needs to be smaller than the electric field strength E T at the time of tunnel breakdown, as described above, and E nsET .
From FIG. 4b, the electric field E 2 becomes E 2 =E 1 −qlN LL E 2 =E nL −qlN LL. Here, in the case of ε L ≠ ε s , if the difference between ε L and ε s is small, it can be treated approximately as E 2 = E ns in practice, but strictly speaking, from the basics of electromagnetism, the value of the electric field E at the boundary is itself is discontinuous, E 2 = E ns does not hold, and the electric flux, D = ε E , becomes continuous. Therefore, if the above equation is expressed in E ns , ε s E ns = ε L {E nL −qlN LL }, and if expressed using the condition of E nsET , ε L {E nL − qlN LL }≦ε s Q T By transforming this equation, l≧ε L /qN L {E nL −ε sL E T } (4) is obtained.

式4からNLが小の場合に、lは大きくする必
要がある。また式(4)では、不純物濃度Nsは直接
にあらわにでてこないが、ETがNsの関数である
ため、式(4)は間接的にNsを含んでいる。Nsが大
きい程ETは小さくなり、従つて、lは大きくす
る必要がある。
From Equation 4, when N L is small, l needs to be large. Furthermore, although the impurity concentration N s is not directly expressed in equation (4), since E T is a function of N s , equation (4) indirectly includes N s . The larger N s is, the smaller E T becomes, and therefore l needs to be larger.

ETとNsの関係は、実用上は次のようにして、
式(1)から求めることができる。アバランシエ型フ
オトダイオードの実用的な暗電流を設定したとき
(例えば、lnA)、この暗電流のうちトンネル電流
の成分が1/10〜1/100ならば、トンネル降伏の影
響は小さいため、実用上これを無視することがで
きる。この電流値とアバランシエ型フオトダイオ
ードの接合面積から電流密度J1を求める。式(1)の
左辺の、J(電流密度)にJ1を代入し、N→Ns
Eg→Egs(禁止帯幅の小さい領域の禁止帯幅)ε→
εsと置き換えて、数値計算によつて電界強度En
算出することができ、算出されたEnが実用的な
ETを与えることになる。例えばNL=1×1016cm
-3,Ns=2×1016cm-3の場合λ=1.55μmの
InGaAsPに対してlは約1.5μm以上となる。この
例の場合、上述した関係を考慮すると、lは1μm
以下にするような素子設計では禁止帯幅に対応す
る波長が1.3μm、あるいは1.5μmに対応する
InGaAsPを禁止帯幅の小さい物質として用いた
素子構成では、トンネル効果がかなり影響し、有
効なアバランシエホトダイオードを作ることは困
難になる。さらに具体的には、第1図b構造のホ
トダイオード先に説明したように、lの下限はト
ンネル効果の影響を考慮した式(4)によつて定めら
れ、これが本発明の骨子である。
In practical terms, the relationship between E T and N s is as follows:
It can be obtained from equation (1). When setting a practical dark current for an avalanche photodiode (for example, lnA), if the tunnel current component of this dark current is 1/10 to 1/100, the effect of tunnel breakdown is small, so it is not practical for practical use. You can ignore this. The current density J 1 is determined from this current value and the junction area of the avalanche photodiode. Substituting J 1 for J (current density) on the left side of equation (1), N→N s ,
E g →E gs (Forbidden band width in area with small forbidden band width)ε→
By replacing ε s , the electric field strength E n can be calculated by numerical calculation, and the calculated E n can be used for practical purposes.
It will give E T. For example, N L = 1×10 16 cm
-3 , N s = 2 × 10 16 cm -3 , then λ = 1.55 μm
For InGaAsP, l is approximately 1.5 μm or more. In this example, considering the above relationship, l is 1 μm
In the following element design, the wavelength corresponding to the forbidden band width corresponds to 1.3 μm or 1.5 μm.
In a device configuration using InGaAsP as a material with a narrow bandgap, the tunnel effect has a significant effect, making it difficult to create an effective avalanche photodiode. More specifically, as explained above for the photodiode having the structure shown in FIG.

一方、lの上限は別の要因によつて定まる。し
かし、半導体層の構成(組成、厚さ、不純物濃
度、中間層の有無等)、ガードリング効果を得る
ための構成(エツヂ降伏防止策)、素子特性の目
標設定値(雑音、応答速度、量子効率、増倍率
等)等の種々の要因により、その各々に対してl
の上限値は異なるため、先に説明したlの下限値
のように一意的には定まらない。
On the other hand, the upper limit of l is determined by another factor. However, the structure of the semiconductor layer (composition, thickness, impurity concentration, presence or absence of an intermediate layer, etc.), the structure to obtain the guard ring effect (measures to prevent edge breakdown), and the target set values of device characteristics (noise, response speed, quantum Due to various factors such as efficiency, multiplication factor, etc.,
Since the upper limit value of l is different, it is not uniquely determined like the lower limit value of l explained earlier.

参考のために、要因の一つであるヘテロ界面に
おけるキヤリアのパイルアツプ効果について例示
する。第4図で例示した、第1の導電型がn-
第2の導電型がP+の場合、入射光が第1の領域
(禁止帯幅が小である、光吸収領域)で吸収され
て発生した電子−ホール対のうち、ホールが電界
によつてPn接合に向かつて移動する。第1の領
域(禁止帯幅が小)と第2の領域(禁止帯幅が
大)の界面では、禁止帯幅が異なることによつて
バンドの不連続段差(ヘテロ障壁)が生じ、ホー
ルの移動が阻害される。ある程度ホールがたまる
までこの段差を越えて移動することが困難になる
現象が発生し、これはホールのパイルアツプ効果
と呼ばれている。この現象は素子特性の応答速度
と雑音特性に影響する。ホールが段差を越えるた
めにはエネルギーが必要であり、この場合エネル
ギーは電界によつて与えられるため、ヘテロ界面
の電界強度EH(第4図bのE2に相当)はある値以
上であることが必要となる。この必要な値はヘテ
ロ界面の中間層の有無及び半導体層の構成(組
成、層数等)等によつて異なる。NLとεLは第2
の領域に用いる半導体によつて定まるが、EnL
ガードリング効果を得るための構成等によつて変
化するため、EHとlとの関係を一律に言うこと
ができない。これまで説明してきたInP−
InGaAsP系の材料の例において、具体的数字の
一例を示すと、先に導いた式 E2=EnLqlNL/εL を使用し、前述したNL=1×1016cm-3の例の場合
をとるとき、EnL=4.5×105V/cmで、EH=2×
105V/cmのとき、lは約1.7μm、EnL=5×
105V/cmで、EH=1×105V/cmのとき、lは約
2.8μmになる。
For reference, the carrier pile-up effect at the hetero interface, which is one of the factors, will be exemplified. The first conductivity type illustrated in FIG. 4 is n - ,
When the second conductivity type is P + , among the electron-hole pairs generated when the incident light is absorbed in the first region (a light absorption region with a small forbidden band width), the hole is It moves toward the Pn junction. At the interface between the first region (small forbidden band width) and the second region (large forbidden band width), a discontinuous band step (hetero barrier) occurs due to the difference in forbidden band width, and the hole Movement is inhibited. A phenomenon occurs in which it becomes difficult to move over this level difference until a certain amount of holes accumulate, and this phenomenon is called the hole pile-up effect. This phenomenon affects the response speed and noise characteristics of the device. Energy is required for the hole to cross the step, and in this case the energy is given by the electric field, so the electric field strength E H (corresponding to E 2 in Figure 4b) at the heterointerface is greater than a certain value. This is necessary. This required value differs depending on the presence or absence of an intermediate layer at the heterointerface, the structure of the semiconductor layer (composition, number of layers, etc.), and the like. N L and ε L are the second
However, since E nL changes depending on the configuration for obtaining the guard ring effect, etc., the relationship between E H and l cannot be stated uniformly. InP− that has been explained so far
In the example of InGaAsP-based materials, to give an example of specific numbers, using the equation derived earlier E 2 = E nLql N LL , the aforementioned N L = 1×10 16 cm -3 When taking the example case, E nL = 4.5×10 5 V/cm and E H = 2×
At 10 5 V/cm, l is approximately 1.7 μm, E nL = 5×
10 5 V/cm, and when E H = 1×10 5 V/cm, l is approximately
It becomes 2.8μm.

を作成する場合には、動作時の最大電界は小さく
なるものの、禁止帯幅の小さい領域の不純物濃度
には制限が必要となる。禁止帯幅の小さい領域で
空乏層がW広がると、禁止帯幅が大きい物質側の
禁止帯幅の小さい物質の電界強度Esは次式で与え
られる。
, the maximum electric field during operation becomes smaller, but it is necessary to limit the impurity concentration in the region where the forbidden band width is small. When the depletion layer widens by W in the region where the forbidden band width is small, the electric field strength E s of the material with the small forbidden band width on the side of the material with the large forbidden band width is given by the following equation.

Es=qNs/εsW (5) 空乏層が(l+W)であり、Wが1μmとすると
EsがETを越えない様にするためには、不純物濃
度Nsは下記の値よりも小さくする必要が生じる。
E s = qN s / ε s W (5) If the depletion layer is (l + W) and W is 1 μm, then
In order to prevent E s from exceeding E T , the impurity concentration N s needs to be smaller than the value below.

Ns:≦約1×1016cm-3 forλ=1.55μm ≦約2×1016cm-3 forλ=1.3μm 上述の如く、物質のEgとNsとの関係を考慮す
る必要がある。化合物半導体では、Siと比べて光
励起キヤリアの寿命が極めて短いため、光電変換
効率を上げるためには、光吸収領域は空乏層化す
る必要があること、及び高速化を図るためには、
接合容量Cを小さくするため、空乏層を拡げる必
要がある。接合容量は近似的に次式で与えられ
る。
N s :≦approximately 1×10 16 cm −3 forλ=1.55 μm ≦approximately 2×10 16 cm −3 forλ=1.3 μm As described above, it is necessary to consider the relationship between E g and N s of the substance. In compound semiconductors, the lifetime of photoexcited carriers is extremely short compared to Si, so in order to increase the photoelectric conversion efficiency, the light absorption region must be made into a depletion layer, and in order to increase the speed,
In order to reduce the junction capacitance C, it is necessary to expand the depletion layer. Junction capacitance is approximately given by the following equation.

Cε/l+WS (6) ε:誘電率, S:接合面積 実用上要請される量子効率(≧50%)、及び接
合容量(≦2pF)を考えると、空乏層Wが1μm程
度拡がることは必要と考えられる。
Cε/l+WS (6) ε: dielectric constant, S: junction area Considering the practically required quantum efficiency (≧50%) and junction capacitance (≦2pF), it is not necessary for the depletion layer W to expand by about 1 μm. Conceivable.

本発明の代表例を第2図に示す。第1の特徴は
能動領域となる禁止帯幅の小さい物質層13の上
に光の窓層となる禁止帯幅の大きい物質層14を
形成し、更に、14の物質の組成原子を含んだ多
原子の物質層15を形成し、表面保護膜17で保
護することによつて、半導体と界面との間の安定
化を図ることにより、暗電流の低下、並びに界面
安定化を図つた受光素子構造を特徴とする。
A typical example of the present invention is shown in FIG. The first feature is that a material layer 14 with a large bandgap width, which serves as an optical window layer, is formed on a material layer 13 with a small bandgap width, which serves as an active region, and furthermore, a material layer 14 with a large bandgap width, which serves as an optical window layer, is formed. A light-receiving element structure that reduces dark current and stabilizes the interface by forming an atomic material layer 15 and protecting it with a surface protection film 17 to stabilize the relationship between the semiconductor and the interface. It is characterized by

また、第2の特徴はこれまで説明してきたよう
に領域14の物質と領域13の物質の不純物濃度
N14とN13の間にN14≧N13の関係があり、N13
2×1016cm- 3以下にすることを特徴とした受光素
子構造を特徴とする。
Furthermore, as explained above, the second feature is the impurity concentration of the material in region 14 and the material in region 13.
The light-receiving element structure is characterized in that there is a relationship between N 14 and N 13 such that N 14 ≧N 13 , and N 13 is set to be 2×10 16 cm -3 or less .

本発明による実施例の一つを第2図に示し、そ
の構造を以下に説明する。
One embodiment according to the present invention is shown in FIG. 2, and its structure will be described below.

約1018cm-3以上の高不純物濃度のn+形InP基板、
11,上に公知の液相エピタキシヤル成長法によ
り不純物濃度が9×1015cm-3,厚さ1.5μmのn形
InP層、12,を形成し、続いて不純物濃度が7×
1015cm-3,厚さ1.3μmのn形In0.61Ga0.39AS0.83P0.17
層、13,を形成する。特に1.3μm以上の波長の
光を受光を十分な感度で受光せしめるために、こ
のIn1-xGaxAsyP1-yは0.47≧x≧0.25の組成が好ま
しい。なお、As含有量は一般にGaの含有量に伴
なつて決定される。
n + type InP substrate with high impurity concentration of approximately 10 cm -3 or more,
11, an n-type film with an impurity concentration of 9×10 15 cm -3 and a thickness of 1.5 μm was grown using a known liquid phase epitaxial growth method.
An InP layer, 12, is formed, followed by an impurity concentration of 7×
10 15 cm -3 , 1.3μm thick n-type In 0.61 Ga 0.39 AS 0.83 P 0.17
A layer 13 is formed. In particular, in order to receive light with a wavelength of 1.3 μm or more with sufficient sensitivity, the composition of this In 1-x Ga x As y P 1-y is preferably 0.47≧x≧0.25. Note that the As content is generally determined in conjunction with the Ga content.

y=x/0.48043+0.00327x の関係式が存在する。引続いて不純物濃度が9×
1015cm-3,厚さ1.8μmのn形InP層14,を形成し、
最後に、不純物濃度7×1015cm-3,厚さ0.2μmの
n形In0.9Ga0.1As0.2P0.8層、15,を連続的に形成
する。Al2O3及びSiO2膜を公知の気相化学反応法
によつて形成した後、公知の選択ホトエツチング
法によつて不心要部のAl2O3及びSiO2膜を除去し
た後更に領域15を除去し、上記絶縁物を拡散マ
スクとして公知の拡散法によつて、Znあるいは
Cd不純物を上記領域14及び15中に導入し、
拡散深さ0.7μmのP+形の拡散領域、16,を形成
する。拡散層、16,とInP層、14,によつて
pn接合が形成される。pn接合面と領域、13,
との間隔は1.1μmである。次に拡散マスクとして
用いた絶縁膜を除去した後、公知の方法によつて
SiO2膜を形成する。公知の選択的ホトエツチン
グ法によつて、不用部のSiO2を除去した後、表
面保護面膜、17が得られる。尚、反射防止膜1
7′,は表面保護膜を適用するか、あるいは、反
射防止膜として適した厚さのSiO2あるいはSi3N4
を再度形成して適用した。この後表面電極、1
8,及び裏面電極、19を形成した。本素子は適
切なステムにマウントされ、素子としての動作が
認められた。
There is a relational expression: y=x/0.48043+0.00327x. Subsequently, the impurity concentration is 9×
10 15 cm -3 and a thickness of 1.8 μm n-type InP layer 14 was formed,
Finally, an n-type In 0.9 Ga 0.1 As 0.2 P 0.8 layer 15 having an impurity concentration of 7×10 15 cm -3 and a thickness of 0.2 μm is continuously formed. After forming Al 2 O 3 and SiO 2 films by a known gas phase chemical reaction method, removing the Al 2 O 3 and SiO 2 films at inconsequential parts by a known selective photoetching method, further areas are formed. 15 is removed, and using the above insulator as a diffusion mask, Zn or
introducing Cd impurities into the regions 14 and 15;
A P + type diffusion region, 16, with a diffusion depth of 0.7 μm is formed. By the diffusion layer, 16, and the InP layer, 14.
A pn junction is formed. p-n junction surface and region, 13,
The distance between the two is 1.1 μm. Next, after removing the insulating film used as a diffusion mask, the
Form a SiO 2 film. After removing unnecessary portions of SiO 2 by a known selective photoetching method, a surface protective film 17 is obtained. In addition, anti-reflection film 1
7', apply a surface protective film or apply SiO 2 or Si 3 N 4 of a thickness suitable as an anti-reflection film.
was re-formed and applied. After this surface electrode, 1
8, and a back electrode 19 were formed. The device was mounted on an appropriate stem and was found to work as a device.

以下に本実施例の構成及び動作を説明する。本
実施例では、禁止帯幅狭い領域13が禁止帯幅の
広い領域によつて囲まれているため、入射光は領
域13中で吸収される構成となつている。また、
表面層は禁止帯幅の広いInGaAsP層で形成され、
その上に表面保護用の絶縁膜が形成されているた
め、界面での特性が安定となり、暗電流の低減に
好適である。この表面層の半導体層はこの下層の
第2の半導体層と(1)格子整合をとり得る、(2)定じ
結晶系をとり得る、(3)高温にさらされても第2の
半導体層よりも安定である等の性質を持つ。又、
この表面層は、能動領域の半導体材料よりバン
ド・ギヤツプを大なる組成を選択する。また、
pn接合は前述した考えに基づいて領域13より
離れて形成されていると共に、不純物濃度分布も
配慮されているため、ハードな接合特性を維持
し、かつ、光励起キヤリアを効率良く接合へ集め
るのに適している。また、電界分布を考慮して空
乏層の広がりを設定してあるため、接合容量を低
減し、高速化に適している。
The configuration and operation of this embodiment will be explained below. In this embodiment, since the narrow forbidden band width region 13 is surrounded by the wide forbidden band width region, the incident light is absorbed in the region 13. Also,
The surface layer is formed of an InGaAsP layer with a wide forbidden band width.
Since an insulating film for surface protection is formed thereon, the characteristics at the interface become stable, which is suitable for reducing dark current. This surface layer semiconductor layer can (1) have lattice matching with the underlying second semiconductor layer, (2) have a fixed crystal system, and (3) remain stable even when exposed to high temperatures. It has properties such as being more stable than or,
This surface layer is selected to have a composition that has a larger band gap than the semiconductor material of the active region. Also,
The pn junction is formed at a distance from the region 13 based on the above-mentioned idea, and the impurity concentration distribution is also taken into consideration, so that it is possible to maintain hard junction characteristics and efficiently collect optically excited carriers to the junction. Are suitable. Furthermore, since the spread of the depletion layer is set in consideration of the electric field distribution, the junction capacitance is reduced and it is suitable for high speed.

本素子を逆方向にバイアスすると、空乏層は接
合直下の領域14及び領域13に広がる。このた
め、領域13の禁止帯幅に対応した長波長端の光
波長まで効率良く吸収し、発生した正孔はドリフ
ト電界によつてpn接合に集められる。本試作pin
ホトダイオードの主な特性は、波長感度領域1.0
〜1.55μm,量子効率65%(1.3μm)接合容量
0.8pF,暗電流は0.1nA(10V)以下である。
When the device is biased in the reverse direction, the depletion layer spreads to regions 14 and 13 just below the junction. Therefore, light wavelengths up to the long wavelength end corresponding to the forbidden band width of the region 13 are efficiently absorbed, and the generated holes are collected in the pn junction by the drift electric field. Main prototype pin
The main characteristics of the photodiode are the wavelength sensitivity range 1.0
~1.55μm, quantum efficiency 65% (1.3μm) junction capacitance
0.8pF, dark current less than 0.1nA (10V).

本実施例の効果を以下に説明する。 The effects of this embodiment will be explained below.

(a) InGaAsP層と絶縁膜との界面特性を用いる
ことにより、暗電流の低減できる。
(a) Dark current can be reduced by using the interface characteristics between the InGaAsP layer and the insulating film.

(b) 前述した様な層構成にすることにより、トン
ネル効果による暗電流の増大を防止できる。
(b) By forming the layer structure as described above, it is possible to prevent an increase in dark current due to the tunnel effect.

(c) 前述した様な層構成にすることにより、光励
起キヤリアを効率良く接合に集めることがで
き、高感度化できる。
(c) By forming the layer structure as described above, optically excited carriers can be efficiently collected at the junction, resulting in high sensitivity.

(d) 前述した様な層構成にすることにより、光励
起キヤリアをドリフト速度で接合へ集めること
ができ、高速化できる。
(d) By forming the layer structure as described above, the optically excited carriers can be collected at the junction at a drift speed, and the speed can be increased.

(e) 前述した様な層構成とすることにより、空乏
層幅を広くとることができるため、接合容量を
小さくでき、素子の高速化に効果がある。
(e) By forming the layer structure as described above, the width of the depletion layer can be increased, so that the junction capacitance can be reduced, which is effective in increasing the speed of the device.

別の実施例として光の入射方向をInP基板側と
した場合がある。第3図はこの例を示す装置断面
図である。第2図と同一符号は同一部位を示して
いる。層15が表面保護のためのInGaAsP層で
ある。第2図における実施例との相違点は電極1
9が拡散領域16の下部に位置する領域の金属を
除去する点、および電極18は入射光不要のため
全面に設けられている。である。
As another example, there is a case where the incident direction of light is set to the InP substrate side. FIG. 3 is a sectional view of the device showing this example. The same symbols as in FIG. 2 indicate the same parts. Layer 15 is an InGaAsP layer for surface protection. The difference from the embodiment in FIG. 2 is that the electrode 1
9 removes the metal in the region located below the diffusion region 16, and the electrode 18 is provided over the entire surface since no incident light is required. It is.

また、上述の例としてInP−InGaAsP系材料の
例を説明したが、材料系はこれに限られるもので
はない。
Moreover, although the example of the InP-InGaAsP-based material has been described as an example above, the material system is not limited to this.

たとえば、14層としてGaAlSb,13層とし
てaSb12層としてGaSb,15層として
GaAlAsSbを用いるGaSbを主体とした材料系を
用いても同様の趣旨の光半導体装置が実現出来
る。
For example, the 14th layer is GaAlSb, the 13th layer is aSb, the 12th layer is GaSb, and the 15th layer is GaSb.
An optical semiconductor device having the same purpose can be realized using a material system mainly composed of GaSb using GaAlAsSb.

本発明によれば、pn接合と光吸収領域との距
離、素子を構成する各層の不純物濃度、各層の厚
さをアバランシエ増倍作用が効果的に生起するよ
うに考慮しているので高感度で暗電流の小さい高
速性を有する受光素子を得ることができる。
According to the present invention, the distance between the pn junction and the light absorption region, the impurity concentration of each layer constituting the device, and the thickness of each layer are taken into consideration so that avalanche multiplication effect occurs effectively, resulting in high sensitivity. A light receiving element with low dark current and high speed can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の素子構造例を示す断面図であ
り、(a)はメサ型、(b)はプレーナ型構造を示す。第
2図および第3図は本発明による一実施例の素子
構造の断面図を示す。第4図はアバランシエ型フ
オトダイオードのpn接合の近傍を模止的に示す
図であり、(a)は断面図、(b)は(a)に示すA−A′断
面における電界強度を示す。 符号の説明、01…n+型InP基板、02…n型
InGaAs、03…P形InGaAs、08,09…電
極、1,11…n+形InP基板、2…n+形InP層、
12…n形InP層、3,13…n形InGaAsP層、
4,14…n形InP層、6,16…P形InGaAsP
拡散層、7,17,17′…絶縁膜、15…n形
InGaAsP層、8,18…P形電極、9,19…
n形電極。
FIG. 1 is a cross-sectional view showing an example of a conventional element structure, in which (a) shows a mesa type structure and (b) shows a planar type structure. FIGS. 2 and 3 show cross-sectional views of an element structure according to an embodiment of the present invention. FIG. 4 is a diagram schematically showing the vicinity of a pn junction of an avalanche type photodiode, in which (a) is a cross-sectional view, and (b) is a diagram showing the electric field strength in the A-A' cross section shown in (a). Explanation of symbols, 01...n + type InP substrate, 02...n type
InGaAs, 03...P type InGaAs, 08,09...electrode, 1,11...n + type InP substrate, 2...n + type InP layer,
12... n-type InP layer, 3, 13... n-type InGaAsP layer,
4, 14... n-type InP layer, 6, 16... p-type InGaAsP
Diffusion layer, 7, 17, 17'...insulating film, 15...n type
InGaAsP layer, 8, 18...P-type electrode, 9, 19...
n-type electrode.

Claims (1)

【特許請求の範囲】 1 基板と、この基板上に設けられた半導体積層
構造体と、この半導体積層構造体に電気的に接続
する1組の電極とを有し、上記半導体積層構造体
は第1の導電型を示す禁止帯幅の小さい第1の領
域と、この第1の領域よりも禁止帯幅が広く第1
の導電型を示す第2の領域と、上記第2の領域内
に選択的に設けられ上記第2の領域内部にPn接
合を形成するための第2の導電型を示す領域とを
有し、上記第1の領域及び上記第2の領域の不純
物濃度及び、誘電率をNs、εs、及びNL,εL、上
記第1の領域の不純物濃度Nsに依存する上記第
1の領域のトンネル降伏時の電界強度をET、上
記第2の領域の最大電界強度をEnL、電気素量を
qとしたとき、上記Pn接合と上記第1の領域の
距離lが l≧εL/qNL{EnL−εs/εLET} の関係を満足することを特徴とする光半導体装
置。 2 特許請求の範囲第1項に記載の光半導体装置
において、前記第1の領域の不純物濃度は2×
1016cm-3以下であることを特徴とする光半導体装
置。
[Scope of Claims] 1. A semiconductor multilayer structure comprising a substrate, a semiconductor multilayer structure provided on the substrate, and a set of electrodes electrically connected to the semiconductor multilayer structure, wherein the semiconductor multilayer structure has a a first region with a small forbidden band width indicating conductivity type 1, and a first region with a wider forbidden band width than this first region.
a second region exhibiting a conductivity type; and a region exhibiting a second conductivity type selectively provided within the second region for forming a Pn junction within the second region; The impurity concentration and dielectric constant of the first region and the second region are N s , ε s , and N L , ε L , and the first region depends on the impurity concentration N s of the first region. When the electric field strength at the time of tunnel breakdown is E T , the maximum electric field strength in the second region is E nL , and the elementary charge is q, the distance l between the Pn junction and the first region is l≧ε L An optical semiconductor device characterized by satisfying the relationship: /qN L {E nL −ε sL E T }. 2. In the optical semiconductor device according to claim 1, the impurity concentration of the first region is 2×
10 16 cm -3 or less.
JP56156282A 1981-10-02 1981-10-02 Photo semiconductor device Granted JPS5857760A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP56156282A JPS5857760A (en) 1981-10-02 1981-10-02 Photo semiconductor device
KR8204346A KR900000074B1 (en) 1981-10-02 1982-09-27 Beam-checking semiconductor apparatus
EP82109103A EP0076495B1 (en) 1981-10-02 1982-10-01 Photodiode
DE8282109103T DE3277353D1 (en) 1981-10-02 1982-10-01 Photodiode
US06/880,118 US4740819A (en) 1981-10-02 1986-06-30 Photo semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56156282A JPS5857760A (en) 1981-10-02 1981-10-02 Photo semiconductor device

Publications (2)

Publication Number Publication Date
JPS5857760A JPS5857760A (en) 1983-04-06
JPH0420274B2 true JPH0420274B2 (en) 1992-04-02

Family

ID=15624407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56156282A Granted JPS5857760A (en) 1981-10-02 1981-10-02 Photo semiconductor device

Country Status (1)

Country Link
JP (1) JPS5857760A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55132079A (en) * 1979-03-30 1980-10-14 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55132079A (en) * 1979-03-30 1980-10-14 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPS5857760A (en) 1983-04-06

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