JPH042011B2 - - Google Patents
Info
- Publication number
- JPH042011B2 JPH042011B2 JP59127122A JP12712284A JPH042011B2 JP H042011 B2 JPH042011 B2 JP H042011B2 JP 59127122 A JP59127122 A JP 59127122A JP 12712284 A JP12712284 A JP 12712284A JP H042011 B2 JPH042011 B2 JP H042011B2
- Authority
- JP
- Japan
- Prior art keywords
- type mos
- enhancement type
- mos transistor
- circuit
- threshold voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 12
- 230000000087 stabilizing effect Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59127122A JPS615623A (ja) | 1984-06-20 | 1984-06-20 | 多値論理回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59127122A JPS615623A (ja) | 1984-06-20 | 1984-06-20 | 多値論理回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS615623A JPS615623A (ja) | 1986-01-11 |
| JPH042011B2 true JPH042011B2 (enrdf_load_stackoverflow) | 1992-01-16 |
Family
ID=14952148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59127122A Granted JPS615623A (ja) | 1984-06-20 | 1984-06-20 | 多値論理回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615623A (enrdf_load_stackoverflow) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62204498A (ja) * | 1986-03-04 | 1987-09-09 | Omron Tateisi Electronics Co | 多値メモリ |
| JPS6342221A (ja) * | 1986-08-07 | 1988-02-23 | Yukio Yasuda | ダイナミツク型多値回路 |
| JP4288355B2 (ja) * | 2006-01-31 | 2009-07-01 | 国立大学法人北陸先端科学技術大学院大学 | 三値論理関数回路 |
-
1984
- 1984-06-20 JP JP59127122A patent/JPS615623A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS615623A (ja) | 1986-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR930006843B1 (ko) | 반도체 집적회로 | |
| US5777491A (en) | High-performance differential cascode voltage switch with pass gate logic elements | |
| EP0239059B1 (en) | Logical circuit | |
| KR940010669B1 (ko) | Mos 트랜지스터와 바이폴라 트랜지스터를 구비한 반도체장치 | |
| GB2156614A (en) | A switching circuit | |
| KR100214195B1 (ko) | 필드 프로그램가능 게이트 어레이 및 그 방법 | |
| US5075579A (en) | Level shift circuit for achieving a high-speed processing and an improved output current capability | |
| US5446700A (en) | Decoder circuit having CMOS inverter circuits | |
| US8306178B2 (en) | vMOS multi-valued counter unit | |
| US4962471A (en) | High speed digital carry look ahead circuit for parallel adder | |
| EP0090186B1 (en) | Complementary logic circuit | |
| US4866432A (en) | Field programmable matrix circuit for EEPROM logic cells | |
| JPH06216759A (ja) | 半導体集積回路装置 | |
| JPH042011B2 (enrdf_load_stackoverflow) | ||
| US5359553A (en) | Low power ECL/MOS level converting circuit and memory device and method of converting a signal level | |
| US4482822A (en) | Semiconductor chip selection circuit having programmable level control circuitry using enhancement/depletion-mode MOS devices | |
| US5136293A (en) | Differential current source type d/a converter | |
| US20200295761A1 (en) | Reconfigurable circuit and the method for using the same | |
| US4489399A (en) | Read-only memory device | |
| US4309629A (en) | MOS Transistor decoder circuit | |
| US5157283A (en) | Tree decoder having two bit partitioning | |
| US4900954A (en) | Mixed CML/ECL macro circuitry | |
| US4935646A (en) | Fully static CMOS cascode voltage switch logic systems | |
| US4631425A (en) | Logic gate circuit having P- and N- channel transistors coupled in parallel | |
| US5182472A (en) | Logic circuit with bipolar CMOS configuration |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |