JPH04199835A - Semiconductor assembly device - Google Patents
Semiconductor assembly deviceInfo
- Publication number
- JPH04199835A JPH04199835A JP2336196A JP33619690A JPH04199835A JP H04199835 A JPH04199835 A JP H04199835A JP 2336196 A JP2336196 A JP 2336196A JP 33619690 A JP33619690 A JP 33619690A JP H04199835 A JPH04199835 A JP H04199835A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- semiconductor chip
- matching circuit
- computer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000005259 measurement Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 abstract description 6
- 238000004904 shortening Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01072—Hafnium [Hf]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体チップと整合回路の間及び整合回路間
をワイヤポンドする半導体組立装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor assembly apparatus for bonding wires between a semiconductor chip and a matching circuit and between matching circuits.
第２図は従来の整合回路を有する半導体装置を組立てる
半導体組立装置を示す説明図である。FIG. 2 is an explanatory diagram showing a semiconductor assembly apparatus for assembling a semiconductor device having a conventional matching circuit.
図において、（１）は半導体装置、（２）は半導体チッ
プ、（３）は半導体チップの電気的特性を良好にするた
めの整合回路、（４ａ） （４ｂ）は半導体チップと整
合回路を接続するためのワイヤ、（５）はワイヤ（４ａ
）（４ｂ）をポンディングするためのワイヤホンダ−で
ある。In the figure, (1) is a semiconductor device, (2) is a semiconductor chip, (3) is a matching circuit to improve the electrical characteristics of the semiconductor chip, and (4a) and (4b) are connections between the semiconductor chip and the matching circuit. (5) is the wire (4a
) (4b) is a wire honda for pounding.
次に従来の組立方法について説明する。Next, a conventional assembly method will be explained.
半導体装置（１）における半導体チップ（２）と整合回
路（３）はワイヤ（４ａ）（４ｂ）で接続されている。A semiconductor chip (2) and a matching circuit (3) in a semiconductor device (1) are connected by wires (4a) and (4b).
このワイヤ（４ａ） （４ｂ）は整合回路（３）と半導
体チップ（２）の構造的な位置関係のみて、ワイヤホン
ダ−（５）によりボンディングされていた。The wires (4a) and (4b) were bonded using a wire honda (5) based only on the structural positional relationship between the matching circuit (3) and the semiconductor chip (2).
従来の半導体組立装置は以上のように構成されていたの
で、半導体チップの高周波特性かチップ間でばらついて
いる場合、後工程でその都度手作業によって作業者（人
間）かワイヤカット又は追 ゛加ワイヤポンドを行うこ
とにより最適整合回路にしなければならないという問題
点かあった。Conventional semiconductor assembly equipment was configured as described above, so if the high frequency characteristics of semiconductor chips vary between chips, the operator (human) manually cuts or adds wires each time in the post-process. There was a problem in that an optimal matching circuit had to be created by wire pounding.
この発明は上記のような問題点を解消するためになされ
たもので、ワイヤポンド工程のみで各半導体チップに対
する最適整合回路を形成することができる半導体組立装
置を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor assembly apparatus that can form an optimal matching circuit for each semiconductor chip using only a wire bonding process.
この発明に係る半導体組立装置は、半導体チップ高周波
特性を測定するネットワークアナライザとコンピュータ
により、ワイヤボンダーのワイヤボンド位置を制御する
ようにしたものである。A semiconductor assembly apparatus according to the present invention is configured to control the wire bond position of a wire bonder using a network analyzer that measures semiconductor chip high frequency characteristics and a computer.
この発明におけるネットワークアナライザとコンピュー
タは、半導体チップ高周波特性を抽出し最適整合回路形
成のためのワイヤボンド位置を算出し、ワイヤボンダー
を制御し、またコンピュータ自身がプログラム的に学習
することにより、スピードが早く適性な整合回路の最適
化が図れる。The network analyzer and computer in this invention extract high-frequency characteristics of semiconductor chips, calculate wire bond positions for forming optimal matching circuits, control wire bonders, and speed up by learning programmatically by the computer itself. A suitable matching circuit can be optimized quickly.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図において、（１）は半導体装置、（２）は半導体
チップ、（３）は半導体チップの電気的特性を良好にす
るための整合回路、（４ａ）（４ｂ）は半導体チップと
整合回路を接続するだめのワイヤ、（５）はワイヤ（４
ａ） （４ｂ）をボンディングするワイヤボンダー、（
６）はネットワークアナライザで、高周波特性測定回路
（７）と接続されている。（８）はコンピュータで、デ
ータバス（９）によりネットワークアナライザ（６）と
、コントロールバスα０）によりワイヤホンダ−（５）
と接続されている。In Figure 1, (1) is a semiconductor device, (2) is a semiconductor chip, (3) is a matching circuit for improving the electrical characteristics of the semiconductor chip, and (4a) and (4b) are the semiconductor chip and matching circuit. The wire (5) is the one that connects the wire (4).
a) A wire bonder for bonding (4b), (
6) is a network analyzer, which is connected to the high frequency characteristic measuring circuit (7). (8) is a computer, a network analyzer (6) is connected to the data bus (9), and a wire Honda (5) is connected to the control bus α0).
is connected to.
次に動作について説明する。Next, the operation will be explained.
半導体装置（１）は最初ワイヤボンダー（５）によりワ
イヤ（４ａ）をボンディングする。次に、ネットワーク
アナライザ（６）と高周波特性測定回路（７）により、
半導体チップ（２）の高周波特性を抽出する。この高周
波特性をデータバス（９）を通じコンピュータ（８）に
入力し、このコンピュータ（８）により最適整合回路（
３）を形成するためのワイヤボンド位置を算出する。The semiconductor device (1) is first bonded with a wire (4a) by a wire bonder (5). Next, the network analyzer (6) and high frequency characteristic measurement circuit (7)
Extract the high frequency characteristics of the semiconductor chip (2). This high frequency characteristic is input to the computer (8) through the data bus (9), and this computer (8) uses the optimal matching circuit (
3) Calculate the wire bond position for forming.
コントロールバスα０）を通しコンピュータ（８）によ
ってワイヤホンダ−（５）を制御させることにより、半
導体チップ（２）と整合回路（３）の間及び整合回路間
にワイヤ（４ｂ）をボンディングする。Wires (4b) are bonded between the semiconductor chip (2) and the matching circuit (3) and between the matching circuits by controlling the wire holder (5) by the computer (8) through the control bus α0).
なお、上記実施例では高周波特性測定回路（７）により
ワイヤボンダー（５）を制御する場合を示したか、高周
波特性でなく低周波特性や静特性てあっても良いことは
言うまでもない。Although the above embodiment shows the case where the wire bonder (5) is controlled by the high frequency characteristic measuring circuit (7), it goes without saying that the wire bonder (5) may be controlled by low frequency characteristics or static characteristics instead of the high frequency characteristics.
以上のように、この発明によれば、半導体組立装置に最
適整合回路を形成するための機能を設けたので、従来の
整合調整工程を省くことかでき、この工程削除により品
質が向上するとともに工期の短縮か計れるという効果が
ある。As described above, according to the present invention, since the semiconductor assembly equipment is provided with a function for forming an optimal matching circuit, the conventional matching adjustment process can be omitted, and by eliminating this process, quality is improved and construction time is improved. This has the effect of being able to measure the shortening of
第１図はこの発明の一実施例である半導体組立装置を示
す回路構成ブロック図、第２図は従来の半導体組立装置
を示す回路構成ブロック図である。
図において、（２）は半導体チップ、（３）は整合回路
、（４ａ） （４ｂ）はワイヤ、（５）はワイヤボンダ
ー、（６）はネットワークアナライザー、（７）は高周
波特性測定回路、（８）はコンピュータを示す。
なお、図中、同一符号は同一、又は相当部分を示す。
代 理 人 大 岩 増 雄早１１￥１
１０１１斗ローＩレバスFIG. 1 is a circuit configuration block diagram showing a semiconductor assembly apparatus according to an embodiment of the present invention, and FIG. 2 is a circuit configuration block diagram showing a conventional semiconductor assembly apparatus. In the figure, (2) is a semiconductor chip, (3) is a matching circuit, (4a) (4b) are wires, (5) is a wire bonder, (6) is a network analyzer, (7) is a high frequency characteristic measurement circuit, ( 8) indicates a computer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masu Oiwa Yuhaya 11 yen 1011 Doro I Rebus
Claims (1)
にするための整合回路を有する半導体装置を前記半導体
チップの高周波特性をネットワークアナライザで測定し
、この測定データによってコンピュータ制御されたワイ
ヤボンダーにより最適整合回路を形成することを特徴と
する半導体組立装置。A semiconductor device having a semiconductor chip and a matching circuit for improving the electrical characteristics of the semiconductor chip is manufactured by measuring the high frequency characteristics of the semiconductor chip using a network analyzer, and using this measurement data to create an optimal matching circuit using a computer-controlled wire bonder. A semiconductor assembly device characterized by forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2336196A JPH04199835A (en) | 1990-11-29 | 1990-11-29 | Semiconductor assembly device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2336196A JPH04199835A (en) | 1990-11-29 | 1990-11-29 | Semiconductor assembly device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04199835A true JPH04199835A (en) | 1992-07-21 |
Family
ID=18296638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2336196A Pending JPH04199835A (en) | 1990-11-29 | 1990-11-29 | Semiconductor assembly device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04199835A (en) |
-
1990
- 1990-11-29 JP JP2336196A patent/JPH04199835A/en active Pending
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