JP3082319B2 - Test method for semiconductor chip - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of testing a semiconductor chip for testing electrical characteristics of the semiconductor chip by using a test board.

When a semiconductor chip such as an LSI element is directly mounted on a substrate, an electrical characteristic test for each semiconductor chip is usually performed, and a semiconductor chip which is a good product as a result of the test is mounted on the substrate. .

[0003] Such mounting is performed by forming a bump on a terminal portion of a semiconductor chip and bonding the bump to a pad of a substrate to be mounted.

[0004]

2. Description of the Related Art Conventionally, this has been performed as shown in the conventional explanatory diagram of FIG. Fig. 4 (a) is an explanatory diagram of the test method, and (b1) ~
(b3) is a mounting process diagram.

[0005] As shown in FIG.
Is placed on a table 12, a probe head 10 provided with a probe pin 11 is positioned just above the semiconductor chip 1,
The probe head 10 is lowered as shown by the arrow, and a predetermined test signal is transmitted and received from the tester 6 by bringing the probe pin 11 into contact with the terminal portion 2 of the semiconductor chip 1. It was done.

The bumps 3 are formed on the respective terminal portions 2 of the semiconductor chip 1 determined to be non-defective by the test of the electrical characteristics, as shown in (b1). In this case, the bump 3 is usually formed by fusing gold Au with a bump tool or by bonding a gold foil having a predetermined thickness by diffusion bonding.

Further, a semiconductor chip on which bumps 3 are formed
1 is a bump 3 formed on the terminal 2 as shown in (b2).
The tip 3A is overlapped so as to be in contact with the glass plate 13 and pressed by a predetermined pressure P to adjust the smoothness so that the tip 3A is smooth.

The semiconductor chip 1 with the tip 3A of the bump 3 smoothed in this way is positioned on a predetermined pad 15 of the substrate 14 to be mounted as shown in FIG. By applying ultrasonic or vibration, bump 3
Bonding for diffusion bonding of the front end 3A to the pad 14 has been performed.

Therefore, a semiconductor chip whose test has been completed
First, bump 3 is formed, and the substrate is
Implementation for 14 was done.

[0010]

However, each of the semiconductor chips 1 is tested, and after the test, bumps 3 are formed on the respective terminal portions.
Adjusting the smoothness of 3A and performing bonding to the substrate 14 requires a lot of man-hours when the amount of the semiconductor chip 1 to be mounted becomes enormous.

Therefore, when the semiconductor chip 1 is mounted on the substrate, there is a problem that a very large number of work steps including a test step are required. Therefore, an object of the present invention is to reduce the number of working steps by simultaneously adjusting the smoothness of the bumps at the time of the test.

[0012]

FIG. 1 is a diagram illustrating the principle of the present invention. As shown in FIG. 1, a semiconductor chip 1 in which bumps 3 are formed in a terminal portion 2 to which signals are input and output, and the terminal portion
A test board 4 on which pads 5 corresponding to 2 are formed;
A tester 6 connected to the test board 4 and testing the electrical characteristics of the semiconductor chip 1 via the pad 5; and pressing the semiconductor chip 1 so that the bump 3 is pressed against the pad 5. To make the tip 3A of the bump 3
The adjustment of the smoothness and the electrical characteristic test of the semiconductor chip 1 are simultaneously executed.

The above-mentioned configuration solves the above-mentioned problem.

[0014]

[Operation] That is, the semiconductor chip 1 is pressed against the test board 4 so that the bumps 3 formed on the terminal portions 2 of the semiconductor chip 1 are pressed against the pads 5 of the test board 4, and the bumps 3
In addition to the adjustment of the smoothness of the tip 3A, the electrical characteristics of the semiconductor chip 1 are tested by the tester 6.

Therefore, by previously forming the bumps 3 on the terminal portions 2 of the semiconductor chip 1 before conducting the test, the conventional process of adjusting the smoothness of the tip 3A of the bumps 3 becomes unnecessary, and the work is not required. The man-hour can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to FIGS. FIG. 2 is an explanatory view of an embodiment according to the present invention, and FIGS. 3A to 3C are mounting process diagrams of the present invention. Throughout the drawings, the same reference numerals indicate the same objects.

As shown in FIG. 2, the semiconductor chip 1 is positioned by being held by a suction head 7 on a test board 4 provided with pads 5 corresponding to the terminal portions 2 of the semiconductor chip 1. The semiconductor chip 1 having the bumps 3 formed thereon is pressed against the test board 4 by a predetermined pressure P.

A connector 8 is fixed to the test board 4, and a pattern wiring 4 A for connecting the pad 5 and the connector 8 is provided. A test signal from the tester 6 is transmitted to the connector 8 via the cable 9. It is formed so as to be connected and further transmitted and received to and from the pad 5 via the pattern wiring 4A.

Then, the terminal 2 is connected to the pad 5 via the bump 3 to test the electrical characteristics of the semiconductor chip 1. At the same time, the bump 3 is applied to each pad 5 by a predetermined pressure P. The tip 3A is brought into contact with the tip 3A, and the smoothness of the tip 3A is adjusted.

Therefore, when testing the semiconductor chip 1, as shown in FIG.
The bumps 3 are formed on the terminal portions 2 of the semiconductor chip 1, and then the semiconductor chip 1 on which the bumps 3 are formed is pressed against the test board 4 as shown in FIG. , And the adjustment of the smoothness of the tip 3A at the same time,
After the test, as shown in FIG.
The step of pressing the semiconductor chip 1 on which the bumps 3 are formed as shown in (b2) of FIG. 4 against the glass plate 13 is not required, and the number of steps can be reduced.

[0021]

As described above, according to the present invention,
The test of the electrical characteristics and the adjustment of the smoothness of the bumps can be performed simultaneously by pressing the semiconductor chip on which the bumps have been formed on the terminals in advance on the test board and testing the electrical characteristics with the test board. Can be.

Therefore, the step of adjusting the smoothness of the bump, which is performed after the formation of the conventional bump, becomes unnecessary, and the cost can be reduced by reducing the number of steps, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory view of an embodiment according to the present invention.

FIG. 3 is a mounting process diagram of the present invention.

FIG. 4 is a conventional explanatory view.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Terminal part 3 Bump 4 Test board 5 Pad 6 Tester 3A Tip

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-59-154035 (JP, A) JP-A-2-52447 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/26 H01L 21/66

Claims (1)

(57) [Claims] A bump is provided at a terminal (2) for inputting and outputting a signal.
(3), a test board (4) on which a pad (5) corresponding to the terminal section (2) is formed, and a test board (4) connected to the test board (4). 5) a tester for testing the electrical characteristics of the semiconductor chip (1) via
(6), and the semiconductor chip (1) is pressed so that the bump (3) is pressed against the pad (5).
(3) Adjustment of the smoothness of the tip (3A) and the semiconductor chip
A method for testing a semiconductor chip, wherein the method further comprises simultaneously executing the electrical characteristic test of (1).