JPH041991A - Redundancy constitution lsi memory - Google Patents

Abstract

PURPOSE:To keep a layout pitch of a spare block decoder within a layout pitch of a spare memory cell array block and to use the area of a redundancy constitution LSI memory efficiently by making the area of the spare memory cell array block large. CONSTITUTION:Plural spare memory cell array blocks YB11 - YB1N are provided for a spare memory cell to relieve a defective memory cell. Thus, even when a large sized fuse is employed for a fuse to program a spare block decoder Y22 selecting the spare memory cell array blocks YB11 - YB1N, since the area of the array blocks YB11 - YB1N is large, the layout pitch of the block decoder Y22 is kept within a layout pitch of the array blocks YB11 - YB1N. Thus, the area of a redundancy constitution LSI memory is used efficiently.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to an LSI memory with redundant configuration.

(Prior art) As the memory capacity of LSI memory increases, the minimum processing size and memory cell area are reduced, making it more likely that memory cells with defective bits will occur, making it difficult to obtain chips with all bits in good condition. It is becoming.

As a means to relieve this defective memory cell and obtain a chip with all bits in good condition, a spare memory cell is mounted, and the memory cell with the defective bit is replaced with the spare memory cell, thereby obtaining a chip with all bits in good condition. is commonly used.

A conventional example of such a redundant LSI memory is the International Conference held in February 1980.

e international solid state circuit
Conferencing (1980 IEE)
EINTERNATIONAL 5OLID-8TAT
E CIRCUITS CONFERENCE) digest, off. technical.

Papers (ISSCCDIGEST OF TECH
NICAL PAPER 8) pages 234-235 (19
“A 2” published in the February 1980 conference
56K RAM Fabricated withMo
lybdenuw-Polysilicon Tech
(Tsuneo Man
There are papers by Mr. o) and others. FIG. 3 shows a block diagram of the redundant LSI memory introduced in the above paper.

The LSI memory in FIG. 3 consists of a memory cell array 11, an X decoder 21, and a Y decoder 3, which are the original memory blocks.
1, a spare column side memory cell array Yll, a row side memory cell array Y12, a spare X decoder Y21, Y
It consists of a decoder circuit 1. In this LSI memory, if there is a defective memory cell in the memory cell array 11, the spare X decoder Y21 or Y decoder 31 is used to replace the spare column side memory cell array Y11 or row side memory cell array Y12. By selecting a spare memory cell in place of a defective memory cell, an LSI memory with all bits in good condition can be obtained. In such a redundant LSI memory, a memory cell having the same area as a normal memory cell is used as a spare memory cell. On the other hand,
In the spare X, Y decoder, a decoder circuit is configured using programmable elements so as to be selected at the same X or Y address as the defective memory cell. An example of a preliminary decoder using a program element is shown in FIG. The preliminary decoder shown in FIG. 4 is an example of a preliminary decoder using a NOR circuit. All address manual signals Ax, Ax are applied to the input transistors of the NOR circuit, and no selection is made in this state. The preliminary decoder is programmed by cutting the fuse connected in series with the drain electrode of the input transistor of the NOR circuit with a laser beam or by electrically blowing it out.

(Problems to be Solved by the Invention) However, in the conventional redundant LSI memory described above, a laser beam or an electrically blowable fuse is used to program the spare X and Y decoders.

Furthermore, these decoder circuits must be arranged at the layout pitch of the spare memory cells. However, LSI
As memory capacity increases from 16M bits to 64M bits, the minimum processing size used will increase from 0.5pm to 0.3pm.
The layout pitch of memory cells is 2~lp.
is about to decrease to m.

However, when a laser beam is used, the area of the fuse used in the preliminary decoder shown in FIG. 4 needs to be approximately 1012 m square in order to ensure the beam spot size. Even when using the electrical fusing method, a layout pitch of several pm or more is required in order to ensure a sufficient fusing area of the material. For this reason, even if the spare memory cell arrays Yll and Y12 are highly integrated using the minimum processing size design rule, the spare decoder circuit cannot be arranged in a high density due to the fuses, and will occupy a large area. Become. For this reason, with the progress of miniaturization of memory cells, the redundant configuration LSI memory has the drawback that a large area is occupied by a spare decoder, resulting in an increase in chip size. Alternatively, although the area of the spare memory cell array is small, only the area of the spare decoder becomes large, creating an unbalanced state, resulting in a disadvantage that the chip area cannot be used effectively.

The purpose of the present invention is to improve these drawbacks and improve redundant LSI configuration.
Even though the address programming fuse used for selecting a spare memory cell array occupies a large area in the memory, the area of the decoder for the spare memory cell array is prevented from increasing, and the chip area is used effectively. Our goal is to provide LSI memory.

(Means for Solving the Problems) A redundant LSI memory of the present invention arranges a plurality of memory cell array blocks having memory cell arrays arranged in a matrix in a matrix, and selects memory cells in the memory cell array. A redundant LSI memory comprising an X decoder, a Y decoder, a block decoder for selecting the memory cell array block, a plurality of spare memory cell array blocks, and a spare block decoder for selecting the spare memory cell array block. .

(Operation) The redundant LSI memory of the present invention has a plurality of spare memory cells as spare memory cell array blocks for relieving defective memory cells. Therefore, even if a large-sized fuse is used as in the past as a fuse for programming a spare block decoder that selects a spare memory cell array block, the area of the spare memory cell array block is large. The layout pitch of the spare block decoder can be accommodated within the layout of the spare memory cell array block, and the area of the redundant LSI memory can be used efficiently. Further, when defective memory cells occur in a group in a memory cell array block, the defective block can be replaced with a spare block in units of memory cell array blocks, so there is an advantage that the defective memory cells can be easily relieved.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a redundant configuration LSI memory showing a first embodiment of the present invention. The LSI memory includes a memory cell array block B consisting of a memory cell array 11, an X decoder 21 and a Y decoder 31 for the memory cell array.
ll, and memory cell array block B21 . ..., BMI, ..., BIJ, ...
BIN, . . . , BMN are arranged in a matrix and X block decoder 22 and Y block decoder 32 are used as block decoders to select these memory cell array blocks, and a spare memory cell array block YBII,
. . , YBIJ, . . . YBIN and a spare X block decoder Y22.

The memory cell array 11 is, for example, a memory cell array arranged in a 512×512 bit matrix.

When the spare memory cell array block is not used, the block decoder address is
and Y block decoder 32 to select one memory cell array block; The signal is applied to a decoder to perform a data read or write operation of the memory cell.

However, if some of the memory cell array blocks Bll to BMN have defective memory cells, the memory cell array block is determined to be a defective memory cell array block, and a spare memory cell array block is selected instead. For example, memory cell array block BI
If J is defective, spare memory cell array block YBIJ is selected instead. In this case, block YB
To select IJ, first disconnect the block selection line of memory cell array block BIJ, and connect the spare X block decoder Y.
22, a programming fuse similar to the conventional example shown in FIG. 4 is blown out with a laser beam or electrically so that the spare memory cell array block YBIJ is selected by the block decoder address that selects the block BIJ. .

In this embodiment, since the memory capacity of the memory cell array block is 256 bits, the area of the block is quite large. For example, minimum processing size 0.5 yen
Approximately 400μm×400 when using a 1m process
It requires an area of pm. Therefore, a block decoder layout pitch of 1100p level is permissible, so a fuse with a large area similar to the conventional one can be used as a fuse for programming the spare block decoder, increasing the area of the spare block decoder. It is possible to prevent wasted chip area from being used.

In this embodiment, a series of blocks in the column direction is shown as a spare memory cell array block, but this may be a cell array block in multiple columns, or a series of blocks in the column direction as a spare memory cell array block. You can also place blocks. In this case, a spare Y block decoder is added. Furthermore, the memory capacity of the memory cell array block can be any bit capacity other than 256 bits.

(Second Embodiment) FIG. 2 is a block diagram of a redundant configuration LSI memory showing a second embodiment of the present invention. The LSI memory is, for example, 5
Memory cell array block Bll, B21. consists of 12×512 bit memory cells. ..., BMI,...
..., BIJ, ...BIN, ..., BMN are arranged in a matrix, and an X block decoder 22 and a Y block decoder 32 serve as block decoders that select these memory cell array blocks, and memory cells in the memory cell array block. X decoder 21 and Y decoder 31, and spare memory cell array block YBII.

..., YBIJ, ..., YBIN, a spare X block decoder Y22, and a spare X decoder Y21. The LSI memory of this embodiment does not have an X decoder and a Y decoder in the memory cell array block as in the embodiment shown in FIG. 21 and a Y decoder 31. Furthermore, the X block decoder 22 and the Y block decoder 32 are also arranged at the same location as the X decoder 21 and the Y decoder 31, overlapping each other.

Reading and writing of data in memory cells when the spare memory cell array block of this LSI memory is not used and when the spare memory cell array block is used is exactly the same as in the first embodiment. In this embodiment as well, the memory capacity of the memory cell array block is 25
Since the size of the cell array block is 6 bits, the area of the cell array block is quite large. Therefore, as a fuse for programming a spare block decoder, a fuse with a large surface IJt as in the past can be used, and redundant configuration LSI Memory area can be used efficiently.

(Effects of the Invention) As described above in detail, the redundant LSI memory of the present invention can be used as a fuse for programming a spare block decoder that selects a spare memory cell array block. Even if a fuse is used, since the area of the spare memory cell array block is large, the layout pitch of the spare block decoder can be kept within the layout pitch of the spare memory cell array block, and the area of the redundant LSI memory can be efficiently reduced. It has advantages and effects if used well.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an LSI memory according to a first embodiment of the present invention, FIG. 2 is a block diagram of an LSI memory according to a second embodiment, and FIG. 3 is a typical block diagram of a conventional redundant LSI memory. FIG. 4 is a circuit diagram showing an example of a preliminary decoder using fuses for programming addresses. 11...Memory cell array, BIJ...Memory cell array block, YBIJ...Spare memory cell array block, 21...X decoder, 31...Y decoder, 22...X block decoder, 32...・Y block decoder, Y21...Spare X decoder, Y2
2...Spare X block decoder.

Claims (1)

[Claims] A plurality of memory cell array blocks having memory cell arrays arranged in a matrix are arranged in a matrix, and an X decoder and a Y decoder select memory cells in the memory cell array, and a block decoder selects the memory cell array block; A redundant LSI memory comprising a plurality of spare memory cell array blocks and a spare block decoder for selecting the spare memory cell array blocks.