JPH04196291A - Inner layer material - Google Patents
Inner layer materialInfo
- Publication number
- JPH04196291A JPH04196291A JP32850190A JP32850190A JPH04196291A JP H04196291 A JPH04196291 A JP H04196291A JP 32850190 A JP32850190 A JP 32850190A JP 32850190 A JP32850190 A JP 32850190A JP H04196291 A JPH04196291 A JP H04196291A
- Authority
- JP
- Japan
- Prior art keywords
- inner layer
- layer material
- cut
- generated
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 title claims abstract description 30
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 230000002093 peripheral effect Effects 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 239000011521 glass Substances 0.000 abstract description 6
- 239000004744 fabric Substances 0.000 abstract description 5
- 239000011889 copper foil Substances 0.000 abstract description 4
- 239000000843 powder Substances 0.000 abstract description 4
- 238000003754 machining Methods 0.000 abstract 1
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000835 fiber Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000010008 shearing Methods 0.000 description 2
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012784 inorganic fiber Substances 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920006380 polyphenylene oxide Polymers 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野〕
本発明は、プリント配線板などに供される多層積層板の
内層材に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an inner layer material of a multilayer laminate used for printed wiring boards and the like.
従来よりエポキシ樹脂の多層銅張積層板はプリント配線
板として多用されている。かかる多層積層板を構成する
ガラス布基材エポキシ樹脂の内層材は、定尺サイズの大
板より所定サイズに切断される。切断の方法例としては
シャーリングや鋸などをあげることができる。所定サイ
ズの切断加工面は、切断時に生した樹脂粉やガラス布ケ
バ、切粉などの異物が積層加工の取扱時において金属箔
の表面や積層成形のプレートに付着することによって、
積層板に凹凸を生したり、回路形成したとき、回路パタ
ーンの断線、欠落などの不良回路を発生させる原因とし
て問題視されていた。特に、微細回路の形成時において
この問題は不良率の増大となり深刻であった。このため
に切断後の内層材の端面を、ルータ−やベルトサンダー
などにより研磨面取り加工する方法、内層材の端面を赤
外線ヒーターで加熱処理して樹脂を溶着し、前記の粉落
ちを防止する方法などが行われているが、端面から発生
する異物は、内層材のラミネート、露光、エツチングな
どの後工程において、なお、十分に解決されていなかっ
た。Multilayer copper-clad laminates made of epoxy resin have been widely used as printed wiring boards. The inner layer material of the glass cloth base epoxy resin constituting such a multilayer laminate is cut into a predetermined size from a large plate of a standard size. Examples of cutting methods include shearing and sawing. The cut surface of a predetermined size is caused by foreign matter such as resin powder, glass cloth fluff, and chips generated during cutting adhering to the surface of the metal foil or the plate of the laminated molding during lamination processing.
It has been viewed as a problem because it causes irregularities in the laminated board and causes defective circuits such as disconnections and missing circuit patterns when circuits are formed. This problem is especially serious when forming fine circuits, as it increases the defective rate. For this purpose, the end face of the inner layer material after cutting is polished and chamfered using a router or belt sander, etc., and the end face of the inner layer material is heated with an infrared heater to weld the resin and prevent the above-mentioned powder falling off. However, foreign matter generated from the end surface has not yet been sufficiently resolved in post-processes such as laminating, exposing, and etching the inner layer material.
本発明は、異物発生のない内層材を提供することにある
。An object of the present invention is to provide an inner layer material that does not generate foreign matter.
本発明は、上記の点に鑑みて為されたものであり、発明
者らは、多層積層板を構成する内層材において、内層材
の周囲の端面が樹脂層で被覆されてなることを特徴とす
る内層材によって問題を解決したのである。The present invention has been made in view of the above points, and the inventors have proposed an inner layer material constituting a multilayer laminate, characterized in that the peripheral end surface of the inner layer material is covered with a resin layer. The problem was solved by using an inner layer material.
以下に、本発明を図面に基づいて説明する。The present invention will be explained below based on the drawings.
第1図は本発明にかかる多層積層板用の内層材の断面図
であり、第2図はその斜視図である。FIG. 1 is a sectional view of an inner layer material for a multilayer laminate according to the present invention, and FIG. 2 is a perspective view thereof.
第1図の内層材は絶縁層1の表面に銅12が接着され、
切断端面に樹脂層3が被覆されたものである0通常は、
積層板を用い1m角、lmX2m矩形等の定尺サイズの
両面銅張り積層板の大板より30C11X30CI、4
5C11X25CIなど任意の所定サイズに切断され、
切断端面に樹脂層を被覆した後、前記銅箔を銅回路に形
成し、さらに黒化処理などの粗面化処理して作ることが
できる。In the inner layer material shown in FIG. 1, copper 12 is bonded to the surface of the insulating layer 1.
Usually, the cut end surface is coated with a resin layer 3.
30C11X30CI, 4 from a large board of double-sided copper-clad laminate of standard size such as 1m square, 1mx2m rectangle, etc. using a laminate board.
Cut into any predetermined size such as 5C11X25CI,
After coating the cut end surface with a resin layer, the copper foil can be formed into a copper circuit, and then subjected to surface roughening treatment such as blackening treatment.
前記の両面銅張り積層板に代えて、片面銅張り積層板を
用いることもできる。Instead of the double-sided copper-clad laminate described above, a single-sided copper-clad laminate can also be used.
これらの、銅張り積層板としては、銅張りガラス基材エ
ポキシ樹脂積層板、ポリイミド樹脂積層板、ポリフェニ
レンオキサイド樹脂積層板、フッ素樹脂積層板、および
、これら樹脂の変性樹脂積層板や無機充填剤を含存した
前記の樹脂などから作られた積層板などを用いることが
できる。These copper-clad laminates include copper-clad glass-based epoxy resin laminates, polyimide resin laminates, polyphenylene oxide resin laminates, fluororesin laminates, modified resin laminates of these resins, and inorganic fillers. A laminate made from the above-mentioned resins and the like can be used.
基材は、ガラスに限定するものではなく、この他、石英
繊維等の無機繊維布やマット、ポリイミド樹脂繊維等の
高耐熱性有機繊維布やマット等を用いることができる。The base material is not limited to glass, and inorganic fiber cloths and mats such as quartz fibers, highly heat-resistant organic fiber cloths and mats such as polyimide resin fibers, etc. can be used as the base material.
切断面を被覆する樹脂層は、内層材に用いられた積層板
樹脂と同しもの、または、同種のものを用いることがで
きる。特に、エポキシ系樹脂は接着性に優れている点で
好んで用いることができる。なお、エポキシ系樹脂は一
液性、二液性に限定することなく用いることができる。The resin layer covering the cut surface may be the same as or of the same type as the laminate resin used for the inner layer material. In particular, epoxy resins can be preferably used because they have excellent adhesive properties. Note that the epoxy resin can be used without being limited to one-component or two-component.
好ましくは硬化温度160°C以下が通している。Preferably, the curing temperature is 160°C or less.
(作用〕
内層材は、定尺サイズの銅張積7i板の大板より所定サ
イズに切断された後に種々の加工工程を経て内層材に仕
上げられる。切断面を樹脂層で被覆したことにより、樹
脂粉やガラス布ケバ、切粉などの異物が切断面から生し
るのを阻止できるために積層板に凹凸を生したり、回路
形成したとき、回路パターンの断線、欠落などの不良回
路の発生が無くなる。(Function) The inner layer material is cut into a predetermined size from a large copper-clad 7i board of standard size, and then subjected to various processing steps to be finished as the inner layer material.By covering the cut surface with a resin layer, This prevents foreign matter such as resin powder, glass cloth fuzz, and chips from forming on the cut surface, which prevents unevenness on the laminate, and prevents defective circuits such as disconnections and missing circuit patterns when forming circuits. No more outbreaks.
〔実施例]
1m角の両面銅張りガラス布基材エポキシ樹脂積層板を
25CffiX50Cm角の所定サイズにシャーリング
で切断した後、高圧水洗洗浄、研磨で一次クリーニング
し、次に、この切断された積層板の端面にエポキシ樹脂
を塗布し、加熱硬化させた。[Example] After cutting a 1 m square double-sided copper-clad glass cloth base epoxy resin laminate into a predetermined size of 25 Cffi x 50 cm square by shearing, primary cleaning was performed by high-pressure water washing and polishing, and then the cut laminate was Epoxy resin was applied to the end face and cured by heating.
この積層板の両面の銅箔層にドライフィルムをラミネー
ト、露光、現像、エツチングの各工程を経て回路パター
ンを形成し、黒化処理で回路パターンの銅層表面を粗面
にした内層材を得た。上記のドライフィルムのラミネー
ト、露光工程では、回路の断線、欠損の原因となる異物
の混入が阻止でき、現像、エツチングの工程では、異物
による各液の汚れが防止できた。A dry film is laminated onto the copper foil layers on both sides of this laminate, and a circuit pattern is formed through each process of exposure, development, and etching, and an inner layer material is obtained in which the surface of the copper layer of the circuit pattern is roughened by blackening treatment. Ta. In the dry film lamination and exposure steps described above, it was possible to prevent the contamination of foreign matter that would cause circuit breakage and defects, and in the development and etching steps, it was possible to prevent each liquid from being contaminated by foreign matter.
本発明の内層材は、後加工工程において、この内層材の
構成材から異物を発生させない。したがって、この内層
材から得られる多層銅張り積層板では、微細回路の形成
が、不良率少なくできるのである。The inner layer material of the present invention does not generate foreign matter from the constituent materials of the inner layer material during post-processing steps. Therefore, in the multilayer copper-clad laminate obtained from this inner layer material, fine circuits can be formed with a reduced defect rate.
第1図は本発明の一実施例の断面図、 第2図はその斜視図である。 1・・・絶縁層 2・・・銅箔 3・・・樹脂層 特許出願人 松下電工株式会社 FIG. 1 is a sectional view of an embodiment of the present invention; FIG. 2 is a perspective view thereof. 1...Insulating layer 2...Copper foil 3...Resin layer Patent applicant Matsushita Electric Works Co., Ltd.
Claims (1)
周囲の端面が樹脂層で被覆されてなることを特徴とする
内層材。(1) An inner layer material constituting a multilayer laminate, characterized in that the peripheral end surface of the inner layer material is covered with a resin layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32850190A JPH04196291A (en) | 1990-11-27 | 1990-11-27 | Inner layer material |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32850190A JPH04196291A (en) | 1990-11-27 | 1990-11-27 | Inner layer material |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04196291A true JPH04196291A (en) | 1992-07-16 |
Family
ID=18210988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32850190A Pending JPH04196291A (en) | 1990-11-27 | 1990-11-27 | Inner layer material |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04196291A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005019641A (en) * | 2003-06-25 | 2005-01-20 | Jfe Steel Kk | Laminated core excellent in dimensional accuracy and its manufacturing method |
JP2009239215A (en) * | 2008-03-28 | 2009-10-15 | Kyocer Slc Technologies Corp | Copper-clad laminate, method of manufacturing wiring board using the same, end face processing method of copper-clad laminate, and end face processing device using the same |
JP2009295620A (en) * | 2008-06-02 | 2009-12-17 | Hitachi Cable Ltd | Metal-coated substrate for printed wiring board, printed wiring board, and method of manufacturing the same |
WO2010137418A1 (en) * | 2009-05-26 | 2010-12-02 | 株式会社エナテック | Application apparatus, applicator, and application method |
WO2018211883A1 (en) * | 2017-05-18 | 2018-11-22 | 株式会社村田製作所 | Method for manufacturing resin multilayer substrate, resin multilayer substrate, and mounting structure of resin multilayer substrate |
-
1990
- 1990-11-27 JP JP32850190A patent/JPH04196291A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005019641A (en) * | 2003-06-25 | 2005-01-20 | Jfe Steel Kk | Laminated core excellent in dimensional accuracy and its manufacturing method |
JP2009239215A (en) * | 2008-03-28 | 2009-10-15 | Kyocer Slc Technologies Corp | Copper-clad laminate, method of manufacturing wiring board using the same, end face processing method of copper-clad laminate, and end face processing device using the same |
JP2009295620A (en) * | 2008-06-02 | 2009-12-17 | Hitachi Cable Ltd | Metal-coated substrate for printed wiring board, printed wiring board, and method of manufacturing the same |
WO2010137418A1 (en) * | 2009-05-26 | 2010-12-02 | 株式会社エナテック | Application apparatus, applicator, and application method |
WO2018211883A1 (en) * | 2017-05-18 | 2018-11-22 | 株式会社村田製作所 | Method for manufacturing resin multilayer substrate, resin multilayer substrate, and mounting structure of resin multilayer substrate |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3815435B2 (en) | Circuit board manufacturing method | |
US20020061415A1 (en) | Resin/copper/metal laminate and method of producing same | |
JPH04196291A (en) | Inner layer material | |
EP0708707B1 (en) | Method of laminate manufacture | |
KR100683108B1 (en) | Method for manufacturing multi-layered printed circuit board | |
US6338937B1 (en) | Lithography method and method for producing a wiring board | |
JPH09270573A (en) | Printed wiring board and manufacture thereof | |
JPS5841177B2 (en) | Multilayer board manufacturing method | |
JP2818361B2 (en) | Manufacturing method of multilayer printed wiring board | |
JPS61211006A (en) | Manufacture of laminated sheet | |
KR100619349B1 (en) | Method for forming circuit pattern of printed circuit board | |
JP2005197443A (en) | Method of manufacturing printed wiring board | |
JPS62212133A (en) | Preparation of laminated board | |
JP2009234223A (en) | Copper-clad laminated sheet, method for manufacturing wiring substrate using this, method for processing end face of copper-clad laminated sheet and end face processing apparatus used for this | |
KR100359957B1 (en) | Dust removal method of prepreg in the lay-up process for pcb | |
JPH0936518A (en) | Inspection method of wiring board and device thereof | |
JPH0499088A (en) | Manufacture of multilayered printed wiring board | |
JPH10329016A (en) | Polishing jig plate and its manufacture | |
JP4595900B2 (en) | Method for producing multilayer metal foil-clad laminate | |
JP2001044635A (en) | Manufacture of inner layer circuit board and multi- layer printed wiring board | |
JPH0341451A (en) | Namufacture of printed wiring board | |
JPH0832211A (en) | Production of printed wiring board | |
JPH0341450A (en) | Manufacture of printed wiring board | |
JP2003249741A (en) | Substrate coupling method | |
JPH0677652A (en) | Production of multilayer copper clad laminate |