JPH04196262A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH04196262A JPH04196262A JP32692590A JP32692590A JPH04196262A JP H04196262 A JPH04196262 A JP H04196262A JP 32692590 A JP32692590 A JP 32692590A JP 32692590 A JP32692590 A JP 32692590A JP H04196262 A JPH04196262 A JP H04196262A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply voltage
- integrated circuit
- semiconductor integrated
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims 2
- 239000003990 capacitor Substances 0.000 abstract description 14
- 230000001052 transient effect Effects 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 2
- 230000008602 contraction Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000004720 fertilization Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体集積回路の電源電圧の安定化に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to stabilizing the power supply voltage of a semiconductor integrated circuit.
第３図は例えば、′８９三菱半導体データブックＩＣパ
ッケージ編１−７ページに示された従来の半導体集積回
路装置の構造図、第４図は第３図の中央付近の拡大図で
ある。図において、（１）は半導体基板、（２）はり一
トフレーム、（３）は半導体基板表面の活性層、（４）
は半導体基板（］、）とリードフレーム（２）を接着す
るロウ材、（５）は活性層（３）とリードフレーム（２
）を電気的に接続する金線、（６）はモールド樹脂、（
７）はリードフレーム（２）と金線（５）を安定的に接
続させるための銀メツキである。また、第５図は第４図
の装置と電源装置との接続を示す回路図であり、図にお
いて、（８）は電源装置、（９）は電源線の自己インダ
クタンス、００）はコンデンサ、（１１）はリードフレ
ーム（２）の自己インダクタンスである。FIG. 3 is a structural diagram of a conventional semiconductor integrated circuit device shown, for example, in the '89 Mitsubishi Semiconductor Data Book IC Package Edition, pages 1-7, and FIG. 4 is an enlarged view of the vicinity of the center of FIG. In the figure, (1) is the semiconductor substrate, (2) the beam frame, (3) is the active layer on the surface of the semiconductor substrate, and (4) is the active layer on the surface of the semiconductor substrate.
(5) is the brazing material for bonding the semiconductor substrate (], ) and the lead frame (2), and (5) is the active layer (3) and the lead frame (2).
) is the gold wire that electrically connects, (6) is the molded resin, (
7) is silver plating for stably connecting the lead frame (2) and the gold wire (5). FIG. 5 is a circuit diagram showing the connection between the device in FIG. 4 and the power supply device. In the figure, (8) is the power supply device, (9) is the self-inductance of the power line, 00 is the capacitor, and (00) is the capacitor. 11) is the self-inductance of the lead frame (2).
次に、電源電圧の変動について説明する。Next, fluctuations in power supply voltage will be explained.
半導体集積回路装置の電源電圧変動の最大の原因は、集
積回路のスイッチング時に流れる過渡電流である。電源
装置（８）と半導体集積回路装置（６）の間には、数十
ｃｍから数ｍの電線か存在するから、この電線の自己イ
ンダクタンス（９）は０．１〜１０μＨ程度であり、数
ｎＳの間（二数十ｍＡの過渡電流か流れる半導体集積回
路に対して、電源電圧の変動を０．５■以内に抑えるこ
とは不可能である。コンデンサ００）は、こうした電源
電圧の変動を抑える為に用いられるもので、半導体集積
回路装置の近くて電源線間に接続され、過渡電流を吸収
して電源電圧の変動を抑える。The biggest cause of power supply voltage fluctuations in semiconductor integrated circuit devices is transient current that flows during switching of the integrated circuit. Since there is an electric wire between several tens of centimeters to several meters between the power supply device (8) and the semiconductor integrated circuit device (6), the self-inductance (9) of this electric wire is about 0.1 to 10 μH, which is several meters long. nS (for semiconductor integrated circuits in which a transient current of a few tens of mA flows, it is impossible to suppress the fluctuations in the power supply voltage to within 0.5μ. Capacitor 00) suppresses such fluctuations in the power supply voltage. It is used to suppress fluctuations in power supply voltage, and is connected between power supply lines near semiconductor integrated circuit devices to absorb transient currents and suppress fluctuations in power supply voltage.
従来の半導体集積回路装置は以上のように使用されてい
るので、電源電圧の変動を抑えるためにはできるたけ各
半導体集積回路装置の近くにコンデンサを接続する必要
かあり、従ってコスト高になる。また、いかに近くに接
続しても、半導体集積回路装置内部の自己インダクタン
ス０１）による内部電源電圧の変動を防ぐことかできな
いという問題点かあった。Since conventional semiconductor integrated circuit devices are used as described above, it is necessary to connect capacitors as close to each semiconductor integrated circuit device as possible in order to suppress fluctuations in power supply voltage, which increases costs. Another problem is that no matter how close they are connected, it is impossible to prevent fluctuations in the internal power supply voltage due to self-inductance 01) inside the semiconductor integrated circuit device.
この発明は上記のような問題点を解消するためになされ
たもので、半導体チップの近くに安価な静電容量を設け
、コスト高の原因となるコンデンサ００）を減らしなか
ら従来以上に安定した電源電圧を確保することかできる
半導体集積回路を得ることを目的とする。This invention was made to solve the above-mentioned problems, and by providing an inexpensive capacitance near the semiconductor chip and reducing the capacitor 00), which causes high costs, it is more stable than before. The purpose of this invention is to obtain a semiconductor integrated circuit that can secure a power supply voltage.
この発明に係る半導体集積回路装置は、半導体基板を一
つの電源電位に接続し、これを接着するリードフレーム
を他方の電源電位に接続することて、２つの電ｒｉ、電
位間に静電容量を形成し、電源電圧を安定させたもので
ある。The semiconductor integrated circuit device according to the present invention connects the semiconductor substrate to one power supply potential, and connects the lead frame to which the semiconductor substrate is bonded to the other power supply potential, thereby creating a capacitance between two electrical potentials. It is designed to stabilize the power supply voltage.
この発明における静電容量は、半導体基板とり一トフレ
ームを両極とし、ロウ材を絶縁物として形成され、半導
体集積回路の発生させる過渡電源電流を吸収することに
よ−て電源電圧を安定させる。The capacitance in this invention is formed by using the semiconductor substrate and the frame as both poles and the brazing material as an insulator, and stabilizes the power supply voltage by absorbing the transient power supply current generated by the semiconductor integrated circuit.
以下、この発明の一実施例を図について説明する。第１
図において、０つは半導体基板を接着させたリードフレ
ーム、０３は負の電源電位のリードフレーム、このリー
ドフレーム０３と半導体基板（１）を電気的に接続する
ために、低抵抗半導体層（１７）の上に設けられたアル
ミ膜Ｏｅの表面に金線０■か溶接される。０４）は正の
電源電位のリードフレーム、０８）はリードフレームＯ
２と（１４）を電気的に接続するだめの金線、０９）は
半導体基板（１）とリードフレームＯ２の間に形成され
る静電容量である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 0 is a lead frame to which a semiconductor substrate is adhered, 03 is a lead frame with a negative power supply potential, and a low resistance semiconductor layer (17) is used to electrically connect this lead frame 03 and the semiconductor substrate (1). ) is welded to the surface of the aluminum film Oe. 04) is a lead frame with positive power supply potential, 08) is a lead frame O
A gold wire 09) electrically connecting 2 and (14) is a capacitance formed between the semiconductor substrate (1) and the lead frame O2.
静電容量０９）の効果はコンデンサＧｏｔと同様である
。The effect of capacitance 09) is similar to that of capacitor Got.
たたし、コンデンサ（１０）か容易に大きな静電容量を
得られるのに比へて静電容量α９）の大きさは限られる
一方、静電容量０９）は半導体集積回路装置内部の自己
インダクタンス０Ｄによる電源電圧変動をも吸収できる
。また、半導体基板（１）と片方の電源電位のリードフ
レーム０３とを接続するａｓ ａｓ （１７）は従来の
半導体集積回路装置にも備わっている場合か多いから、
この発明を実施するには金線ａｇを追加するのみて僅か
数銭のコストで可能であり、半導体集積回路装置の大き
さも従来と全（変わらない。However, the size of capacitance α9) is limited compared to the capacitor (10) that can easily obtain a large capacitance, while capacitance 09) is the self-inductance inside the semiconductor integrated circuit device. It can also absorb power supply voltage fluctuations due to 0D. Further, since the as as (17) for connecting the semiconductor substrate (1) and the lead frame 03 at one power supply potential is often provided in conventional semiconductor integrated circuit devices,
This invention can be implemented at a cost of only a few sen by adding a gold wire AG, and the size of the semiconductor integrated circuit device remains the same as the conventional one.
各半導体集積回路装置に静電容量０９）を形成する代わ
りに、コンデンサα０）の数を半導体集積回路装置２０
個あたり１個程度まで減らすことができるから、コンデ
ンサＱＯＩの減少分だけコスト及び実装面積を減少させ
ることかできる。Instead of forming capacitance 09) in each semiconductor integrated circuit device, the number of capacitors α0) is
Since the number of capacitors can be reduced to about one per piece, the cost and mounting area can be reduced by the reduction in capacitor QOI.
なお、上記実施例ではリードフレームα２と０４）の接
続を金線０εによって行なったか、リードフレーム（１
のと０４）を一体に形成してもよい。この場合には、金
線ＱＥＩのコストは削減できるか、リードフレームを設
計し直す必要か生しる。In the above embodiment, the lead frames α2 and 04) were connected by gold wire 0ε, or the lead frames α2 and 04)
and 04) may be formed integrally. In this case, the question is whether the cost of the gold wire QEI can be reduced or whether the lead frame needs to be redesigned.
以上のように、この発明によれば半導体基板とり一トフ
レームの間の静電容量を電源電圧の安定化のために利用
したので、半導体集積回路装置内部の自己インダクタン
スによる電源電圧の変動をも抑えることかてき、またコ
ンデンサの個数削減によってプリント基板のコスト削減
及び面積の縮小を達成できる効果かある。As described above, according to the present invention, since the capacitance between the semiconductor substrate and the frame is used to stabilize the power supply voltage, fluctuations in the power supply voltage due to self-inductance inside the semiconductor integrated circuit device can be prevented. Moreover, by reducing the number of capacitors, it is possible to reduce the cost and area of the printed circuit board.
【図面の簡単な説明】
第１図は二の発明の一実施例による半導体集積回路装置
の中心部の断面図、第２図は第１図の装置と電源装置と
の接続を示す回路図、第３図は従来の半導体集積回路装
置の構造図、第４図は第３図の中心部の断面図、第５図
は第４図の装置と電源装置との接続を示す回路図である
。
図において、（１）は半導体基板、（７）は銀メツキ、
０り、 （１３、Ｃ１４）はり−トフレーム、ａｓ、ａ
ａは金線、０■はアルミ膜、０７）は低抵抗半導体層、
０９）は静電容量である。
なお、各図中、同一符号は同一または相当部分を示す。
代 理 人 大 岩 増 雄第１団
第？閉
第３肥
躬４閾
、ガBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of the center of a semiconductor integrated circuit device according to an embodiment of the second invention, FIG. 2 is a circuit diagram showing the connection between the device of FIG. 1 and a power supply device, FIG. 3 is a structural diagram of a conventional semiconductor integrated circuit device, FIG. 4 is a sectional view of the central part of FIG. 3, and FIG. 5 is a circuit diagram showing the connection between the device of FIG. 4 and a power supply device. In the figure, (1) is a semiconductor substrate, (7) is silver plating,
0ri, (13, C14) beam frame, as, a
a is gold wire, 0■ is aluminum film, 07) is low resistance semiconductor layer,
09) is the capacitance. In each figure, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa 1st group? Closed 3rd fertilization 4th threshold, Ga
Claims (1)
に接続され、上記導体基板に片面を接着された半導体基
板とを有することを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device comprising a conductor substrate connected to a certain power supply potential and a semiconductor substrate connected to another power supply potential and having one side bonded to the conductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32692590A JPH04196262A (en) | 1990-11-27 | 1990-11-27 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32692590A JPH04196262A (en) | 1990-11-27 | 1990-11-27 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04196262A true JPH04196262A (en) | 1992-07-16 |
Family
ID=18193295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32692590A Pending JPH04196262A (en) | 1990-11-27 | 1990-11-27 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04196262A (en) |
-
1990
- 1990-11-27 JP JP32692590A patent/JPH04196262A/en active Pending
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