JPH04195627A - Logic circuit - Google Patents

Abstract

PURPOSE:To normally transfer data even in case of an accidental delay of the operating time of a block by providing a data transfer control means which detects the end of the operation of each block and generates a control signal. CONSTITUTION:A block A performs an operation f(a) for an input (a) sent with a control signal phi0B and generates a one-shot pulse as a data transfer control signal phi1B for a block B when detecting the end of the operation. With this control signal phi1B, the arithmetic result (b) is transferred to the block B. Similarly, transfer is performed from the block B to a block C and from the block C to a next block. Consequently, even if the delay of the operating time is caused for any reason, a transfer signal and transfer data have no deviation and normal data transfer is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit that requires data transfer in multiple stages.

[Conventional technology]

Among conventional logic circuits that require data transfer in multiple stages, there is a circuit shown in FIG. 3 that uses a delay circuit to control data transfer without using a synchronizing signal.

In the figure, l is a block A that performs an operation of f (a+) on a certain input a and outputs the result of the operation, and block 2 performs an operation of g (b+) on a certain input and outputs the result of the operation C. Block B, 3 has h for some input C
(This is block C that performs the calculation of C1 and outputs the calculation result d. Also, 4 to 7 are input/output data a, b, c, and d of blocks 1 to 3.

8 is a one-shot pulse generation circuit; 9 is a trigger signal TR input to the one-shot pulse generation circuit 8; 10 to 1;
2 is a delay circuit that generates a delay commensurate with the calculation time of blocks 1 to 3, and +3A-+6A are delay circuits for each block 1 to 3.
These are signals φOA to φ3A that control data transfer between the three terminals.

Next, the operation will be explained.

First, the trigger signal TR is sent to the one-shot pulse generation circuit 8.
A pulse of φOA is generated by manually inputting
After that, the delay circuits 10 to 12 perform φIA, φ2
A, φ3A pulses are still generated. Transfer control of blocks 1 to 3M is performed using this pulse as a control signal. FIG. 4 shows a timing chart in this case.

In the figure, 17 to 19 are delay circuits lO to 12, respectively.
The delay times tl, t2. t3, 20-2
2 are the calculation times ta and tb of blocks 1.2.3, respectively.
, tc.

[Invention or problem to be solved]

Since conventional logic circuits are configured as described above, the delay circuit must be designed to generate a delay commensurate with the calculation time of each block.

In other words, as shown in FIG. 4, tt>ta is always held.

The relationships t2>tb and ta>tc must hold, and therefore, if even one of these relationships breaks down for some reason, there is a problem that normal data transfer will not be possible.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a logic circuit that eliminates the deviation between the calculation time of each block and the data transfer completion signal.

[Means to solve the problem]

In a logic circuit according to the present invention that requires data transfer in multiple stages, the data transfer sub-section between each block detects the completion of an operation in each block and uses the generated one-shot pulse as a control signal. The device is equipped with data transfer means for performing the following.

[Effect]

The data transfer means in the present invention detects the end of the calculation of each block and generates a one-shot pulse of the data transfer control signal, so it is normal even if the block calculation time is delayed from normal due to some reason. data transfer is possible.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a logic circuit which is an embodiment of the present invention, and since the reference numerals in the figure are the same as those in the conventional circuit, a description thereof will be omitted. Block A performs an operation f(al) on a certain input a sent by control signal φOB.Then, when it detects the end of the operation, it generates a one-shot pulse and sends a data transfer control signal φ1B to block B. The operation result is transferred to block B by this control signal φIB.Hereafter, from block B to block C,
Transfer from block C to the next block is performed in the same manner.

The end of the computation may be detected by detecting the end of computation for all inputs, or by detecting the end of computation with a particularly long delay time for some inputs. A timing chart of the above embodiment is shown in FIG. In this way, the one-shot pulse is generated by detecting the end of each block's computation, so even if there is a delay in computation time due to some factor,
There is no deviation between the transfer signal and the transfer data, and normal data transfer is possible.

〔Effect of the invention〕

As described above, according to the present invention, since data transfer control means is provided that detects the end of the calculation of each block and generates a control signal, even if an accidental delay in the calculation time of a block occurs, the operation can be performed normally. This has the effect of being able to transfer data.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a logic circuit which is an embodiment of the present invention, Fig. 2 is a timing waveform diagram of each signal in Fig. 1, and Fig. 3 is a block diagram of a logic circuit that is an embodiment of the present invention. FIG. 4 is a block diagram of a logic circuit that performs transfer control, and is a timing waveform diagram of each signal in FIG. 3. In the figure, 1 to 3 represent human power a and b, respectively. Perform the calculations f(aJ, g(bl, h(CI) for C. Blocks that obtain the outputs of c and d, 4 to 7 are each block 1 to 7.
3 input/output data a, b, c, d, 13B to 16B are data transfer signals φOB, φIB,
φ2B, φ3B, and 20 to 22 indicate the calculation times ta, tb, and tc of each block. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Data transfer signals for each block 1-3 Blocks 13B-16B 20-22 Operation time for each block Figure 3 Figure 4 Procedure amendment (self-proposed) July 2, 1991 Japan-Mi1 Commissioner of the Japan Patent Office
・Mi1, Incident Display Patent Application No. 2-335378 2,
Name of the invention Logic circuit 3, Person making the amendment Representative Moriya Shiki 4, Agent name (7375) Patent attorney Daikimi Masayoshi (contact number 03 (3213) 3421 Patent Department) - & Specification subject to amendment Column for Detailed Description of the Invention & Contents of Amendment fil The "data transfer success signal" on page 3, lines 14 to 15 of the specification is corrected to "data transfer control signal."that's all

Claims (1)

[Claims] In a logic circuit that requires data transfer in multiple stages, it is equipped with a data transfer means that detects the end of the calculation that generates the data to be sent, generates a one-shot pulse, and uses this as a data transfer signal to transfer data. Characteristic logic circuit.