JPH04195235A - Read-only memory circuit - Google Patents

Read-only memory circuit

Info

Publication number
JPH04195235A
JPH04195235A JP2320074A JP32007490A JPH04195235A JP H04195235 A JPH04195235 A JP H04195235A JP 2320074 A JP2320074 A JP 2320074A JP 32007490 A JP32007490 A JP 32007490A JP H04195235 A JPH04195235 A JP H04195235A
Authority
JP
Japan
Prior art keywords
program
storage area
rom
area
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2320074A
Other languages
Japanese (ja)
Inventor
Katsumi Saito
斎藤 勝美
Takeshi Kiyono
清野 剛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Miyagi Ltd
Original Assignee
NEC Corp
NEC Miyagi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Miyagi Ltd filed Critical NEC Corp
Priority to JP2320074A priority Critical patent/JPH04195235A/en
Publication of JPH04195235A publication Critical patent/JPH04195235A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To detect the abnormality before the start of a program by storing the result of the check sum obtained to the program working with a processor into a storage area of a read-only memory ROM. CONSTITUTION:A ROM 1 consisting of an area 1a where the data are written and an area 1b where the result of check sum is written is loaded into a processor. Thus the check sum of each data is calculated before the operation of the area 1a every time the ROM 1 is started. Then the calculated check sum is compared with the check sum of the area 1b. If one of bits of the data stored in the area 1a has a wrong change, no coincidence is obtained from the comparison of check sums. Thus the abnormality of a program stored in the ROM 1 is detected before the program starts its operation.

Description

【発明の詳細な説明】 技術分野 本発明は読出し専用記憶回路に関し、特に読出し専用記
憶回路上に書込まれているプログラムの正常性を確認す
る方式に関する。
TECHNICAL FIELD The present invention relates to a read-only memory circuit, and more particularly to a method for confirming the normality of a program written on the read-only memory circuit.

従来技術 従来、この種のプログラムの正常性の確認方式において
は、読出し専用記憶回路(以下ROMとする)にロムラ
イタによりプログラムが書込まれるとき、書込まれたプ
ログラムの正常性がロムライタて自動的に確認されてい
るか、ROMか装置に搭載されて出荷されてしまうと、
装置内のROMに書込まれたプログラムの正常性の確認
を行う方法はなかった。
Prior Art Conventionally, in this type of program normality confirmation method, when a program is written to a read-only memory circuit (hereinafter referred to as ROM) by a ROM writer, the ROM writer automatically checks the normality of the written program. If the product is shipped after being installed in ROM or equipment,
There was no way to check the normality of the program written in the ROM in the device.

このような従来のRO〜1上のブロクラムの正常性を確
認する方式では、ROMか装置に搭載されて出荷されて
しまうと、装置内のROMに書込まれたプログラムの正
常性の確認を行う方法はなかったので、装置が8荷され
た後で、ROM上のプログラムに異常が生しても、該プ
ログラムか動作する前にその異常を検出することかでき
ないという欠点がある。
In this conventional method of checking the normality of the block diagram on RO~1, once the ROM is installed in the device and shipped, the normality of the program written in the ROM in the device is checked. Since there was no method, even if an abnormality occurred in the program on the ROM after the device was loaded, there was a drawback that the abnormality could only be detected before the program started operating.

発明の目的 本発明は上記のような従来のものの欠点を除去すべくな
されたもので、装置の出荷後にROM上のプログラムに
異常が生じても、該プログラムか動作する前にその異常
を検出することができる読出し専用記憶回路の提供を目
的とする。
Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and even if an abnormality occurs in the program on the ROM after the device is shipped, the abnormality is detected before the program starts operating. The object of the present invention is to provide a read-only storage circuit that can perform the following functions.

発明の構成 本発明による読出し専用記憶回路は、処理装置上で動作
するプログラムを格納する第1の格納領域と、前記第1
の格納領域に格納された前記プログラムに対するチェッ
クサムの結果を格納する第2の格納領域とからなること
を特徴とする。
Structure of the Invention A read-only storage circuit according to the present invention includes a first storage area for storing a program running on a processing device;
and a second storage area for storing checksum results for the program stored in the storage area.

実施例 次に、本発明の一実施例について図面を参照して説明す
る。
Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例による読出し専用記憶回路の
メモリマツプを示す図である。図において、読出し専用
記憶回路(以下ROMとする)1は図示せぬ中央処理装
置を操作するプログラムを格納する格納領域1aと、二
の格納領域1aへの該プログラムの書込み時に計算され
たチエ・ツクサムの結果を格納する格納領域1bとから
構成されている。
FIG. 1 is a diagram showing a memory map of a read-only storage circuit according to an embodiment of the present invention. In the figure, a read-only memory circuit (hereinafter referred to as ROM) 1 has a storage area 1a for storing a program for operating a central processing unit (not shown), and a storage area 1a for storing a program for operating a central processing unit (not shown). It consists of a storage area 1b for storing the results of the TUXUM.

第2図はチェックサムの算出例を示す図である。FIG. 2 is a diagram showing an example of calculating a checksum.

この第2図を用いてチェックサムの算出について説明す
る。
Checksum calculation will be explained using FIG. 2.

“10110100′、“ttooooto“、“00
010011”というデータのチェックサムを算出する
場合、これらのデータ“10110100”、  ”1
1000010′、“00010011”をビット毎に
加算する。
“10110100′, “ttooooto”, “00
When calculating the checksum of the data “010011”, these data “10110100”, “1
1000010' and "00010011" are added bit by bit.

ただし、加算途中で生したキャリー(carry )は
捨ててしまうので、その結果“01100101”か゛
チェックサムの結果となる。
However, the carry generated during the addition is discarded, resulting in a checksum result of "01100101".

これら第1図および第2図を用いて本発明の一実施例の
動作について説明する。
The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

たとえば、上記の各データ“10110100” 、 
 “ll000010”、“00010011″がRO
MIの格納領域1aに書込まれたとすると、そのデータ
のチエ・ツクサムの算出結果“01100101”が格
納領域1bに書込まれる。
For example, each of the above data “10110100”,
“ll000010”, “00010011” are RO
Assuming that the data is written to the MI storage area 1a, the calculation result of the Chie Tsukusum of the data "01100101" is written to the storage area 1b.

各データ“10110100”、“11000010”
、“00010011”が書込まれた格納領域1aと、
チエ・ツクサムの結果″01100101“が書込まれ
た格納領域1bとからなるROMIが図示せぬ処理装置
に搭載され、工場から出荷されると、ユーザが該処理装
置を立ち上げる毎に、格納領域1aのプログラムによる
動作か開始される前に、格納領域1aに書込まれた各デ
ータ“10110100” 、  “11000010
”。
Each data “10110100”, “11000010”
, a storage area 1a in which “00010011” is written;
When a ROMI consisting of a storage area 1b in which the Chie Tsukusum result "01100101" is written is installed in a processing device (not shown) and shipped from the factory, each time a user starts up the processing device, the storage area 1b is Each data “10110100” and “11000010” written in the storage area 1a before the operation by the program 1a is started.
”.

“oootoott”のチェックサムか算出され、その
算出結果と格納領域1bに書込まれたチェックサムの算
出結果“01100i01”とか比較される。
The checksum of "ooootoott" is calculated, and the calculation result is compared with the checksum calculation result "01100i01" written in the storage area 1b.

ROMIの格納領域1aのデータのいずれかのビットか
誤って変化した場合にはその比較結果か不一致を示すの
で、ROMI上のプログラムの異常を動作開始前に検出
することかできる。
If any bit of the data in the storage area 1a of the ROMI is erroneously changed, the comparison result will indicate a mismatch, so an abnormality in the program on the ROMI can be detected before the start of operation.

このように、格納領域1aに格納され、処理装置上で動
作するプログラムのチェックサムの算出結果を格納領域
1bに格納しておくようにすることによって、格納領域
1aのプログラムが動作する前に算出したチェックサム
の算出結果と格納領域1bのプログラムが正常なときの
チエ、ツクサムの算出結果とを比較してプログラムの正
常性を確認することができるので、装置の出荷後にRO
M1上のプログラムに異常が生しても、該プログラムが
動作する前にその異常を検出することができる。
In this way, by storing the checksum calculation result of the program stored in the storage area 1a and running on the processing device in the storage area 1b, the checksum calculation result of the program stored in the storage area 1a can be calculated before the program in the storage area 1a runs. The normality of the program can be confirmed by comparing the checksum calculation result obtained when the program in storage area 1b is normal and the checksum calculation result when the program in storage area 1b is normal.
Even if an abnormality occurs in a program on M1, the abnormality can be detected before the program starts operating.

発明の詳細 な説明したように本発明によれば、ROMに書込まれ、
処理装置上で動作するプログラムに対するチェックサム
の結果をRO〜1に設けた格納領域に格納するようにす
ることによって、装置の出荷後にROM上のプログラム
に異常か生しても、該プロクラムが動作する前にその異
常を検出する二とかできるという効果かある。
According to the present invention, as described in the detailed description of the invention,
By storing the checksum result for the program running on the processing device in the storage area provided in RO~1, even if an abnormality occurs in the program on the ROM after the device is shipped, the program will continue to work. This has the effect of being able to detect anomalies before they occur.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による読出し専用記憶回路の
メモリマツプを示す図、第2図はチェックサムの算出例
を示す図である。 主要部分の符号の説明 1・・・・・ROM 1a・・・・・・プログラムの格納領域1b・・・・・
・チェックサムの格納領域出願人 日本電気株式会社(
外1名)
FIG. 1 is a diagram showing a memory map of a read-only storage circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of calculating a checksum. Explanation of symbols of main parts 1...ROM 1a...Program storage area 1b...
・Checksum storage area Applicant: NEC Corporation (
(1 person outside)

Claims (1)

【特許請求の範囲】[Claims] (1)処理装置上で動作するプログラムを格納する第1
の格納領域と、前記第1の格納領域に格納された前記プ
ログラムに対するチェックサムの結果を格納する第2の
格納領域とからなることを特徴とする読出し専用記憶回
路。
(1) The first part stores the program that runs on the processing device.
A read-only storage circuit comprising: a storage area; and a second storage area that stores a checksum result for the program stored in the first storage area.
JP2320074A 1990-11-22 1990-11-22 Read-only memory circuit Pending JPH04195235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2320074A JPH04195235A (en) 1990-11-22 1990-11-22 Read-only memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2320074A JPH04195235A (en) 1990-11-22 1990-11-22 Read-only memory circuit

Publications (1)

Publication Number Publication Date
JPH04195235A true JPH04195235A (en) 1992-07-15

Family

ID=18117428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2320074A Pending JPH04195235A (en) 1990-11-22 1990-11-22 Read-only memory circuit

Country Status (1)

Country Link
JP (1) JPH04195235A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08320834A (en) * 1995-05-26 1996-12-03 Nec Corp Automatic restoration system for flash rom

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08320834A (en) * 1995-05-26 1996-12-03 Nec Corp Automatic restoration system for flash rom

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