JPH04192647A - Cell traffic monitor - Google Patents

Abstract

PURPOSE:To monitor a cell traffic with the hardware of the rational scale by adopting a tapped delay circuit and providing a counter means, a threshold level latch circuit and a comparison discrimination circuit to taps. CONSTITUTION:The monitor is provided with a detection circuit 12 detecting the presence of a valid cell in a signal synchronously with a signal to be monitored, a shift register 13 being a delay circuit receiving a detection output and shifting the received output to the right for each cell time, and a counter means 14 receiving the detection output as a sum input and receiving a delay output shifted out from an S stage of the register 13 as a subtraction input. Moreover, the monitor is provided with a threshold level latch circuit 15 latching a threshold level (Y) for an S cell time and a comparison discrimination circuit 16 comparing the threshold level with a count of the counter 14 to send a discrimination output. Thus, plural sets of discrimination are implemented in parallel and the cell traffic is monitored with the hardware of the rational scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used for packet communication. The present invention relates to a technique for monitoring traffic of cells (fixed-length packets are referred to as "cells" in this specification) transferred in a packet communication network.

INDUSTRIAL APPLICATION This invention is utilized for the policing (policing, police action) which discards a cell as a violation of a contract when a cell is transmitted in excess of the pre-contracted traffic.

[Conventional technology]

In a packet communication network, if a large number of cells arrive at one relay point at the same time, smooth operation becomes impossible. For this reason, telecommunications carriers operating packet communication networks have agreements with users that: ■ Users must not transmit more than Y cells within a consecutive S cell time; ■ Telecommunication carriers must: A condition of the usage contract is that cells transmitted in violation of the rules are discarded. For example, S=
5. If Y=3, up to 3 cells can be transmitted within a continuous 5-cell period, but if a cell is transmitted beyond this time, the cell will be discarded.

Monitoring and discarding for this purpose is called policing, and is automatically and continuously executed at the entrance of the packet communication network.

FIG. 4 is a block diagram of a conventional device.

This circuit has been patented by the applicant (Japanese Patent Application No. 1992-130).
No. 464, unpublished at the time of filing of this application). The circuit shown in FIG. 4 is a circuit that monitors so that up to three cells can be transmitted in a continuous five-cell period, but four or more cells are not allowed.

In FIG. 4, a monitored signal is input to terminal 11. In FIG. The cell detection circuit 12 synchronizes with this monitored signal and sends out a detection output if there is a valid cell in the signal. The delay circuit 13 receives this detection output as an input, and is constituted by a shift register, and is shifted one stage to the right in the figure every cell time by a clock signal (not shown). That is, the input of this delay circuit 13 is sent to the delayed output after the S cell time.

The detection a of the cell detection circuit 12 is input to the addition input of the up-down counter 14, and the delayed output of the delay circuit 13 is input to the subtraction input thereof. The threshold value holding circuit 15 holds the threshold value Y set according to the contract.

This threshold value Y is compared with the contents of the up/down counter 14, and if D>Y, a prohibited signal is sent to the terminal 17. Due to this prohibition output, the cell is discarded by a device not shown.

In the circuit configured in this manner, the number of cells detected in the past S cell time is stored in the up/down counter 14, and when this exceeds the set threshold Y, an inhibit output is sent to the terminal 17. will be sent to. Forbidden to terminal 17 8
When the cell is sent out, the cell currently detected on the transmission path is discarded by a circuit not shown. Since that cell has been discarded, the value of the first stage of the counter 14 is cleared by the judgment output.

Here, not only the contract conditions are set for S and Y as described above, but also the large price sell time (T > S
) with the condition that it does not exceed cell X. Furthermore, this contract is not a common value for one monitored signal, but may be set to different values on the communication path side. Here, the communication route (path) may be a real route, but is generally a virtual path (virtual path), and for each virtual path, a virtual path number (in this specification, VPI (v+
A different monitoring condition is set for each VPI. The value of T is, for example, several hundred, and the value of X is, for example, several hundred.

Setting such conditions is extremely advantageous for communication carriers in order to reduce the multiplicity of the transmission paths to be prepared.

FIG. 5 shows an example of a cell configuration. FIG. 6 shows how multiplexing is performed on the transmission path.

[Problem to be solved by the invention]

This conventional device is an excellent circuit that can monitor the number of cells over the cell time S for any continuous phase.
The usage contract conditions stipulate that in addition to not transmitting more than Y cells within an S cell time, the user must not transmit more than X cells within a T cell time. In this case, it is necessary to adopt a two-stage configuration as shown in FIG. 7, which has the disadvantage of making the hardware configuration redundant.

The present invention improves this, and the contract terms are S and Y.
It is an object of the present invention to provide a cell traffic monitoring device that can handle the case where two stages such as IT and X are specified without redundancy with a single hardware configuration.

[Means to solve the problem]

A first aspect of the present invention is that the delay circuit has a tap configuration, and is provided with a counter means, a threshold value holding circuit, and a comparison/judgment circuit, respectively, according to the tap position.

The second aspect of the present invention is a configuration that can be generally applied to a large number of different values and a large number of different VPIs, and includes an identification circuit for identifying the VPI detected by the cell detection circuit, and a delay circuit. is the VP given to its input
The configuration is such that a plurality of different delay times are set, a counter means is individually provided for each of the plurality of VPIs, and the threshold value holding circuit is configured to hold the plurality of VPIs and send the VPI to the delayed output. The present invention is characterized in that a plurality of threshold values corresponding to delay times are held, and the comparison/judgment circuit is configured to individually compare the plurality of VPIs and the plurality of delay times with the respective threshold values and send out a judgment output.

[Effect]

By providing a plurality of means for counting the number of cells, a counter means for storing the counted value, a threshold holding circuit for storing the threshold value, and a comparison judgment circuit for comparing and judging the threshold value and the stored counted value, multiple judgments can be made. can be executed in parallel.

In addition, by storing count values and threshold values corresponding to VPI and delay time as a table, and making comparative judgments by referring to the table, it is possible to Cell traffic monitoring can also be performed with reasonably sized hardware.

〔Example〕

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention. In this embodiment, the signal to be monitored is input to the terminal 11. A cell detection circuit 12 is provided which synchronizes with this monitored signal and detects the presence or absence of a valid cell in the frame. When a valid cell is detected, the detection output of this cell detection circuit 12 becomes "1".
is sent out, and when no valid cell is detected, "O" is sent out. A shift register 13, which is a first delay circuit, receives this detected power as input and shifts it to the right every cell time.
Similarly, a 10th counter means is provided which uses this detection output as an addition input and a delayed output shifted out from the S-th stage of the shift register 13 as a subtraction input. This counter means is an up/down counter constituted by a counter control circuit 18 and a counter 14. Furthermore, a first threshold value holding circuit 15 that holds the threshold value (Y) for S cell time, and a threshold value (Y) held by this first threshold value holding circuit 15;
A first comparison/judgment circuit 16 is provided which compares the count value of the first 〇 counter 14 and outputs a first determination output.

Here, as a feature of the cell traffic monitoring device of the present invention, the delay circuit 13 has a multi-stage configuration and is provided with a second delay output terminal after T cell time at the right end of the figure.

This second delay output terminal is processed by the 20th counter means. That is, the second counter means is an up/down counter comprising a counter control circuit 28 and a counter 24. The detection output of the cell detection circuit 12 is applied to the addition input of this 20th counter means, and the delayed output of the delay circuit after T cell time is applied to the subtraction input. Furthermore, a second threshold value holding circuit 25 that holds a second threshold value (X);
A second comparison/determination circuit 26 is provided which compares and determines the threshold value (X) held by the second threshold value holding circuit 25 and the count value held by the twenty-th counter 24 and sends out a second determination output. The first judgment output and the second judgment output are logically summed by the OR circuit 31 and sent to the terminal 17. The signal at terminal 17 is processed by a device not shown, and then arrives at that node, and the cell just detected is discarded without being relayed. Since this process is executed within one cell time and the cell is discarded, the value "1" in the first stage of the delay circuit 13 is cleared when the judgment output from the terminal 17 is sent out.

Both the 10th counter 14 and the 20th counter 24 are non-negative arithmetic circuits. In other words, the count value never exceeds zero and becomes a negative value, and is configured so that zero is the limit.

In this device, the first counter 14 holds the number of cells detected within the past S cell time as a count value.

In other words, each time a cell is detected, the value of the counter 14 is incremented by 1, and the cells detected before S cell time are sequentially subtracted. This is the number of cells detected so far. Similarly, the number of cells detected within the past T cell time is held as a count value in the 20th counter 24.

Therefore, the count value of the first counter 14 is the threshold value Y held by the threshold value holding circuit 15, and the count value of the 20th counter 2
The count value of 4 is compared with the threshold value X held by the threshold value holding circuit 25, and when the count value exceeds the threshold value, a determination output is sent out and the cell is discarded by a circuit (not shown) connected to the terminal 17. Since this is executed within one cell time and the cell is discarded, the 1 in the -th digit of the delay circuit 13 is cleared.

In this way, a device is obtained that monitors two different conditions in parallel: not exceeding the Y cell during the short S cell time and not exceeding the X cell during the long T cell time.

FIG. 2 is a block diagram of an apparatus according to a second embodiment of the present invention. This example makes it possible to monitor cells having a large number of different VPIs multiplexed on a transmission path under conditions set for each VPI.

An identification circuit 35 that identifies the VPI (vertical cell bus number) of the cell detected by the cell detection circuit 12.
Equipped with The delay circuit 13 has VPI given to its input.
is held and its VPI is sent to the delayed output. In the first embodiment described above, 1 or O is held simply to indicate the presence or absence of a detection output, but in this example, VPI (for example, an 8-bit signal) is held. Furthermore, this delay circuit 13 is set so that a plurality of different delay times are output from its taps. That is, in FIG. 2, two taps, Sl and Sm, are illustrated for a small value S, and T1, Tk, and Tn are illustrated for a large value T.

In this device, the counter means is a control section 4 indicated by a dashed line.
1 and a count value holding section (column D of memory area 42 and column C of memory area 43) that holds the count value. That is, the counter means is provided individually for each of the plurality of VPIs, and the control unit 41 identifies the VPI and delay time for each output with a different delay time of each delay circuit, and adds and subtracts the counted value to this memory area. including.

The threshold value holding circuit also operates in this memory area 42 and 4.
3 corresponds to the Y column and the X column, and a plurality of threshold values corresponding to a plurality of VPIs and a plurality of delay times (S or T) are held. Furthermore, the comparison/judgment circuits 44 and 45 are configured to individually access the memory area 42 or 43 for a plurality of VPIs and a plurality of delay times, compare the count value with a threshold value, and send out a judgment output. be.

The count value holding section of the counter means and the threshold value holding circuit are held in one memory as a table corresponding to a plurality of VPIs and a plurality of delay times, and the delay circuit 1
3 is a FIFO (first-in first-out memory), which includes a control section 41 of the counter means and a comparison/judgment circuit (44, 4).
5) is composed of one program control circuit (CPU).

To explain the control unit 41, each tap of the delay circuit 13 has SR5Sm5Tβ, Tk,
Memories 51 to 55 are provided for temporarily storing fixed values such as Tn, etc., as well as VPI taken in from that tap of the delay circuit 13.

Counter value controls 856 and 57 identify these VPIs and organize and store them as tables in memory areas 42 and 43 for each VPI and for each tap value S(]).

In this table, D (i) and C (1) are each a count value, and Y (i) and X (i) are each a threshold value.

Comparison and judgment circuits 44 and 45 compare and judge the count value and the corresponding threshold value for the row of this table in which there is a new write, or more precisely, a new addition count. As a result of the comparison and judgment, if the counted value exceeds the threshold value, it is a violation of the contract conditions, and a judgment output is sent to the terminal 17. terminal 17
The signals are processed by a circuit not shown, and the cells detected at that time are discarded.

This process is executed within 1 second and 11 hours. When the cell is discarded, the negative digit signal of the delay circuit 13 is cleared to rO'' (meaning that there is no VPI), assuming that the cell has been discarded.

In this way, cell traffic can be monitored in parallel for multiple VP Is, multiple different delay times, and multiple different thresholds.

FIG. 3 is an explanatory diagram of an apparatus according to a third embodiment of the present invention.

This is the F used as the delay circuit 13 in the second embodiment.
The IFO memory is configured as a cascade connection of a plurality of FIFO memories. By configuring like this,
There is no need to use a special circuit for the FIFO memory tap, and it can be realized using general-purpose hardware.

As yet another example, in each of the above embodiments, a threshold value Y(i) or X(1) corresponding to the count value C(1) or D(i) of the color counter is entered in advance, and a new detection is performed. If the configuration is configured such that the counted value is subtracted for the cells obtained from the delayed output of the delay circuit, and this counted value is added for the cells obtained from each delay output of the delay circuit, the comparison judgment is made based on whether the counted value exceeds 0 or falls below. You will be able to do that. Therefore, there are advantages that the memory area is saved and the configuration of the comparison/judgment circuit is simplified. The present invention can be implemented with this configuration.

〔Effect of the invention〕

As explained above, according to the present invention, even in a contract where multiple conditions are set or different conditions are set for multiple different VPIs, the number of hardware is determined according to the number of set conditions. Cell traffic can be monitored using reasonably sized hardware without the need for expansion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention. FIG. 2 is a block diagram of an apparatus according to a second embodiment of the present invention. FIG. 3 is a partial block diagram of a device according to a third embodiment of the present invention. FIG. 4 is a block diagram of a conventional device. FIG. 5 is a diagram showing an example of the structure of a cell. FIG. 6 is a diagram showing how cells are multiplexed on a transmission path. FIG. 7 is a configuration diagram when two cell monitoring devices are required. 11... Terminal into which the monitored signal is input, 12... Cell detection circuit, 13... Delay circuit, 14... Counter,
15...Threshold value holding circuit, 16...Comparison judgment circuit, 1
7... Terminal to which judgment output is sent, 18... Counter control circuit, 24... Counter, 25... Threshold value holding circuit, 26... Comparison/judgment circuit, 28... Counter control circuit, 31.32...OR circuit, 35...VP
I identification circuit, 41...control unit of counter means, 42.
43...Memory area, 44.45...Comparison/judgment circuit (comprised of CPU), 56.57...Counter value control section (comprised of CPU), 51-5
5...-Memory for time storage. Patent Applicant Nippon Telegraph and Telephone Corporation Agent Patent Attorney Naotaka Ide (and 1 other person) Embodiment Fig. 1 Fig. 3 Embodiment Fig. 3 Conventional example Fig. 4 Cell -> Cell - Transmission line Transmission line Figure 7

Claims (1)

[Claims] 1. A cell detection circuit (12) that synchronizes with the monitored signal and detects the presence or absence of a valid cell in the signal; and a cell detection circuit (12) that receives the detection output of this cell detection circuit (12) after S cell time. a delay circuit (13) for sending out a first delayed output; and a first counter means (14) for which the detection output of the cell detection circuit (12) is an addition input and the delayed output is a subtraction input.
, 18), a first threshold holding circuit (15) that holds a threshold (Y) over S cell time, and a threshold (Y) held by this first threshold holding circuit and the first counter means (14). ) and a first comparison/judgment circuit (16) that sends out a first judgment output by comparing the counted value of ) is provided with a terminal for sending out a second delayed output, the second counter means (24
, 28), a second threshold holding circuit (25) that holds the threshold (X) over T cell time, and a threshold (X) held by this second threshold holding circuit and the second counter means (24). ) and a second comparison/judgment circuit (26) that compares the counted value of the cell traffic with the count value of the cell traffic monitor (26) and sends out a second determination output. 2. a cell detection circuit that synchronizes with the monitored signal and detects the presence or absence of a valid cell in the signal; a delay circuit that receives the detection output of this cell detection circuit as an input and sends out a delayed output after a set delay time; a counter means having the detection output of the cell detection circuit as an addition input and the delayed output as a subtraction input; a threshold holding circuit holding a threshold over a set delay time; In the cell traffic monitoring device, the set delay time is divided into a short time S and a long time T, and is detected by the cell detection circuit. The virtual path number (hereinafter referred to as VPI) of the cell
tifier), the delay circuit holds the VPI given to its input and sends the VPI to its delayed output, and a plurality of different delay times are set, and the counter means: The count value holding unit has multiple VPIs
The threshold value holding circuit includes a control unit that is individually provided for each delay circuit, and that identifies the VPI and delay time for each output with a different delay time of each delay circuit, and adds and subtracts a count value to this memory area. A plurality of threshold values corresponding to a plurality of VPIs and a plurality of delay times are held, and the comparison judgment circuit is configured to individually compare the plurality of VPIs and the plurality of delay times with the respective threshold values and send out a judgment output. A cell traffic monitoring device featuring: 3. The cell traffic monitoring device according to claim 2, wherein the count value holding section of the counter means and the threshold value holding circuit are held in one memory as a table corresponding to a plurality of VPIs and a plurality of delay times. 4. The cell traffic monitoring device according to claim 3, wherein the delay circuit is a FIFO (first-in first-out memory), and the control section of the counter means and the comparison judgment circuit are constituted by one program control circuit (CPU).