JP2905884B2 - Cell traffic monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for packet communication. The present invention relates to a technique for monitoring traffic of a cell (a fixed-length packet is referred to as a "cell" in this specification) transferred in a packet communication network.

INDUSTRIAL APPLICABILITY The present invention is used for policing in which when a cell is transmitted over traffic that has been previously contracted, the cell is discarded as a violation of the contract.

[Conventional technology]

In a packet communication network, if a large number of cells arrive at one relay point at once, smooth operation cannot be performed. For this reason, the telecommunications carrier that operates the packet communication network must not transmit more than n cells within consecutive m-cell hours in the contract with the user, and the telecommunications carrier violates this. Discarding the transmitted cell is a condition of the usage contract. For example, m =
If 5, n = 3, up to three cells can be transmitted within five consecutive cell times, but if cells are transmitted beyond this, the cells will be discarded. Monitoring and discarding for this purpose is called policing, and is performed automatically and continuously at the entrance of the packet communication network.

FIG. 4 is a block diagram of a conventional apparatus. This circuit has been filed by the present applicant as a patent application (Japanese Patent Application No. 2-130464, not disclosed at the time of filing the present application). The circuit shown in FIG. 3 is a circuit that can transmit up to three cells in five consecutive cell times, but monitors so that four or more cells are not allowed.

In FIG. 4, a monitored signal is input to a terminal 1. The cell detection circuit 2 synchronizes with the monitored signal and sends out a detection output when there is a valid cell in the signal. The delay circuit 3 receives the detection output as an input, and the delay circuit 3 is constituted by a shift register.
Shifted to the right in the figure step by step. That is, the delay circuit 3 has its input sent to the delay output after m cell times. The detection output of the cell detection circuit 2 is input to the addition input of the up / down counter 4, and the delay output of the delay circuit 3 is input to the subtraction input. The threshold value holding circuit 5 holds a threshold value n set by a contract. The threshold value n is compared with the content S of the up / down counter 4. If S> n, an inhibit output is sent to the terminal 7. The cell is discarded by a device (not shown) due to the prohibited output.

In the circuit configured as described above, the number of cells detected in the past m cell time is stored in the up / down counter 4. When the number exceeds the set threshold value n, the prohibited output is output to the terminal 7. Sent to When the prohibition output is sent to the terminal 7, the cell that has been detected on the transmission line by a circuit (not shown) is discarded. Since the cell has been discarded, the value of the first stage of the counter 4 is cleared by the judgment output.

Here, not only the contract conditions are set for m and n as described above, but also the conditions are set on condition that they do not exceed X cells in a large value T cell time and that they are dispersed on average. The value of T is, for example, tens of thousands, and the value of X is, for example, several hundreds. Setting such conditions is extremely advantageous for a communication company to reduce the multiplicity of the prepared transmission path.

[Problems to be solved by the invention]

This prior art device is an excellent circuit that can monitor the number of cells over the cell time m for any continuous phase.
The cell time m is determined by the number of stages of the shift register. Therefore, even if an extremely large value is set as the value of m as described above, there is a disadvantage that the hardware becomes large because an m-stage shift register must be prepared. When the value of m exceeds 10,000, the scale of the hardware becomes impractical.

FIG. 5 is a diagram in which the abscissa indicates the value of m and the ordinate indicates the required hardware amount by the number of bits. VPI as a parameter
The case where the number of (Virtual Path Identifier: virtual path number) is 1000, 2000, and 4000 respectively is shown. VPI
Is an identification number for each virtual route added to the header of each cell, and when monitoring a transmission cell for one terminal as shown in the example of FIG. In the case of monitoring cells transmitted from multiple terminals and corresponding to multiple terminals at an intermediate relay node,
VPI identification is required. As can be seen from FIG. 5, if the value of m is tens of thousands, hardware of about one million bits is required for the cell monitoring device, and it becomes impossible to design a realistic device.

Further, in this prior art apparatus, contract conditions are set such that a large value of m (indicated as T in this specification) and a large value of n (indicated as X in this specification) are dispersed on average. In such a case, it cannot be dealt with rationally.

The present invention is an improvement of the present invention, which provides a cell traffic monitoring device that can easily handle an extremely large value of m with a small hardware, and also monitors a small value of m. It is intended to provide a device.

It is a further object of the present invention to provide a cell traffic monitoring device that allows transmission of X cells during a T cell time and can cope with a case where the contract condition is that distribution is averaged.

[Means for solving the problem]

The device of the present invention monitors the number of cell detection outputs over m cell times (m is an integer of 2 or more), and allows the transmission of X cells at the T cell time using the detection output of the cell detection circuit as an additional input. A second counter circuit which periodically takes the average cell detection rate (X / T) as a subtraction constant as a subtraction input, and counts the second counter circuit with a second threshold value (N). It is characterized in that it is determined by comparison.

Since the average cell detection rate (X / T) is not always an integer, when the subtraction constant given to the addition input and the subtraction input of the second counter circuit is multiplied by T, the count value of the second counter circuit always becomes an integer.

Further, the count value of the first counter circuit may be input to the addition input of the second counter circuit every m cell times. In that case, the average cell detection rate is the average cell detection rate per m cell time.

[Action]

The second counter circuit is a non-negative operation circuit (a circuit that does not become a negative value and the subtraction stops at zero). The second counter circuit subtracts the average cell detection rate (X / T) as a subtraction constant at a constant period. Therefore, the detection output of the cell detection circuit is given to the addition input of the second counter circuit,
It monitors that the counted value does not exceed a preset threshold (N). The threshold value N is the constant period 1 cell time, when the subtraction constant is the average cell detection rate X / T per cell time, a X-X ² / T.

〔Example〕

FIG. 1 is a block diagram of the first embodiment of the present invention. In this embodiment, a monitored signal is input to a terminal 1. A cell detection circuit 2 is provided which detects the presence or absence of a valid cell in the monitored signal in synchronization with the monitored signal. The cell clock signal is input to a terminal 10. This cell clock signal is a clock signal in which one pulse arrives every cell time.

When a valid cell is detected, "1" is transmitted to the detection output of the cell detection circuit 2, and "0" is transmitted when no valid cell is detected. A shift register 3 which is a first delay circuit which receives this detection output as an input and shifts to the right every cell time, and a delay output which similarly receives this detection output as an addition input and is shifted out of the m-th stage of the shift register 3 And a first counter circuit 4 which takes a subtraction input as a subtraction input. Further, a first threshold value holding circuit 5 for holding a threshold value (n) over m cell times, and a threshold value (n) held by the first threshold value holding circuit and a count value of the first counter circuit 4 are compared. And a first comparison / determination circuit 6 for transmitting a first determination output.

Here, as a feature of the cell traffic monitoring device of the present invention, a second counter circuit 41 is provided. The detection output of the cell detection circuit 2 is given to the addition input of the second counter circuit 41. Further, an average cell detection rate (X / T) per cell time, which is a predetermined subtraction constant, is given to the subtraction input of the second counter circuit 41 from the subtraction constant holding circuit 14 every cell time. . Further, a second threshold value holding circuit 51 for holding a second threshold value (N), a threshold value (N) held by the second second threshold value holding circuit 51 and a count value of the second counter circuit 41 And a second comparison / determination circuit 61 for comparing and determining the same and sending out a second determination output. The logical sum of the first judgment output and the second judgment output is calculated by the OR circuit 11 and sent to the terminal 7. The signal at the terminal 7 is processed by a device (not shown), and then arrives at that node, and the currently detected cell is discarded without being relayed. Since this processing is executed within one cell time and the cell is discarded, the value “1” of the first stage of the shift register 3 is cleared when the judgment output of the terminal 7 is transmitted.

Both the first counter circuit 4 and the second counter circuit 41 are non-negative operation circuits. That is, the count value does not exceed zero and becomes a negative value, and is configured so as to limit zero.

In this device, the counter circuit 4 includes the shift register 3
, That is, the number equal to the number of valid cells detected over the past m cell times is held as a count value. On the other hand, the counter circuit 41 holds a value obtained by periodically subtracting the average cell detection rate as a count value. When this value exceeds the threshold value N, the transmission cell has been transmitted in violation of the contract conditions, and is detected and discarded by the second comparison / determination circuit 61.

As the second counter circuit 41 subtracts the subtraction constant at regular intervals and uses the remainder as the count value, since the bucket has a hole and water is leaking, the leaky bucket (leaking bucket) is generally used. ) Method.

FIG. 2 is a modification of the first embodiment, and is a device in which the contents of the second counter circuit 41 are always considered to be an integer. That is, the multiplying circuit 17 is provided to increase the input to be added to the addition input of the second counter circuit 41 by T times. The threshold value N for comparison and determination is also multiplied by T.

FIG. 3 is a block diagram of the apparatus according to the second embodiment of the present invention. In this example, the addition input of the second counter circuit 41 is used as the count value of the first counter circuit 4. First counter circuit 4
Since the number of valid cells detected over the past m cell times is stored in the second counter circuit 41, the number of valid cells detected over the past m cell times (not one cell time) is added. The number given to the addition input of the second counter circuit 41 every time is equal to that of the first embodiment. Since the subtraction constant is also given every m cell time, the average cell detection rate per m cell time (mX / T) is obtained by multiplying the subtraction constant of the first embodiment by m. The control clock signal of the second counter circuit 41 is a clock signal obtained by dividing the cell clock signal of the terminal 10 by m by the frequency dividing circuit 9. The threshold value N is the same as the threshold value of the first embodiment.

In the configuration of the second embodiment, the first counter circuit 4
Operates every one cell time, but since the second counter circuit 41 operates every m cell times, the second counter circuit 41 can be constituted by a lower speed hardware. Further, there is an advantage that power consumption is reduced. However, since the monitoring interval is every m cells, it becomes coarser than the case where the monitoring is performed every one cell.

In each of the above embodiments, the shift register 3, the counter circuits 4 and 41 have been described as being constituted by hardware, however, these shift registers 3, the counter circuits 4 and 41 are composed of one memory (RAM), A circuit having a similar function can be realized by firmware combining a control circuit (CPU) and a memory (ROM) for storing a program. Further, the threshold holding circuits 5 and 51 and the comparison determination circuits 6 and 61 can be incorporated in the firmware. These memories and CPUs can be easily and inexpensively configured using generally mass-produced hardware.

If this is achieved by firmware, the first
A plurality of the circuits illustrated in FIGS. 3 to 3 can be simultaneously configured in a small number of combinations of memory and program control circuits. This is extremely useful as a device provided at a node in a communication network that requires parallel policing of many VPIs.

〔The invention's effect〕

As described above, according to the present invention, even when monitoring is performed for a long time by setting m to an extremely large value under the condition to be monitored and the condition that up to n cells are allowed within the m cell time, The amount of hardware does not increase in proportion to the value, it can be easily realized with realistic small hardware, and the average is that transmission does not exceed X cells on average in the T cell time. It is also possible to realize a cell traffic monitoring device that can reasonably deal with contract conditions based on a rate.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention. FIG. 2 is a block diagram showing a modification of the first embodiment of the present invention. FIG. 3 is a block diagram of a device according to a second embodiment of the present invention. FIG. 4 is a block diagram of a conventional apparatus. FIG. 5 is a diagram for explaining an increase in the amount of hardware with respect to the value of m. Reference numeral 1 denotes a terminal to which a monitored signal is input; 2 denotes a cell detection circuit; 3
.., A shift register as a delay circuit, 4... A first counter circuit, 5... A first threshold value holding circuit, 6... A first comparison and judgment circuit, 7.
10, a terminal to which a cell clock signal is input; 11, an OR circuit; 14, a subtraction constant holding circuit; 41, a second counter circuit;
51 ... second threshold holding circuit; 61 ... second comparison / judgment circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-183938 (JP, A) JP-A-1-183939 (JP, A) JP-A-4-25255 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H04L 12/28 H04L 12/56

Claims (2)

(57) [Claims] 1. A cell detection circuit (2) for detecting presence or absence of a valid cell in a signal to be monitored in synchronization with a monitored signal, and having a detection output of the cell detection circuit (2) as an input and outputting a delay output after m cell times. A delay circuit (3) to send out, and a first counter circuit (4) using the detection output of the cell detection circuit (2) as an addition input and the delay output as a subtraction input.
A first threshold value holding circuit (5) for holding a threshold value (n) over m cell times, a threshold value (n) held by the first threshold value holding circuit, and a total of the first counter circuit (4). And a first comparison / determination circuit (6) for comparing the value with a numerical value and transmitting a first determination output, wherein the count value of the first counter circuit (4) is used as an addition input, and m A second counter circuit (41) in which the average cell detection rate per cell time (Xm / T) is periodically subtracted and the input is executed every m cell times, and over a T cell time (T> m) A second threshold value holding circuit (51) for holding a threshold value (N); comparing a threshold value (N) held by the second threshold value holding circuit with a count value of the second counter circuit (41); And a second comparison / determination circuit (61) for transmitting the second determination output. Cell traffic monitoring device. 2. The cell traffic monitoring device according to claim 1, further comprising an OR circuit for calculating a logical sum of the first judgment output and the second judgment output.