JPH04162847A - Cell traffic monitor - Google Patents

Abstract

PURPOSE:To realize the cell traffic supervisory equipment simply coping with by a small hardware by providing a 1st and a 2nd counter circuit receiving an average cell detection rate of a short period and a long period as a subtraction input periodically. CONSTITUTION:First and 2nd counter circuits 41, 42 are non-negative arithmetic circuits, and the 1st counter circuit 41 is subtracted by a subtraction constant being an average cell detection rate (n/m) of a prescribed short period. Thus, a detection output of a cell detection circuit 2 is given to an addition input of the 1st counter circuit 41 to monitor it that the count does not exceeds a preset threshold level of a short period. Moreover, the 2nd counter circuit 42 is subtracted by a subtraction constant being an average cell detection rate (X/T) of a prescribed long period. Thus, a detection output of the cell detection circuit 2 is given to an addition input of the 2nd counter circuit 42 to monitor it that the count does not exceeds a preset threshold level of a short period. Even when a value (m) is set to a very large value on the condition that up to n-cells are allowed in an m-cell time, the cell traffic supervisory equipment is realized, which is realized simply and rationally without increasing the hardware quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used for packet communication. The present invention relates to a technique for monitoring traffic of cells (fixed-length packets are referred to as "cells" in this specification) transferred in a packet communication network.

The present invention is used for policing, in which when a cell is transmitted in excess of the traffic that has been contracted for, the cell is discarded as a violation of the contract.

[Conventional technology]

In a packet communication network, if a large number of cells arrive at one relay point at the same time, smooth operation becomes impossible. For this reason, telecommunications carriers operating packet communication networks have agreements with users that: ■ Users must not transmit more than n cells within m consecutive cell periods; ■ Telecommunications carriers must: A condition of the usage contract is that cells transmitted in violation of the rules are discarded. For example m=
5. If n=3, up to 3 cells can be transmitted within a continuous 5-cell period, but if a cell is transmitted beyond this time, the cell will be discarded.

Monitoring and discarding for this purpose is called borishing, and is automatically and continuously performed at the entrance of the packet communication network.

FIG. 4 is a block diagram of a conventional device.

Even the applicant of this application applied for a patent for this circuit (Japanese Patent Application No. 2-13
No. 0464, unpublished at the time of filing of this application).

The circuit shown in FIG. 4 is a circuit that monitors so that up to three cells can be transmitted in a continuous five-cell period, but four or more cells are not allowed.

In FIG. 4, a monitored signal is input to terminal 1. The cell detection circuit 2 synchronizes with this monitored signal and sends out a detection output if there is a valid cell in the signal. The delay circuit 3 receives this detection output as an input, and is constituted by a shift register, and is shifted one stage to the right in the figure every cell time by a clock signal (not shown). That is, this delay circuit 3 sends its input to the delayed output after m cell times.

The detection output of the cell detection circuit 2 is input to the addition input of the up-down counter 4, and the delayed output of the delay circuit 3 is input to the subtraction input thereof. The threshold value holding circuit 5 holds the threshold value n set according to the contract.

This threshold value n is compared with the content S of the up/down counter 4, and if S>n, a prohibition output is sent to the terminal 7. Due to this prohibition output, the cell is discarded by a device not shown.

In the circuit configured in this manner, the number of cells detected in the past m cell time is stored in the up/down counter 4, and when this exceeds the set threshold value n, the prohibition output is output to the terminal 7. will be sent to. When a prohibition output is sent to terminal 7, the cell currently detected on the transmission path is discarded by a circuit not shown. Since the cell was discarded,
The value of the first stage of the up/down counter 4 is cleared by the judgment output.

[Problem to be solved by the invention]

This conventional device is an excellent circuit that can monitor the number of cells over a cell time m for any continuous phase.
The cell time m is determined by the number of stages of the shift register. Therefore, even if an extremely large value is set as the value of m as described above, there is a drawback that the hardware becomes large because m-stage shift registers must be prepared. When the value of m exceeds 10,000, the scale of the hardware becomes unrealistic.

FIG. 5 is a diagram in which the horizontal axis represents the value of m, and the vertical axis represents the amount of required hardware in bit numbers. VP as a parameter
I (Virtual Path Identifier)
r: verti cell bus number) is 1000.2 each
The case of 000.4000 will be shown. VPI is an identification number on the virtual route side attached to the header of each cell,
As shown in the example in Figure 4 above, when monitoring transmitted cells for one terminal, classification by VPI is not necessarily necessary, but cells transmitted from multiple terminals and applied to multiple terminals at an intermediate relay node are monitored. VPI
identification is required.

As can be seen from Figure 5, if the value of m is arbitrary, a cell monitoring device would require 71-doware of around 100 bits, making it impossible to design a realistic device. .

Another problem is that when the original signal is conversational audio such as a telephone conversation, sound sections and silent sections appear alternately, and the number of cells transmitted in the sound section is smaller than that in the silent section. The number will be overwhelmingly large. In other words, the transmitted cells are concentrated in bursts.

In such a case, optimal management cannot be achieved with the simple contract conditions of up to n cells in m cell time as in the conventional system. That is, if borsing is performed under strict conditions during a period when transmitting cells are concentrated, the voice of the call will become unclear. Furthermore, if conditions corresponding to a period in which transmission cells are concentrated are applied to a long period, the efficiency of use of the transmission path will deteriorate. To this end, it has been considered to devolution the number of cells to be transmitted under different conditions for short cycles and long cycles. To this end, in the conventional device described above, the devices illustrated in FIG. 4 must be provided separately for short periods and long periods.

The present invention improves this by providing a cell traffic monitoring device that can easily handle extremely large values of m with small hardware, and also provides a cell traffic monitoring device that can also monitor small values of m. The purpose is to provide equipment. Furthermore, the present invention allows for the transmission of n cells every m short-cycle cell times, and allows the transmission of X cells every long-cycle T cell time, and requires that these be distributed evenly as a condition of the contract. It is an object of the present invention to provide a cell traffic monitoring device that can handle the following cases.

[Means to solve the problem]

The device of the present invention includes a cell detection circuit (2) that synchronizes with a monitored signal and detects the presence or absence of a valid cell in the signal, and the detection output of this cell detection circuit (2) as an addition input, and a short-cycle average A first counter circuit (41) that periodically inputs the cell detection rate (n/m) for subtraction, a first threshold holding circuit (51) that holds a short-period threshold, and a first threshold holding circuit (51) that holds a short-period threshold. a first comparison judgment circuit (61) that compares a threshold value held by the circuit with a count value of the first counter circuit (41) and sends out a first judgment output; ) as an addition input and a long-period average cell detection rate (X/T) as a periodic subtraction input, and a second threshold that holds the long-period threshold A holding circuit (52), a threshold held by this second threshold holding circuit, and the 20th counter circuit (4).
2) and a second comparison/determination circuit (62) that compares the count value with the count value of 2) and sends out a second determination output.

It is desirable to have a configuration including an OR circuit <11) that calculates the logical sum of the first determination output and the forward rotation second determination output.

[Effect]

The first and 20th counter circuits are non-negative arithmetic circuits (circuits that do not produce negative values and stop subtraction up to zero). This No. 1 counter circuit has an average cell detection rate (n
/m) as a subtraction constant. therefore,
The detection output of the cell detection circuit is applied to the addition input of this No. 10 counter circuit, and it is monitored that the counted value does not exceed a preset short-cycle threshold. The threshold value of this short period is n-n2 when the constant short period is m cell times, the subtraction constant is a ratio of n to m cell times, and the average cell detection rate per cell time is n/m. /m. Further, the No. 20 counter circuit subtracts the average cell detection rate (X/T) at a constant long period as a subtraction constant. Therefore, the detection output of the cell detection circuit is applied to the addition input of this 20th counter circuit, and it is monitored that the counted value does not exceed a preset short-cycle threshold. The threshold value of this long period is X-X2/T when the above-mentioned constant period is T cell time and the subtraction constant is the average cell detection rate per cell time is X/T.

〔Example〕

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention. In this embodiment, the signal to be monitored is input to terminal 1. A cell detection circuit 2 is provided which synchronizes with this monitored signal and detects the presence or absence of valid cells in the signal. When a valid cell is detected, "1" is sent to the detection output of this cell detection circuit 2, and "0" is sent when no valid cell is detected.

A 10th counter circuit 41 which uses the detection output of this cell detection circuit 2 as an addition input and periodically subtracts the short-cycle average cell detection rate n/m as an input, and a first threshold value that holds the short-cycle threshold value. Holding circuit 51 and this first threshold holding circuit 51
A first comparison/judgment circuit 6 that compares the threshold value held by the counter circuit 41 with the count value of the first counter circuit 41 and sends out a first judgment output.
1.

Further, a 20th counter circuit 42 which takes the detection output of the cell detection circuit 2 as an addition input and periodically takes the long-period average cell detection rate X/T as a subtraction input, and a second counter circuit 42 that holds a long-period threshold value Threshold value holding circuit 52 and this second threshold value holding circuit 52
and a second comparison/determination circuit 61 that compares the threshold value held by the second counter circuit 42 with the count value of the second counter circuit 42 and sends out a second determination output.

The logical sum of the first judgment output and the second judgment output is calculated by the OR circuit 11, and the judgment output of the device is sent to the terminal 7. The signal at terminal 7 is sent to a device not shown, and the cell that was about to be relayed at that time is discarded. Since that cell has been discarded, the count values of counter circuits 41 and 42 are subtracted by 1 via monomulti circuit 12.

First counter circuit 41 and twenty counter circuit 42
Both are non-negative arithmetic circuits. In other words, the count value never exceeds zero and becomes a negative value, and is configured so that zero is the limit.

FIG. 2 illustrates the count values and threshold values of this device. Time is plotted on the horizontal axis, and the count value of the counter circuit 41 is shown by a broken line, and the count value of the counter circuit 42 is shown by a solid line. The arrow at the bottom indicates the timing at which a valid cell is detected. In this example, when m=5, n=2, Tm2O3, and X=10, the counter circuit 41 has 1
N/m=215 is subtracted every cell time, and the counter circuit 42 is subtracted by X/T=1/10 every cell time. The △ mark in the figure indicates a state in which the count value of the counter circuit 41 exceeds the short cycle threshold and is discarded.

Two counter circuits, such as 4L 42, which subtract a subtraction constant at regular intervals and use the remainder as a count value are equivalent to a bucket with a hole and water leaks out, so it is generally called a leaky packet (a leaky bucket). ) method.

FIG. 3 is a block diagram of an apparatus according to a second embodiment of the present invention. In this example, the number of counters that count the number of detected valid cells is reduced, and the device of the first embodiment has a 10th counter circuit and a second counter circuit, but a single counter circuit is used. It is made up of only 43.

This counter circuit 43 does not apply leaky packets, and is separately provided with a first subtraction counter 71 for short periods and a second subtraction counter 72 for long periods, each with a cell detection rate (n/m or X/ T) is periodically accumulated and added every cell time, and the value of this subtraction counter 71 or 72 is added to each threshold value to perform a comparative judgment.

I will explain in more detail. A cell clock signal is input to terminal 1. This cell clock signal is frequency-divided by m in a frequency dividing circuit 91 and drives the latch operation of the latch register 13. For short cycles, the count value S of the counter circuit 43 is calculated at each start point of the short cycle. is latched into the latch register 13. On the other hand, in the subtraction counter 71, the short-cycle cell detection rate (n
/m) is cumulatively added. If the count value of the subtraction counter 71 is M, the arithmetic circuit 81 calculates Cn + S o +
M ] is calculated, and this value and the current value S of the counter circuit 43 are compared and determined by the comparison and determination circuit 61. More generally speaking, when n+so +M S > 0, the first decision a is sent.

For long periods, a subtraction counter 72 cumulatively adds the long period cell detection rate (X/T) every cell time. When the count value of the subtraction counter 72 is 2, the calculation circuit 82 calculates CN+M:), and the comparison judgment circuit 62 compares and judges this value with the current value S of the counter circuit 43. More generally, when N+Z-3>0, the second decision a is sent.

The subtraction counter 71 is reset when the first judgment output is sent out, and the subtraction counter 72 is reset when the second judgment output is sent out.

Regarding each of the embodiments described above, each counter circuit and the like were explained to be constructed by hardware.
These are one memo+J (RAM), a program control circuit (CPU), and a memo that stores programs! J
A circuit with similar functions can be realized using firmware combined with (ROM). Furthermore, a threshold value holding circuit and a comparison/judgment circuit can also be incorporated into the firmware.

These memories and CPUs can be easily and inexpensively constructed using generally mass-produced hardware.

If this is accomplished by firmware, multiple of the circuits illustrated in FIG. 1 or 3 can be implemented simultaneously in a small number of memory and program control circuit combinations. This is extremely useful as a device in a node within a communications network that requires parallel policing of a large number of VPIs.

〔Effect of the invention〕

As explained above, according to the present invention, the conditions to be monitored,
Even when monitoring for a long time by setting m to a very large value under the condition that up to n cells are allowed within m cell time, the amount of hardware will increase in proportion to that value. It can be easily realized with practical small hardware, and on average n in m cell time.
It is also possible to realize a cell traffic monitoring device that reasonably accommodates contract conditions based on average rates such as not transmitting beyond cells and not transmitting beyond X cells on average during T cell time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram of the operation of the apparatus according to the first embodiment of the present invention. FIG. 3 is a block diagram of an apparatus according to a second embodiment of the present invention. FIG. 4 is a block diagram of a conventional device. FIG. 5 is a diagram illustrating an increase in the amount of hardware with respect to the value of m. l...Terminal to which the monitored signal is input, 2...Cell detection circuit, 3...Delay circuit, 4...Up/down counter, 5...Threshold value holding circuit, 6...Comparison judgment circuit,
7... Terminal to which judgment output is sent, 11... OR circuit, 12... Mono multi circuit, 13... Latch register, 41... No. 1 counter circuit, 42...
No. 20 counter circuit, 43... counter circuit, 51.
...first threshold value holding circuit, 52...second threshold value holding circuit, 61...first comparison judgment circuit, 62...second comparison judgment circuit, 71...first subtraction counter, 72・
... second subtraction counter, 81 ... first arithmetic circuit,
82... Second arithmetic circuit, 91... Frequency dividing circuit. Patent applicant Nippon Telegraph and Telephone Corporation - Agent Patent attorney Naotaka Ide' (and 1 other person) ゛Figure 1 Figure 3 Conventional example Figure 4 Ko 5

Claims (1)

[Claims] 1. A cell detection circuit (2) that synchronizes with a monitored signal and detects the presence or absence of a valid cell in the signal;
) a first counter circuit (41) which uses the detection output of the cell as an addition input and periodically subtracts the short-period average cell detection rate (n/m) as an input, and a first threshold value that holds the short-period threshold value. a holding circuit (51); a first comparison judgment circuit (51) that compares the threshold held by the first threshold holding circuit with the count value of the first counter circuit (41) and sends out a first judgment output; 61), a second counter circuit (42) which takes the detection output of the cell detection circuit (2) as an addition input, and takes the long-period average cell detection rate (X/T) as a periodic subtraction input; A second threshold holding circuit (52) that holds a cycle threshold; and a second judgment output by comparing the threshold held by this second threshold holding circuit with the count value of the second counter circuit (42). A cell traffic monitoring device comprising: a second comparison/judgment circuit (62) that sends out a second comparison/judgment circuit (62). 2. The cell traffic monitoring device according to claim 2, further comprising an OR circuit (11) for calculating a logical sum of the first determination output and the second determination output. 3. A cell detection circuit (2) that synchronizes with the monitored signal and detects the presence or absence of valid cells in the signal;
); a first threshold holding circuit (51) that holds a short-cycle threshold;
S_0), a first subtraction constant counter (71) that periodically adds up the average cell detection rate (n/m), and the counter circuit at the starting point of each short cycle. Let the count value of (43) be S_0,
The current count value of the counter circuit (43) is S, the count value of the first subtraction constant counter (71) is M,
When the short-cycle threshold held by the first threshold holding circuit (51) is n, a first comparison judgment means (81, 61) sends out a first judgment output when n+S_0+M-S>0. a second threshold holding circuit (52) that holds a long-period threshold; and a second subtraction constant counter (72) that periodically adds up the long-period average cell detection rate (X/T). When the count value of the second subtraction constant counter (72) is Z and the long-period threshold held by the second threshold value holding circuit (52) is N, then when N+Z-S>0, the second A cell traffic monitoring device characterized by comprising: a second comparison/determination means (82, 62) for transmitting a determination output.