JP2855235B2 - Cell traffic monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for packet communication. The present invention relates to a technique for monitoring traffic of a cell transferred in a packet communication network (in this specification, a fixed-length packet is referred to as a “cell”).

INDUSTRIAL APPLICABILITY The present invention is used for policing in which when a cell is transmitted over traffic that has been previously contracted, the cell is discarded as a violation of the contract.

[Conventional technology]

In a packet communication network, if a large number of cells arrive at one relay point at once, smooth operation cannot be performed. For this reason, the telecommunications carrier that operates the packet communication network must not transmit more than n cells within consecutive m-cell hours in the contract with the user, and the telecommunications carrier violates this. Discarding the transmitted cell is a condition of the usage contract. For example, m =
If 5, n = 3, up to three cells can be transmitted within five consecutive cell times, but if cells are transmitted beyond this, the cells will be discarded. Monitoring and discarding for this purpose is called policing, and is performed automatically and continuously at the entrance of the packet communication network.

FIG. 3 is a block diagram of a conventional apparatus. This circuit has been filed by the present applicant as a patent application (Japanese Patent Application No. 2-130464, not disclosed at the time of filing the present application). The circuit shown in FIG. 3 is a circuit that can transmit up to three cells in five consecutive cell times, but monitors so that four or more cells are not allowed.

In FIG. 3, a monitored signal is input to a terminal 1. The cell detection circuit 2 synchronizes with the monitored signal and sends out a detection output when there is a valid cell in the signal. The delay circuit 3 receives the detection output as an input, and the delay circuit 3 is constituted by a shift register.
Shifted to the right in the figure step by step. That is, the delay circuit 3 has its input sent to the delay output after m cell times. The detection output of the cell detection circuit 2 is input to the addition input of the up / down counter 4, and the delay output of the delay circuit 3 is input to the subtraction input. The threshold value holding circuit 5 holds a threshold value n set by a contract. The threshold value n is compared with the content S of the up / down counter 4. If S> n, an inhibit output is sent to the terminal 7.

In the circuit configured as described above, the number of cells detected in the past m cell time is stored in the up / down counter 4. When the number exceeds the set threshold value n, the prohibited output is output to the terminal 7. Sent to When the prohibition output is sent to the terminal 7, cells on the transmission line are discarded by a circuit (not shown).

Here, m and n are contracted for small values as described above, and large values, for example, m = 1000
A condition may be set such that 0, n = 300, ie, not exceeding 300 cells for 10,000 cell times. Further, both the small value and the large value may be set as contract conditions. This is because setting a large value of m is advantageous because the multiplexing effect that many users can share the transmission path is increased. FIG. 4 shows m on the horizontal axis.
FIG. 9 is a diagram showing the multiplexing effect as a relative index on the vertical axis when n is 300. A relative index of 10 with respect to a relative index of 1 means that a user with the same capacity can multiplex 10 times. That is, it is found that setting an extremely large value as the value of m is advantageous because the line utilization efficiency is greatly increased.

[Problems to be solved by the invention]

This prior art device is an excellent circuit that can monitor the number of cells over the cell time m for any continuous phase, but the cell time m is determined by the number of stages of the shift register. Therefore, even if an extremely large value is set as the value of m as described above, there is a disadvantage that the hardware becomes large because an m-stage shift register must be prepared. When the value of m exceeds 10,000, the scale of the hardware becomes impractical. FIG. 5 shows the amount of hardware calculated by the number of gates. The value of m is plotted on the horizontal axis, and the number of gates is plotted on the vertical axis.

It is an object of the present invention to improve the above and to provide a cell traffic monitoring device which can easily cope with an extremely large value m with a small hardware.

[Means for solving the problem]

The present invention provides the values m and n when contracting not to transmit more than n cells over successive m cell times.
Is used when m is extremely large, and the delay is set to m / k cell time (m is an integer, and in practice, k and m / k are preferably integers) as one unit period. Alternatively, a shift is performed.

That is, the present invention provides a cell detection circuit (2) which synchronizes with a monitored signal and detects the presence or absence of a valid cell in the signal, a detection output of the cell detection circuit as an addition input, and a read and reset time of m / k cell. Counter circuit performed every time (12)
A delay circuit (3) which receives the output value of the counter circuit as an input value and outputs the input value to a delay output after m (k-1) / k cell times; An up / down counter (4) that receives the output value of the circuit (12) as an addition input; a threshold holding circuit (5) that holds a threshold n; the threshold n, the value S of the up / down counter, and the counter circuit (12) A comparison determination circuit (6) for taking in the output value 1 and determining the magnitude relation between (S + 1) and n.

Furthermore, in addition to the first condition in which the values m and n are set to large values, the present invention also provides a small value m as a second condition.
And n (herein referred to as ms and ns) are also used when contracted together. In this case, the second threshold value holding circuit (21) holding the second threshold value ns
A second comparison / judgment circuit (22) for judging the magnitude relationship between the output value l and the second threshold value ns; and a comparison / judgment circuit (6).
And an OR circuit (23) for calculating a logical sum of the judgment output of the second comparison judgment circuit (22) and the judgment output of the second comparison judgment circuit (22).

[Action]

When the value m is extremely large, the delay or shift is performed in units of m / k, so that the scale of the hardware is reduced.

〔Example〕

FIG. 1 is a block diagram of the first embodiment of the present invention. In this embodiment, a monitored signal is input to a terminal 1. A cell detection circuit 2 is provided which detects the presence or absence of a valid cell in the monitored signal in synchronization with the monitored signal. The cell clock signal is input to a terminal 10. This cell clock signal is a clock signal in which one pulse arrives every cell time. A frequency divider 11 divides the cell clock signal by m / k.
The constant k is a value m determined by a contract that the number of cells to be transmitted does not exceed n over m successive cell times.
It is a value that divides equally. When m on the contract is, for example, 10,000, and if k is 500, m / k becomes 20. At this time, the frequency divider
11 divides the cell clock signal by 20.

Further, the detection output of the cell detection circuit 2 is used as an addition input, and reading and resetting are performed every m / k cell times.
That is, it includes a counter circuit 12 in which reading and resetting are performed by the output of the frequency dividing circuit 11. This counter circuit 12
And a delay circuit 3 which outputs the input value to the delay output after m (k-1) / k cell times.
That is, the delay circuit 3 is constituted by a shift register capable of holding a numerical value 1 (5, 2, 3,..., 4 in the example of FIG. 1) in each of the (k-1) stages. The shift is performed by the output of the circuit 11. Since the output of the frequency dividing circuit 11 is transmitted every m / k cell time, the value input to the delay circuit 3 is (m / k) cell time × (k−1) stage = m (k−1) / It will appear at the delayed output after k cell times.

Further, the delay output of the delay circuit 3 is used as a subtraction input,
An up / down counter 4 that receives the output value 1 of the counter circuit 12 as an addition input, and a threshold value holding circuit 5 that holds a threshold value n
And the threshold value n and the value S of the up / down counter 4
And the output value 1 of the counter circuit 12 is taken in, and (S +
1) a comparison / judgment circuit 6 for judging the magnitude relation between n) and n. In this embodiment, the value of the counter circuit 12 is decremented by one each time one judgment output is sent. The value S of the up-down counter 4 is zero or positive and never negative.

In the circuit configured as described above, when a valid cell is detected by the cell detection circuit 2, the counter circuit 12 accumulates the number over the m / k cell time. When a trigger is input from the frequency dividing circuit 11, the value 1 is input to the delay circuit 3, and the counter circuit 12 is reset to zero. This value 1 is given to the addition input of the up / down counter 4.

In the delay circuit 3, this value is shifted rightward in the figure every m / k cell time. When the m (k-1) / k cell time elapses, that is, after the detection output is first sent from the cell detection circuit 2, the elapsed time inside the counter circuit 12 is added to obtain m (k-1) / k + m / k = L cell time elapses, the value 1 appears at the delayed output. This is provided to the up / down counter 4 subtraction input. In other words, the delay output becomes the up-down counter 4
Is subtracted from it. Thus, at one point in time, the sum of the contents S of the up / down counter 4 and the value 1 of the counter circuit 12 (S + 1) equals the number of detection outputs over m cell times.

This is compared with the threshold value n by the comparison determination circuit 6. That is, the magnitude relationship between (S + 1) and n is determined. Specifically, if (S + 1)> n, a prohibition output is sent to the terminal 7 as a judgment output.
The transfer of the cell on the transmission line is prohibited by the circuit (not shown) by this prohibition output and discarded. When there is no prohibited output, the cell is transferred. For the determination of the magnitude relationship, a valid output may be transmitted instead of the prohibited output, and the determination when (S + 1) = n can be arbitrarily set by the initial setting.

Thus, in the device of the present invention, the number of stages of the shift register of the delay circuit 3 becomes 1 / k of that of the conventional device. However, since each stage of the shift register needs the number of digits to hold the numerical value, the total hardware amount does not become 1 / k, but if k = 500 in the above example, , The amount of hardware is at least several tenths. Further, in the apparatus of the present invention, the continuous m-cell time is counted every m / k-cell time, so that it is not possible to measure a phase finer than the m / k-cell time, but there is no problem in practice.

FIG. 2 is a block diagram of the apparatus according to the second embodiment of the present invention. This second embodiment device does not transmit more than n cells over m consecutive cell hours by contract as described above,
This is used when a second condition for setting small values of ms and ns is provided in addition to a condition for setting large values for m and n. For example, not to transmit more than 300 cells over a continuous 10,000 cell hours (m = 10000, n = 300),
Do not transmit more than 3 cells in cell time (ms = 5,
ns = 3).

In this case, in addition to the configuration shown in FIG. 1, k is selected so that m / k = ms. That is, in the apparatus shown in FIG. 2, in addition to the elements described in FIG. , The second threshold
ns, and a second comparison / determination circuit for determining a magnitude relationship between the output value l and the second threshold ns.
22, and outputs the judgment output of the comparison judgment circuit 6 and the judgment output of the second comparison judgment circuit 22 to the terminal 7 via the OR circuit 23.

With this configuration, it is possible to obtain an apparatus that can set conditions for both large and small values of m and n.

This device can also be effectively handled with a small amount of hardware.

〔The invention's effect〕

As described above, according to the present invention, even if m or n is set to an extremely large value under the condition to be monitored and the condition that up to n cells are allowed within the m cell time, the hardware is increased in proportion to the value. There is no increase in the amount of hardware, and it is possible to obtain a device that can be easily handled with realistic small hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention. FIG. 2 is a block diagram of a device according to a second embodiment of the present invention. FIG. 3 is a block diagram of a conventional device. FIG. 4 is a diagram showing that the line multiplexing efficiency is improved when a large value is set as the value of m. FIG. 5 is a diagram showing that when a large value is set as the value of m, the number of gates in the conventional circuit becomes too large to cope with it. Reference numeral 1 denotes a terminal to which a monitored signal is input; 2 a cell detection circuit; 3 a delay circuit; 4 an up-down counter;
5: threshold holding circuit, 6: comparison / determination circuit, 7: terminal to which a determination output is transmitted, 10: terminal to which a cell clock signal is input, 11: frequency dividing circuit, 21: second threshold Holding circuit, 22... Second comparison / determination circuit, 23... OR circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-183939 (JP, A) JP-A-1-183938 (JP, A) JP-A-4-25255 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H04L 12 / 28,12 / 56

Claims (2)

(57) [Claims] A cell detection circuit for detecting presence or absence of a valid cell in the monitored signal in synchronism with a monitored signal; a detection output of the cell detection circuit as an addition input; The counter circuit (1
2) and the output value of this counter circuit is set as an input value and the input value is m
A delay circuit (3) sent to a delay output after (k-1) / k cell time, and the counter circuit (12)
An up / down counter (4) having the output value of the addition as an addition input, a threshold holding circuit (5) holding a threshold n, and the threshold n, the value S of the up / down counter and the The output value 1 is taken and (S +
1) A cell traffic monitoring device comprising: a comparison judgment circuit (6) for judging a magnitude relationship between n) and n. 2. The cell traffic monitoring device according to claim 1, wherein a second threshold value holding circuit (21) for holding a second threshold value ns, and a magnitude relationship between the output value l and the second threshold value ns is determined. A second comparison / judgment circuit which performs a logical OR operation of a judgment output of the comparison / judgment circuit according to claim 1 and a judgment output of the second comparison / judgment circuit. A cell traffic monitoring device comprising: