JPH04192645A - Synchronization transmission control system - Google Patents

Abstract

PURPOSE:To send a signal required for synchronization by sending a dummy data frame having a data length equal to a length of a data to be stored in a frame length register when a token returned through a ring circulatingly is detected prior to the transmission of a synchronization data frame. CONSTITUTION:The system is provided with a synchronization transmission control section consisting of a token reception detection circuit, a period counter 1, a frame length counter 2, a frame length register 3, a 1st D counter comparator 7 and a 2nd D counter comparator 8 being limit circuits. Then a node being a master station for synchronization sends a dummy data frame whose frame length is equal to a value in the register 3 at a time when a token is received and detected prior to the transmission of a synchronization data frame. Thus, the transmission start time of the synchronization data frame sent from the master station is synchronized with a routine time and when a node being a slave station generates an out of synchronism signal when the interval of timings is not within a preset allowable range. Thus, the synchronization is corrected without a delay.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data transmission control system, and in particular to a ring-shaped high-speed optical L'AN (US ANSI standard LAN fiber distributed data interface (FDDI)). Exchanging data between control devices at multiple locations at regular intervals using
Or related to applications in which multiple computers and control devices are connected via LAN and all processing devices process data in synchronized time, and synchronous transmission control methods that enable transmission of voice data, etc. that requires periodic transmission. It is.

(Prior Art) In recent years, the application of local area networks (LANs) has been rapidly progressing. Among them, the next high-speed,
ANSI-FD is gaining attention as a high-bandwidth LAN.
There is DI.

This FDDI (Fiber Distributed Data Interface)
is a 100 Mdps ring-shaped LAN system using an optical fiber as a transmission line and a transmission line control system using a token passing system, and its standardization is being discussed by the ANSIC American National Standards Institute (ANSI). Standardization of some parts has been completed. For this reason, FDDI
LSIs and protocol processing software that meet the standards are now available from semiconductor manufacturers, and the results of FDDI are attracting attention in the computer and communication industries.

On the other hand, in a token-passing LAN, transmission rights called tokens are sequentially passed between nodes in the system, and multiple nodes are prevented from transmitting at the same time. The node to which the token is received can transmit data within a preset time. Therefore, since deterministic transmission path access becomes possible, bus-type A token passing method is used.

FIG. 6 is a block diagram showing an example of the configuration of this type of FDDI LAN. In FIG. 6, each node N, -N
, are interconnected by two optical fiber cables L, -L2 whose transmission data flow directions are opposite to each other. FDDI has a transmission path control function that allows each node to arbitrate transmission requests from each node N, -Nfi interconnected in a ring according to the transmission band available on the network and acquire the right to use the transmission path. A data transmission/reception function for each node, a transmission system failure detection/failure part isolation function, and a transmission system reconfiguration function are provided.

On the other hand, FDDI provides two service classes: synchronous service and asynchronous service.

That is, the synchronization service allows a node to send a synchronization frame whenever it receives a token. Additionally, asynchronous services allow asynchronous frames to be sent only when the token is circulating fast enough.

As part of the ring initialization process, each node arbitrates a target token rotation time (TTRT) value. This means that each node requests a value that is fast enough to support the same traffic request, and the shortest value (T
OPR) is set in each node cyclic timer (TRT). Also, the Late-Ct (late counter) of each node increases each time the TRT value expires, and is cleared each time a token is received. Furthermore, if the TRT has not expired since the node previously received the token, i.e. if Late-Ct is 0, the token is considered to have reached the node within the target time, otherwise the token is considered late. be considered.

Here, if the token reaches within the target time,
The current value of TRT is set in the token hold timer (THT), TRT is reset to the TOPR value, and the timer is restarted. Then, after transmitting the synchronization frame, THT
Asynchronous frame transmission is possible for a period of time corresponding to the value. Also, if the THT expires or there are no asynchronous frames to send, the token is passed to the next node.

On the other hand, if the token is later than the target time, La
te-Ct is reset, but TRT is not. In this case, only the transmission of synchronization frames is allowed, and the token is passed to the next node after the transmission is complete.

Incidentally, FDDI was proposed as a packet-switched network that provides high-speed interconnection between mainframes, between mainframes and the mass storage systems connected to them, and between other peripheral devices, as well as low-speed interconnections such as Ethernet and MAP. It has been proposed that the LAN system be used as a backbone network to connect LAN systems.

(Problems to be Solved by the Invention) On the other hand, there is a demand for integrating audio and video data by utilizing the high bandwidth characteristics of FDDI. 8kHz
Periodic transmission is required at multiples of −125 μsec, and although the current FDDI based on the packet switching method allows data to be transmitted periodically, an accumulation of errors with respect to the fixed time occurs. In addition to these packet switching functions, ANSI has developed a new FDDI that adds circuit switching functions.
-2 standards, and it will take many years before the draft standards are established.

The purpose of the present invention is to use FDDI, which is a leading standard for the next generation of high-speed, high-bandwidth LAN, to be able to perform data transmission synchronized at a fixed time using packet transmission for FDDI, and to accommodate voice data or LAN
Time synchronization is necessary for applications in which multiple computers and control devices are connected and all processing devices process data in time synchronization, or in applications in which process data from multiple locations distant from each other is sampled simultaneously and in the same phase. It is an object of the present invention to provide a synchronous transmission control method capable of transmitting signals.

In other words, a LAN is constructed using and without compromising the inherent functions of FDDI, and its functions and performance are expanded along with the deterministic, self-healing, and scalable characteristics inherent in FDDI. The aim is to construct a compact transmission device by using a general-purpose LSI.

[Configuration of the Invention (Means for Solving the Problem) In order to achieve the above object, the present invention provides a transmission device having a configuration in which a plurality of nodes are interconnected by a ring-shaped transmission path, and a fiber distributed data interface. (FDD
I) or a synchronous transmission control method in which data is transmitted in synchronization with a fixed time using a network having a similar function, a token reception detection circuit and a timing time signal from an external source are used as transmission control means of the node. a frame length counter that counts down and resets to the cycle value counted by the cycle counter at each timing according to the timing time signal, and a frame length register that stores the frame length from the frame length counter. and a limit circuit for limiting the frame length, and the node serving as the master station for synchronization has a frame length counter at the time when the token reception detection circuit detects the reception of the token that has returned after going around the ring. The value of is held in the frame length register, a dummy data frame having a data length equal to the value held in the frame length register is transmitted prior to the synchronous data frame, and the transmission start time of the synchronous data frame transmitted from the main station is determined. I am trying to synchronize it at a fixed time.

(Function) Therefore, in the synchronous transmission control system of the present invention, by using the above-mentioned means, a LAN is constructed using the functions inherent in FDDI without impairing them, and the LAN is constructed using the functions originally provided in FDDI. By expanding the functions and characteristics along with the excellent features of determinism, self-healing, and expandability, and using a general-purpose LSI, it is possible to configure a compact transmission device.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, the configuration example of the FDDI transmission system of this embodiment is the same as that shown in FIG. 6 described above, and only the different parts will be described here.

That is, each node N, -N has two optical fiber cables L1 whose transmission data flow directions are opposite to each other.
．． They are mutually connected via L2. Also, each node N,
-N is composed of a transmission control unit that controls transmission control and equipment connected to this.

FIG. 1 is a block diagram showing an example of the configuration of a synchronization control section that is a part of the transmission control section. In FIG. 1, the synchronization control section includes a period counter (P counter) 1, a frame length counter (D counter) 2, a frame length register 3, a Pmax register 4, a Pl register 5, and an instruction decoding section. 6, a first D counter comparator 7 and a second D counter comparator 8 which are limit circuits, an out-of-synchronization detection section 9, a periodic signal generation section 10, a timing block No. setter 11, and a block No. Comparator 12;
It consists of a D initial value register 13, a P counter value holding section 14 provided between the period counter 1 and the frame length counter 2, gates 15A to 15E, and a control section 16.

Here, when the period counter (P counter) 1 receives a timing time signal (external period signal) A from the outside to the main station, it is reset and counts the period equivalent to a fixed time period. Further, the frame length counter 2 is reset to the period value counted by the period counter 1 at each timing based on the external period signal A, and counts down.

Further, the frame length register 3 stores the frame length from the frame length counter 2.

On the other hand, the P 68m register 4 holds P□. Moreover, Pl, register 5 is P,.

It is intended to hold the following. Furthermore, the instruction decoding unit 6
It decodes instructions received from the processor.

On the other hand, the first D counter comparator 7 receives the D counter value from the frame length counter 2, Pl, and P from the register 4.
This is to compare s a x. Also, the second D
The counter comparator 8 receives the D counter value from the frame length counter 2 and the 1. This is a comparison. Further, the out-of-synchronization detection unit 9 receives the D counter value from the frame length counter 2, the comparison value from the first D counter comparator 7, and the comparison value from the second D counter comparator 8. , to detect out-of-synchronization. Furthermore, the periodic signal generating section 10
The comparison value from the counter comparator 7 and the comparison value from the second D counter comparator 8 are input, and if the two do not match, a periodic signal is generated.

On the other hand, the timing block number setter 11 sets the block number of data. Also, block N
o The comparator 12 receives the data block No. from the timing block No. setter 11 and the received frame block No.
B, and if they match, the slave timing signal C
is generated. Furthermore, D initial value register 13
gives the initial value of the frame length counter 2.

On the other hand, the P counter value holding section 14 stores the period counter 1
This is to hold the P counter value of . The control section 16 also has a function of setting the P counter value of the period counter 1 when receiving the external periodic signal A in the P counter value holding section 14, and loading the frame length counter 2 with the external periodic signal A. A function that resets the value of the P counter value holding unit 14 to the frame length counter 2 and causes the frame length counter 2 to run on its own when the D counter value of the frame length counter 2 becomes zero upon detecting the interruption of the A. It has a function of controlling opening and closing of each gate 15A to 15E.

Next, the operation of the synchronous transmission control system of this embodiment will be explained using FIGS. 2 and 3.

FIG. 2 is a diagram showing the transmission timing of synchronous data frames in the main station. In FIG. 2, the P counter value of the period counter 1 is reset each time an external synchronization signal S, arrives, and counts up as time passes. Also,
The value immediately before being reset is loaded into the frame length counter 2.

That is, the time length P1 of the arrival section of the i-th external synchronization signal S becomes the initial value of the frame length counter 2 for the i+1-th section.

On the other hand, the frame length counter 2 counts down the passage of time. Now, in the i-th interval, the external periodic signal S
, the time from arrival to reception of the token is also assumed to be the time length of the dummy frame to be sent. At this time, if 1-P+-+ at is set, the synchronous data frame to be sent following the dummy frame will be sent exactly in synchronization with the timing of the external periodic signal S. In this case, Pl-11
The value of 11 is obtained by reading the value of frame length counter 2 at the time the token was received. Further, the value of d is limited to a preset tolerance range d,lll≦d1≦d, □ by a limiter circuit. At the main station, an external periodic signal S.

When the frame length counter 2 is lost, the above operation is maintained by the frame length counter 2 running on its own. In this case, the time when the D counter value of the frame length counter 2 becomes zero corresponds to the arrival time of the external periodic signal S.

On the other hand, FIG. 3 is a diagram showing a method for detecting out-of-synchronization in a slave station. In FIG. 3, the period counter 1 and the frame length counter 2 are different from each other except that the arrival time of the timing frame sent from the main station is changed to the external periodic signal S.
The operation is the same.

That is, the slave station monitors the PI and determines the preset allowable minimum timing interval from Pal. , the allowable maximum timing interval is Pl, 8, and if pp, .

Next, the above operation will be explained in more detail using FIG. 4.

Since both the master station and the slave station are configured with common hardware, the distinction between the master station and the slave station is set by the processor within the node. Although there may be a plurality of nodes that can serve as the master station in the transmission loop, in reality, only the - node becomes the master station and performs synchronization control using a special master station determination method.

That is, in the node that has become the master station, the processor writes P□ and dl to register 4. , P, d in fi register 5,
, 8 are loaded. The operation of the synchronization control section begins when the period counter 1 and frame length counter 2 are enabled by the processor. By providing data in the format shown in FIG. 4, for example, in the transmission memory, the data can be transmitted correctly to the LSI that controls the transmission of the transmission control unit. Therefore, by using a register instead of a memory for the part of the transmission word count shown in FIG. can be configured. At this time, synchronization control can be performed by setting the value given by the register to a value corresponding to the difference between the token reception time and the timing signal time.

The period counter 1 is reset each time the external synchronization signal A arrives, and counts up as time passes. Further, the P counter value immediately before being reset is loaded into the frame length counter 2. That is, the time length P of the i-th section,
becomes the initial value of the frame length counter 2 for the i+1th section. The frame length counter 2 counts down the passage of time.

When a token is received, the D counter value of the frame length counter 2 is exactly the value corresponding to the difference between the token reception and the timing signal time, so this value is sent to the frame length register 3 and the transmission control unit is activated. The controlling LSI reads the frame length register 3 as the number of words to transmit the dummy frame. The D counter value of the frame length counter 2 at the time of token reception is determined by the first D counter comparator 7, which compares the D counter value with Pl,8, and the second D counter comparator 7, which compares the D counter value with P11111. D counter comparator 8
Therefore, when Dad□8, the value of dmat is in frame length register 3, and Dd4. .

At this time, the values of d m + , , , etc. are set in the frame register 3, respectively. This makes it possible to limit the length of the dummy frame. Furthermore, when the external periodic signal A is interrupted, the operation of the periodic counter 1 is stopped and the frame length counter 2 is allowed to run freely, thereby continuing the synchronous control. The time period in this case is held in the P counter value holding section 14.

On the other hand, in the slave node, P
max Register 4 has Pam, P +ml. The P1ns timing block number register 5 is loaded with the reception block number of the timing frame sent from the main station. The operation of the synchronization control section begins when the period counter 1 and frame length counter 2 are enabled by the processor. When the slave station receives the frame, the value indicated by the reception block NoB is
Timing block N in block NO comparator 12
o.

It is compared with the value in the register 11, and if the two are equal, a slave timing signal C is generated. Further, the operations of the period counter 1 and the frame length counter 2 are similar to those of the main station except that the slave timing signal C is used instead of the external period signal. When the slave timing signal C is subsequently generated, the value of the frame length counter 2 is changed to the D counter value and P am! a first D counter comparator 7 that compares the
A second D counter comparator 8 compares the D counter value and P +++1m, respectively, so that D > P, +.

Alternatively, when the D counter 2 becomes zero once and starts counting down again from the previous initial value and D<Pssi, an out-of-synchronization signal is generated.

Note that in both the main station and the slave station, a periodic signal is transmitted from the periodic signal generator 7 to the processor once per period.

As described above, in the synchronous transmission control method of this embodiment, a transmission device that has a configuration in which a plurality of nodes N1 to Nfi are interconnected by a ring-type transmission path, and a fiber distributed data interface (FDDI)* or its equivalent is used. In a synchronous transmission control method that uses a network with similar functions to perform data transmission in synchronization with a fixed time, the transmission control unit of a node includes a token reception detection circuit, a period counter 1, a frame length counter 2, and a frame long register 3,
A synchronous transmission control unit consisting of a first D-counter comparator 7 and a second D-counter comparator 8, which are limit circuits, is provided, and a node serving as a synchronization main station has a frame length register at the time when a token is received and detected. By transmitting a dummy data frame with a frame length of 3 before the synchronous data frame, the transmission start time of the synchronous data frame transmitted from the master station is synchronized with the fixed time, and the node that becomes the synchronized slave station , the arrival interval of timing frames is monitored, and if the timing interval is not within the range of a preset allowable minimum timing interval and an allowable maximum timing interval, an out-of-synchronization signal is generated externally.

Therefore, by using the frame length counter 2 that counts the time corresponding to a fixed time period, when the main station receives a token, it is possible to immediately detect the difference in reception time as the value of the frame length counter 2. By directly converting this value into a dummy data frame length using hardware, synchronization correction can be performed without delay. This makes it possible to perform fixed-time transmission without cumulative time errors even in similar transmission equipment that uses a packet-switching method such as the FDDI transmission method, and for data that requires periodicity such as voice transmission. This also makes it possible to transmit . In addition, a LAN can be constructed using the inherent functions of FDD I without sacrificing them, and FDD
By expanding the functions and characteristics of I, along with its inherent excellent characteristics of determinism, self-healing, and expandability, and using a general-purpose LSI, it becomes possible to construct a compact transmission device.

In the above embodiments, the transmission line may be a coaxial cable, space transmission, or the like, or may be configured in a mixed manner with an optical fiber cable.

Furthermore, in the above embodiment, as the data structure of the dummy data frame, dummy data corresponding to the maximum dummy frame length is prepared as shown in FIG.
How to prepare the number of data for N, and when the transmission/reception control circuit starts transmitting the dummy data frame and reads the transmitted data from the memory, the memory address is incremented one by one, but the memory for reading the data for LEN is explained. By always using the same address, it is possible to reduce the memory capacity for storing dummy data frame transmission data.

[Effects of the Invention] As explained above, according to the present invention, FDDI, which is a leading standard for next-generation high-speed, high-bandwidth LAN, is used.
It is possible to transmit data synchronized to a fixed time using packet transmission to the DI, and it is also possible to accommodate audio data, or connect multiple computers and control devices using FDDILAN so that all processing devices process data in synchronized time. Synchronous transmission control method that can transmit time-synchronized signals necessary for applications such as applications that sample process data (e.g., instantaneous values of voltage, current, etc.) at multiple points far apart from each other at the same time and in the same phase. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the transmission timing of the synchronized data frame of the master station in the same embodiment, and FIG. 3 is a method for detecting out of synchronization of the slave station in the same embodiment. 4 is a diagram showing a general configuration example of the transmission control word in the same embodiment. FIG. 5 is a diagram showing a configuration example of the transmission control word of the main station in the same embodiment. FIG. 1 is a block diagram showing an example of a LAN system configuration. 1... Period counter (P counter), 2... Frame length counter (D counter), 3... Frame length register, 4... Pl, 8 register, 5... P m l
n register, 6... instruction decoding unit, 7... first D counter comparator, 8... second D counter comparator, 9... out of synchronization detection unit, 10... periodic signal Generation unit, 11... Timing block NO setting device, 12
...Block No. comparator, 13...D initial value register, 14...P counter value hold unit, 15A-15
E...Gate, 16...Control unit, N1-N,...
node. Applicant's agent Patent attorney Takehiko Suzue Figure 4 Figure 5 Figure 5

Claims (5)

[Claims] (1) A transmission device that has a configuration in which multiple nodes are interconnected through a ring-type transmission path, and uses a fiber distributed data interface (FDDI) or a network with similar functions to transmit data in synchronization at a fixed time. In the synchronous transmission control method, the transmission control means of the node includes a token reception detection circuit, a period counter that receives a timing time signal from the outside and counts the period equivalent to a fixed time period, and a periodic counter that receives a timing time signal from the outside and counts the period equivalent to a fixed time period. A transmission control means comprising a frame length counter that resets and counts down to the cycle value counted by the cycle counter, a frame length register that stores the frame length from the frame length counter, and a limit circuit that limits the frame length. , In the node that becomes the synchronization main station, the value of the frame length counter at the time when the token reception detection circuit detects reception of the token that has gone around the ring and returns is held in the frame length register, and is stored in the frame length register. A synchronization system characterized in that a dummy data frame having a data length equal to a held value is transmitted prior to a synchronous data frame, and the transmission start time of the synchronous data frame transmitted from the main station is synchronized with a fixed time. Transmission control method. (2) In the node that becomes the main station of the synchronization, set a limit value on the frame length counter, and if the synchronization is extremely out of sync, limit the data length of the dummy data frame to a constant value, and if the synchronization is small. 2. The synchronous transmission control system according to claim 1, wherein the synchronous transmission control system is configured to perform correction if the case occurs. (3) In the node serving as the synchronization main station, when the timing signal from the outside is lost, the timing time signal is generated by itself with the period being the value stored in the period counter immediately before the loss. The synchronous transmission control method according to claim (1). (4) The slave node for synchronization generates a timing signal when the block number in the received frame is equal to the preset timing frame block number, and resets the frame length counter to the cycle value counted by the cycle counter. However, when the timing signal is generated again and the timing interval is not within the range of the preset allowable minimum timing interval and allowable maximum timing interval,
2. The synchronous transmission control system according to claim 1, wherein the synchronization loss is notified to the outside. (5) When a data frame equal to a preset timing frame block number is lost, the slave node for synchronization generates a timing time signal by itself with the period being the value stored in the period counter immediately before the loss. The synchronous transmission control system according to claim 1, characterized in that: