JPH04192186A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce a current consumption at the time of nonselection of chip by dropping the voltage of power source inside of a chip only when the chip is in nonselection. CONSTITUTION:When a pin 2 for chip select input is in the 'H' state, the inside of chip is not in operation. At this time, an inside power dropping circuit 6 is operated to drop the voltage of power source voltage level supplied from a power voltage supplying pin 1, and the dropped power is supplied to a peripheral circuit 4 and a memory cell array 5. Since the power source voltage of circuit 4 is also dropped at the unoperating time, a pass-through current is reduced for even the device wherein the initial stage of an address input is not cut such as a SRAM, etc., for which high speed access is required, then the current consumption including the current flowing in a high resistance of memory cell is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an internal circuit configuration for suppressing standby power consumption of a semiconductor memory device.

[Conventional technology]

In recent years, semiconductor memory devices have made remarkable progress, with efforts toward higher integration, higher speed, and lower power consumption.

FIG. 2 is a schematic block diagram showing an example of the configuration of a conventional SRAM. In Figure 2, (1) is a power supply voltage supply pin for supplying power to the SRAM circuit, (2) is a chip select input pin that controls internal chip operation and non-operation, and (3) is a pin that controls circuit operation. CS buffer circuit to control,
(4) is a peripheral circuit for reading and writing data in memory cells, and (5) is a memory cell array.

Next, the operation will be explained. The voltage supplied from the power supply voltage supply bin (1) is supplied internally as it is without changing the potential in the internal circuit.

Also, the 4 input from the chip select input bin (2)
No. N is the peripheral circuit (
4) It generates signals to control the operations and acts on each circuit. For example, when the H signal is input, the signal (hereinafter referred to as the C8 signal) that controls the operation or non-operation of the chip that is input from the chip select input pin (2) is sent from the CS buffer circuit (3) to control the operation or non-operation of the chip. A signal is generated, and the peripheral circuit (4) stops operating.

Medium-speed SRA that does not place much emphasis on speeding up access time
In M, the control signal from the CS buffer circuit (3) is also input to the address input first stage circuit for selecting an arbitrary memory cell to suppress the through current, or in SRAM that requires high-speed access, the address input first stage circuit When the signal from the CS buffer circuit (3) is cut, the access becomes C
Normally, only the first stage of address input is not controlled by the C8 signal, since the processing is delayed due to the 3 signals being used. Therefore, even when not in operation, a through current is flowing in the input first stage circuit.

Furthermore, if the memory cells forming the memory cell array (5) are of a high resistance load type, when the chip is in an inactive state, the current flowing from the power supply voltage supply bin (1) through the high resistance or the power supply current flowing through the high resistance. becomes. In other words, the standby current consumption for an SRAM that does not emphasize access time is only the current flowing through the high resistance mentioned above, and the standby current consumption for an SRAM that emphasizes high-speed access time is the through current of the address input first stage circuit. , is the sum of the current flowing through the high resistance of the memory cell.

[Invention or problem to be solved]

Since the conventional SRAM is configured as described above, there have been problems in that the memory capacity has increased rapidly and the current when the chip is not selected has increased in response to the recent trend toward higher integration.

The present invention was made in order to solve the above-mentioned problems, and an object thereof is to obtain a semiconductor memory device that can sufficiently reduce current consumption during non-operation despite a large capacity memory. do.

[Means to solve the problem]

The semiconductor memory device according to the present invention includes an internal power supply step-down circuit that steps down the power supply level supplied to the internal circuit when a chip is not selected in response to a chip signal for activating a memory element.

[Effect]

The power supply voltage of the internal circuit in this invention is the power supply voltage Vcc applied from the outside during operation, whereas when it is not operating, the potential supplied by the internal power supply voltage step-down circuit is lower than that during operation. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) to (5) are the same as those shown in the conventional example of FIG. 2, and therefore their explanation will be omitted. (6) steps down the voltage level given from the power supply voltage supply pin (1),
This is an internal power supply step-down circuit that supplies stepped-down power supply voltage to each internal circuit.

Next, the operation will be explained.

When the chip select bin (2) is in the L state, the inside of the chip is in operation. At this time, the internal power supply step-down circuit (6) does not operate, and if the power is supplied from the power supply voltage supply pin (1) or the logic that is transmitted inside the chip is assembled in the internal power supply step-down circuit (6). , which is the same as normal operating condition. When the chip select input bin (2) is in the H state, the inside of the chip is inactive. At this time, the internal power supply step-down circuit (6) operates, steps down the power supply voltage level applied from the power supply voltage supply pin (1), and supplies the reduced power to the peripheral circuit (4) and memory cell array (5). be able to.

During non-operation, the power supply for the peripheral circuit (4) is also stepped down, so even in SRAMs that require high-speed access and devices where the first stage of address input is not cut, the through current is reduced and the high voltage of the memory cell is reduced. The current consumption, together with the current flowing through the resistor, is reduced.

In the above embodiment, as a means for operating the internal power supply step-down circuit (6), the control signal from the CS buffer circuit (3) is applied, or the internal power supply step-down circuit (6) is operated directly from the input of the power supply voltage supply pin (1). A method of operating the circuit (6) may also be used.

〔Effect of the invention〕

As described above, according to the present invention, since the voltage of the power supply inside the chip is reduced only when the chip is not selected, the current consumption when the chip is not selected can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram showing the configuration of a conventional general SRAM. In the figure, (1) is the power supply voltage supply pin, (2) is the chip select input pin, (3) is the CS buffer circuit, and (4) is the chip select input pin.
) is a peripheral circuit, (5) is a memory cell array, and (6) is an internal power supply step-down circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A semiconductor memory device comprising an internal power supply step-down circuit that steps down a power supply voltage supplied to an internal circuit when a chip is not selected in response to a chip select signal for activating a memory element.